EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces

Transcription

1 EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture 23 Case Studies Disk Drive Read/Write Channels Borivoje Nikolić April 13, Announcements Homework #3 (the last one!) posted, due in 10 days Feedback on project, ed to you today 2

2 Outline Wrap up Ethernet Disk-drive signal processing 3 Marvel of Technology 32

3 Disk Drives 1956 IBM engineers in San Jose introduced the first computer disk storage system The 305 RAMAC (Random Access Method of Accounting and Control) could store five million characters (five megabytes) of data on 50 disks, each 24 inches in diameter. 33 Today s Disks Hitachi (IBM) Travelstar 70 Gb/in 2 Experimental densities: 100+Gb/in 2 ; every square inch of disk space could hold 12 GB -- nearly as much data as a three inch diameter DVD-ROMs. (4.7 GB per surface) or 20 CD-ROMs (each 650 MB). Desktop drives 300 GB Notebook drives 80 GB Microdrive (1-inch) > 4 GB. 34

4 Trends in Magnetic Disk Drives Exponential growth in capacity is due to: reduction of head flying height reduction of the gap size in the head reduction of the media thickness advanced signal processing methods advanced digital integrated circuits Areal Density [Mb/in 2 ] Gb/in 2 Demo Areal density of data in disk drives: Super Paramagnetic Limit 30Gb/in 2 Demo 3 Gb/in 2 Demo 30% CGR 60% CGR Year 35 IBM s Areal Densities 36

5 Areal Density Trends Areal Density (Mbits/sq. in.) MR Head/ PRML Technologies 30% CGR 60% CGR GMR Head 0.01 H.Thapar Time 37 Datarate Trends in Disk Drives Data rate increase through technology scaling Data Rate [Mb/s] Data rate trends in read channels Year Source: ISSCC + vendors web sites 38

6 Flight Height Rotation speeds: rpm 39 Price Trends 40

7 Magnetic Recording Fundamentals Magnetic Disk Track Recording Magnetization Levels Detected signal in the Head 41 Magnetic Recording Fundamentals Increased recording density results in: reduced peak amplitude peak shift Reduced Amplitude Isolated Pulses Superposed Pulses Peak Shift 42

8 Lorentzian Pulse 1 Lorentzian: s( t) = 2 2t 1+ PW50 Amplitude of Step Response PW Normalized Time t/pw Bandlimited Channels Spectral control (ISI control) SNR limitation Towards Shannon capacity Going to 1Tb/in 2 density will lower the SNR by another 6dB Equalization - Partial response Channel coding - Trellis/Parity coding Combined coding and Equalization - Iterative coding 44

9 Signal Equalization Lorenzian Pulse () t = 2 l 2t 1+ PW 50 Equalization (1 D)(1+D) n PW 50 User density = PW 50 /T 1 (1-D)(1+D) (1-D)(1+D) 2 (1-D)(1+D) PR4 EPR4 E 2 PR Signal Response Simulated readback signal User density = 1.4 User density = 3.0 Recording Channel Input/Output PW50/T = 1.4 Recording Channel Input/Output PW50/T = 3.0 Amplitude Amplitude Time Time 46

10 Amplitude Spectra A m plitude Normalized Frequency pw50/t=1.0 pw50/t=1.4 pw50/t=1.8 pw50/t=2.2 pw50/t=2.6 pw50/t= Equalization Targets Magnitude EPR4 (n=2) E 2 PR4 (n=3) Frequency PR4 (n=1) 48

11 Read Channel Building Blocks 49 Eye Diagrams PR4 EPR4 50

12 Maximum Likelihood Detection 51 The Viterbi Detector Equalization Response Memory States PR4 1 D (2) EPR4 (1 D)(1+D) E 2 PR4 (1 D)(1+D) Alternative is to use DFE; not used in practice because of error propagation 52

13 Error Distances Channel input error sequence: e x ( D) = xˆ( D) x( D) Channel output error sequence: e y ( D) = yˆ( D) y( D) Squared Euclidean error distance: d 2 2 y = ( D) e ( D) h( ) 2 ( E) = e D x 53 Error Probability Probability of misdetection of sequence S k by S k is a function of error distance, d K Performance of the PRML system is determined by the minimum distance error events P e K dmin d Q 2σ min Error event distance spectrum Q () - Error function 54

14 Signal Processing Trends Density (2,7) TURBO CODING d=0 or n d=1 PRML EPRML E PRML, GE n PRML PARITY CODING d=0 (1,7) MFM PEAK DETECT H. Thapar ANALOG DIGITAL Time 55 Current Implementation Approaches Function System Architecture Equalization ADC Detection Gain control Timing Recovery Approach EPR, E 2 PR, or generalized E 2 PR with 16/17 or 8/9 codes Digital FIR, analog FIR, or continuous-time filter Flash, typically 6 bits Full Viterbi detector or Viterbi detector with post-processor First-order loop with digital or analog integration Second-order PLL using synchronous or interpolated timing 56

15 Parity-Coded Channel Viterbi Detector Delay r k P(D) - + x k n k Check Parity Error Correlate Correct Error Detect Error Maximum Data Determine Likely Error Location 57 Architecture #1 READ SIGNAL VGA Low pass filter FIR Eq. VITERBI DETECT TIMING CONTROL DETECTED DATA Key Features: All analog GAIN CONTROL SSI,

16 Architecture #2 READ SIGNAL VGA Low pass filter FIR Eq. ADC VITERBI DETECT TIMING CONTROL DETECTED DATA Key Features: Analog FIR equalizer 40-levels in ADC GAIN CONTROL Lucent 59 Architecture #3 READ SIGNAL VGA Low pass filter ADC FIR Eq. TIMING CONTROL VITERBI DETECT DETECTED DATA GAIN CONTROL Key Features: Digital FIR equalizer Full 6-bit ADC Dominant: TI (SSI), Marvell, Datapath, IBM 60

17 Architecture #4 READ SIGNAL VGA Low pass filter ADC FIR Eq. Interpolation filter VITERBI DETECT TIMING CONTROL DETECTED DATA GAIN CONTROL Key Features: Digital FIR equalizer Interpolated timing recovery Full 6-bit ADC with >(1/T) samples/sec. Cirrus Logic 61 Design Examples 1st generation chip 170 Mb/s, 1.3W, 5V, 27.5mm 2, 0.56mm Published in 1997 ISSCC Paper nd generation chip 240 Mb/s, 1.4W, 5V, 18.5mm 2, 0.54mm Unpublished 3rd generation chip 400 Mb/s, 1.1W, 3.3V, 13.5mm 2, 0.29mm Published in 1999 ISSCC Paper 2.2 H. Thapar, et al, CICC 98 62

18 Analog Front-End Pre-equalization in analog domain 63 Design Challenges One of the first Systems-on-a-Chip (SoC) > 2Gb/s rate Power limited (<2W, preferably 1W), inexpensive (<$2.5) Single step vs. lookahead/parallel Reduced SNR, complex detection Integration with controller gives opportunities for more powerful coding and processing Iterative decoders (Turbo, LDPC) 64

19 Architectural Choices Equalizer 6-10 taps, >1Gb/s Choices of interleaving, pipelining, recoding, carry-save Infinite speed at the expense of power 65 Architectural Choices Viterbi Decoder state, trellis coded with prostprocessor, variable equalization targets Radix-2 vs. Radix-4, ACS vs. CSA Bit-level pipelining 66

20 Future Signal Processing SNRs will continue to decrease Iterative decoding LDPC based Can we control the byte error rate? Complexity? Timing recovery at low SNRs Vertical recording is already back Multi-track recording? 67 IBM s Advanced Storage Roadmap 68

21 Holographic Storage 69 IBM s MIllipede 70