Direct and Recursive Filters

Transcription

1 EE219A Spring 2008 Special Topics in Circuits and Signal Processing Lecture 11 Direct and Recursive Filters Dejan Markovic Annoucements Homework 2 Due Wed, May 7 You need SynDSP tool stop by my office to get it Next Monday Simulink-to-hardware mapping Lecture/tutorial by R. Nanda Synplicity DSP training Fri, May 16 (9am-5pm) Slide 2

2 Multiplier-less FIR Filter Implementation Power-of-two multiplications are obtained for free by simply shifting data busses. Example of CSD multiplier coefficient implementation: Result is a low-complexity multiplier-less FIR filter with little performance degradation from the ideal filter response. Slide 3 FIR Filter Architecture Transpose direct form has pipelining built-in Critical path contains fewer adder delays Slide 4

3 FIR filter, direct form y Transversal Filter [ n] = a x[ n] + a x n 1] + a x[ n 2] a x[ n N 1] 0 1 [ 2 N + [From Prof. B. Nikolic, UCB] Slide 5 Critical Path Digital FIR T = T mult + (N-1)T add [From Prof. B. Nikolic, UCB] Slide 6

4 Pipelining Pipelining can be used in both digital and analog (mixed-signal) implementations to increase throughput Pipelining: Adding same number of delay elements in each forward cutset (in the data-flow graph) from the input to the output Cutset: set of edges in a graph that if removed, graph becomes disjoint Forward cutset: cutset from input to output over all edges Increases latency Register overhead (power, area) Slide 7 Pipelining 3-tap FIR [From Prof. B. Nikolic, UCB] Slide 8

5 Optimizing Retiming x(n) + 4D + x y(n) a Y(n) = x(n) + ay(n-4) + c t critical = 2*Tadd + Tmult Which Retiming Solution Better? c x(n) + D x y(n) a x(n) + D x y(n) a 2D + D D + 2D c t critical = Tmult (I) c t critical = Tmult (II) Slide 9 Optimizing Retiming The problem complicates if multipliers support variable pipeline depth x(n) + 2D D + D y(n) a t critical = Tmult / 2 + Tadd c y(n) x(n) + D D + 2D a t critical = Tmult / 3 + Tadd c Pipelining must be taken into account when retiming to get more optimum results Slide 10

6 Pipelined Direct FIR Critical path T = T mult + T add [From Prof. B. Nikolic, UCB] Slide 11 FIR Filter Implementations Slide 12

7 Adders form a tree Multi-Operand Addition T = T mult + (log 2 N)T add [From Prof. B. Nikolic, UCB] Slide 13 Multi-Operand Addition Using 3:2 or 4:2 compression Optional pipelining, 1-2 stages [From Prof. B. Nikolic, UCB] Slide 14

8 Transposing FIR Transposition: Reversing the direction of all the edges in a signal-flow graph, Interchanging the input and output ports Functionality unchanged Slide 15 Transposed FIR Represent as a signal-flow graph [From Prof. B. Nikolic, UCB] Slide 16

9 Transposed FIR Critical path shortened Input loading increased T = T mult + T add [From Prof. B. Nikolic, UCB] Slide 17 Data Flow Graph to Optimized Hardware In D D D [Rashmi Nanda] x x x x Out Matlab Simulink Optimizer Lower Area Low Energy, high throughput Higher speed Pipeline Registers Transposed Architecture Time Multiplex Time Multiplex Parallel Parallel Retime/Pipeline Slide 18

10 Optimization Strategy Architectural Optimization Environment Simulink Scheduling Retiming Pipelining Parallelism Control Logic Infrastructure to support above transformations Synthesis Gate Sizing Carry Save Power Estimation Interface between Simulink and Cadence backend tools for synthesis. Support for gate sizing, carry save optimizations and power estimation. Post Synthesis Vdd Scaling Power Estimation E-A-D Space Slide 19 Example: 16-tap FIR Filter Retiming, CSA optimization and scheduling Energy (pj) [log scale] 10 1 N=2 N=2 / retimed Ref. Ref. / retimed Ref. no CSA Lat + Lat + / ret. 166 M 125 M 100 M M = Ms/s Vdd 516 M 395 M 350 M 300 M 250 M 187 M 623 M Area (µm 2 ) x 10 4 Carry-Save (CSA) optimizations improve throughput and area, retiming improves throughput, scheduling improves area Slide 20

11 Parallel FIR Feed-forward algorithms are easy to parallelize Processing element representation of a transversal filter a 1 x[n] x[n-1] x[n-2] 0 a 0 a 1 a 2 y[n] Processing element Transversal filter [From Prof. B. Nikolic, UCB] Slide 21 Parallel FIR Two parallel paths Two cycles to complete operation Can be extended to more Two parallel path FIR Processing element [From Prof. B. Nikolic, UCB] Slide 22

12 Formal Approach: Unfolding FIR x(n) d c b a D D D Y(n) = ax(n) + bx(n-1) + cx(n-2) + dx(n-3) y(n) t critical = Tadd + Tmult x(2m) x(2m+1) d c b a Y(2m+1) = ax(2m+1) + bx(2m) + cx(2m-1) + dx(2m-2) Y(2m) = ax(2m) + bx(2m-1) + cx(2m-2) + dx(2m-3) + D + + D + d dc b da D + + D y(2m+1) y(2m) t critical = Tadd + Tmult t critical/iter = t critical / 2 Throughput Doubles!! [Rashmi Nanda] Slide 23 Energy Efficiency (GOPS/mW) Result of Unfolding Automated exploration of optimized architecture options 6 16-tap FIR filter (90nm CMOS) 0.5V 0.47V 0.39V Ref V 0.5V P=2 0.57V P=4 1 1V P=5 0.73V P=8 1V P = Area (µm 2 ) x 10 5 Parallelism improves throughput or energy-efficiency 0.36V 0.4GS/s 1GS/s ~10x tuning range Slide 24

13 Unfolding Describe multiple iterations of DFG Generate Parallel Architectures for high throughput or low power Unfolding recursive DFG does not yield much benefit since register count in loops remains constant Feed forward networks are primary targets for unfolding y(n) [Rashmi Nanda] x(n) + x a Y(n) = x(n) + ay(n-1) D t critical = Tadd + Tmult x(2m) x(2m+1) + + D* = 2D y(2m) y(2m+1) x x a a Y(2m) = x(2m) + ay(2m-1) Y(2m+1) = x(2m+1) + ay(2m) t critical = 2*Tadd + 2*Tmult t critical/iter = t critical / 2 Throughput Remains Same Slide 25 Example #2: UWB Digital Baseband 80% of power Slide 26

14 Starting Point: PMF Block, P1 (Direct Mapped Design) 1x Slide 27 Wiring up Blocks ADD_LINE EXAMPLE add_line('sys-name', 'block1/portx, 'block2/porty') >> add_line('connecting', Counter/1', 'Register/1') Slide 28

15 Wiring up Blocks (Cont.) >> add line('connecting', 'Register/1', >> add line('connecting', 'Constant/1', Slide 29 Architecture Exploration 4 levels of Parallelism 2 levels of Parallelism 16 levels of Parallelism Slide 30

16 Parallel Transformation: PMF Block, P16 (Fully Parallel Design) Slide 31 Tradeoff Analysis Varying level of parallelism / Vdd scaling Active Power: ~ f clk x V DD 2 Leakage Power: ~ V DD 2.5 ~P Slide 32

17 Minimizing Overall Power (and Area): Parallel-4 Architecture, 0.43V Voltage (V) Power (mw) V V> P16 P8 versus P4 P8 P4 P8 has 5% lower power P1 P2 but also 38% larger area Throughput (GS/s) 1 = 333MHz (0.6 = 200MHz) P1 P2 P4 P8 P16 1.8mm 2.4mm Effective 1GS/s 0. 43V Parallel-4 filter ST 90nm CMOS A. Chang, M. Chen, D. Markovic, B. Brodersen Slide 33 Final Architecture: P4 (parallel 4) Final voltage: 0.43V Power: ~10mW Effective throughput: 1GS/s 60% power reduction compared to direct-mapped design (P1) that works at 0.68V! Slide 34

18 More Examples: Channel Equalization Slides: courtesy of Prof. B. Nikolic, UC Berkeley Link as a Communication System Communication through a band-limited channel Tx Rx Channel H(f) channel frequency Slide 36

19 Inter-Symbol Interference Effects of frequency-selective attenuation in the time domain No ISI x[nt] x[mt] = 0 m n No ISI x[nt] x[mt] 0 m n Slide 37 Channel General channel should be ISI-free Tx Rcvr Front-End Slicer/ Detector Channel ISI-free channel Slide 38

20 Equalizer Most channels are low-pass Channel Eq H(f) Channel G(f) Equalizer G(f)H(f) Channel + equalizer f Band-limited channel (w/isi) no ISI f f Slide 39 Equalizer: Amplitude + Phase 1 H(f) channel 10 G(f) Equalizer H(f) channel f 90 o G(f) Equalizer f -90 o 0 f f Band-limited channel (w/isi) no ISI Slide 40

21 Digital equalizer Receive Equalizers Mixed-signal equalizer Slide 41 Practical Digital Equalizers Mita, ISSCC 96, two parallel paths 150Mb/s 0.7µm BiCMOS Slide 42

22 Practical Digital Equalizers Moloney, JSSC 7/98, 2 parallel paths, 3:2 Wallace 150Mb/s 0.7µm BiCMOS Slide 43 Practical Digital Equalizers Wong, Rudell, Uehara, Gray JSSC 3/95, 4 parallel paths 50Mb/s, 1.2µm CMOS Slide 44

23 Practical Digital Equalizers Thon, ISSCC 95 Transposed filter, 240Mb/s 0.8µm 3.7V CMOS, 150mW Semi-static coefficients, Booth-encoded Slide 45 Practical Digital Equalizers Staszewski, JSSC 8/00 2 parallel transposed paths, Booth encoded data 550Mb/s 0.21µm CMOS, 36mW Slide 46

24 Practical Digital Equalizers Rylov, ISSCC Gb/s, 1.2W, 0.18µm domino CMOS Distributed arithmetic Slide 47 Practical Digital Equalizers Tierno, ISSCC Gb/s, 450mW, 0.18µm 2.1V domino CMOS Slide 48

25 References from Bora Nikolic R. Jain, P.T. Yang, T. Yoshino, "FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits," IEEE Transactions on Signal Processing, vol.39, no.7, pp , July R.A. Hawley, B.C. Wong, T.-J. Lin, J. Laskowski, H. Samueli, "Design techniques for silicon compiler implementations of high-speed FIR digital filters," IEEE Journal of Solid-State Circuits, vol.31, no.5, pp , May W.L. Abbott, et al, A digital chip with adaptive equalizer for PRML detection in hard-disk drives IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC 94, San Francisco, CA, Feb , 1994, pp D.J. Pearson, et al, Digital FIR filters for high speed PRML disk read channels, IEEE Journal of Solid-State Circuits, vol.30, no.12, pp , May S. Mita, et al, A 150 Mb/s PRML chip for magnetic disk drives, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC 96, San Francisco, CA, Feb. 8-10, 1996, pp , 418. D. Moloney, J. O'Brien, E. O'Rourke, F. Brianti, "Low-power 200-Msps, areaefficient, five-tap programmable FIR filter," IEEE Journal of Solid-State Circuits, vol.33, no.7, pp , July Slide 49 References from Bora Nikolic (Cont.) C.S.H. Wong, J.C. Rudell, G.T. Uehara, P.R. Gray, "A 50 MHz eight-tap adaptive equalizer for partial-response channels," IEEE Journal of Solid-State Circuits, vol.30, no.3, pp , March L.E. Thon, P. Sutardja, F.-S. Lai, G. Coleman, "A 240 MHz 8-tap programmable FIR filter for disk-drive read channes," 1995 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC '95, pp.82-3, 343, San Francisco, CA, Feb R. B. Staszewski, K. Muhammad, P. Balsara, "A 550-MSample/s 8-Tap FIR Digital Filter for Magnetic Recording Read Channels," IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp , August S. Rylov, et al, A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC 01, San Francisco, CA, Feb. 5-7, 2001, pp J. Tierno, et at, A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC 02, San Francisco, CA, Feb. 3-7, 2002, pp , 444. Slide 50

26 And Some More Examples: Adaptive Equalization Adaptive Equalizers Key technology: Non-recursive filters Linear equalizers Zero-forcing (ZF) Least Mean-Square (LMS) Nonlinear equalizers Decision Feedback Equalizers (DFE) More advanced equalizers Fractionally Spaced Equalizers (FSE) Slide 52

27 Application of Equalizers High Speed Data Transmission Time dispersive channels cause ISI Utilize equalizers to reduce ISI, achieve high data rate, and maximize the probability of correct decisions In 80 s, data rate in telephone line ~ 2400 b/s Variation in channel characteristics may be large Use adaptive equalizers that are adjustable to the channel response Mitigate multipath effects (in radio, underwater channels, etc.) Achieve data rate > 2400 b/s Slide 53 ISI and channel impulse response Deterministic channels: Nyquist Criterion violation Statistical channel: large delay spread ISI and additive noise Introduction Basic equalization principles Zero-Forcing (ZF) Cause noise enhancement Least mean-square (LMS) More robust Slide 54

28 LMS Adaptive Equalization Achieve minimum mean-square error (MMSE) Sequence of error signals: ek = zk xk 2 Objective: min E[ e k ] E[ e For real optimality: set 2 k ] = 0 cn ( k) Normal equation: K cnrrr n k) = Rxr ( k), k = 0,1, n= K Based on a block of data ( 1,2, 2,... Slide 55 LMS Adaptive Equalization (cont d) Alternative approach to minimize MSE For computational optimality Set Tap update equation: ek = zk x Step size: Good approximation if using: k Small step size Large number of iterations Error-signal power comparison: σ 2 2 LME σ ZF Slide 56

29 Decision-Feedback Equalizers To cancel the interference from previously detected symbols Pre-cursor channel taps and post-cursor channel taps Feed forward equalizer Remove the pre-cursor ISI FIR (linear) Feedback equalizer Remove the post-cursor ISI Like a ZF equalizer If previous symbol detection is correct Feedback equalizer coefficient update equation: b ( m+ 1 k + 1) = bm ( k) ek dk m Slide 57 Decision-Feedback Equalizers (cont d) Less noise enhancement compared with ZF or LMS without DFE Allows more freedom in selecting coefficients of feed foward equalizer Feed forward equalizer needs not to fully inverse channel response Symbol decision may be incorrect Error propagation (slight) Slide 58

30 Automatic Equalizer Synthesis Setup coefficients before regular data transmission begins Transmit a known training signal Apply LMS for robustness c ( k + 1) = c ( k) e r( t0 + kt nt) n n k 216 course notes Slide 59 Equalizers for QAM Systems Use QAM for higher speeds: ,400 b/s Require in-phase and quadrature-phase representation for baseband processing * cn ( k + 1) = cn ( k) ek r ( t0 + kt nt) Slide 60

31 Fractionally-Spaced Equalizers Sampling at symbol period equalizes the aliased response Sensitive to sampling phase Can oversample at higher rate (e.g. 2X faster) Avoid spectral aliasing at the equalizer input Sample the input signal of Rx at higher rate (e.g. 2X faster) Produce equalizer output signal at symbol rate Can update coefficients at symbol rate Less sensitive to sampling phase c ( k + 1) = c ( k) e r( t0 + kt nt / 2) n n k Slide 61 Equalizer Convergence To achieve fast convergence Nyquist criterion 1 = Set step size 5N taps PowerRxSignal Training mode: use larger step size Data mode: use smaller step size Stability: use leaky update equation * cn( k + 1) = (1 a ) cn( k) ek r ( t0 + kt nt) Slide 62

32 Summary Use equalizers to reduce ISI and achieve high data rate Use adaptive equalizers to track time-varying channel characteristics LMS based equalization prevail in MODEM design DFE makes use of previous decisions to estimate the current symbol FSE is resilient to sampling phase variation Properly select step size for convergence Slide 63 References S. Qureshi, Adaptive Equalization, IEEE Communications Magazine, pp. 9-16, March J. Cioffi, Digital Communication, pre-printed course reader A. Goldsmith, Wireless Communication, Cambridge, 2005 Slide 64