Low-Power Realization of FIR Filters Using Current-Mode Analog Design Techniques

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1 Low-Power Realization of FIR Filters Using Current-Mode Analog Design Techniques Venkatesh Srinivasan, Gail Rosen and Paul Hasler School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, Georgia Abstract This work demonstrates the feasibility of low-power analog FIR filters using current-mode techniques. Preliminary results from the proposed filter indicates a power consumption that is much lower than alternate digital implementations at 2MSPS making it attractive for portable applications. The FIR filter comprises of a current-mode sample-and-hold configured as a delay element followed by an analog multiplier. Results from an 8-tap linear phase filter and a 16-tap non-linear phase filter are shown to match well with the ideal filter responses. x n Z -1 Z -1 Z Z -1 w w 1 w 2 w n Fig. 1. Block Diagram of an N-tap FIR Filter. y n I. MOTIVATION FOR ANALOG FIR FILTERS Traditionally, signal processing has been performed in the digital domain. In recent times, however, analog implementations of signal processing functions are gaining popularity owing to its low-power capability [1]. Repetitive signal processing operations such as multiplication and addition are both power and area intensive in the digital domain. An analog implementation on the other hand is area and power efficient as demonstrated by an analog vector matrix multiplier (VMM) [2]. The VMM chip uses analog techniques to achieve extremely low power dissipation and floating-gate transistors are used to provide programmability. The low-power capability of analog signal processing is demonstrated in this paper with the implementation of a finite impulse response (FIR) filter. FIR filters are typically used to realize linear phase filters and matched filters. They offer full control over their frequency response through algorithms that optimally minimize various constraints and have predominantly been implemented using digital circuitry. FIR filtering is represented by, y n = M 1 m= w m x n m (1) It is clear from (1) that FIR filters primarily require a timedelay function and repetitive multiplication and addition operations. Figure 1 shows a block diagram representation of a direct form I FIR filter that implements (1). An analog implementation of the time-delay function that is low-power, accurate and area efficient is quite challenging. Voltage-mode implementations of delay chains involve the use of charge coupled devices (CCDs) [3] or switched capacitor circuits [4]. CCDs require the use of non-standard process steps while the use of switched capacitor circuits require linear capacitors that may be difficult to obtain in a standard digital CMOS process. A current-mode approach that uses switched-current techniques are advantageous on a number of counts. A switchedcurrent approach does not require linear sampling capacitors, can operate at low supply voltages and can be implemented easily on a standard digital CMOS process. Besides, a full current-mode implementation of the signal processing chain provides the addition operation for almost no extra power dissipation. Owing to Kirchoff s current law (KCL), addition is easily implemented by tying the outputs together. Using such an approach a direct form I FIR filter has been implemented. Initial results indicate a power consumption that is much lower than a corresponding digital implementation. The frequency response of the filter matches well with that of an ideal filter with 7-bit quantized coefficients making such an analog approach attractive from both a power and accuracy standpoint. Section II of the paper discusses the analog FIR filter architecture and its circuit implementation. The simulation results of an 8-tap and 16-tap filter designed on a.5µm standard digital CMOS process are presented in section III. Section IV provides a comparison between the power dissipated in the proposed analog approach and the various digital implementations. Section V concludes the work by summarizing the results. II. ANALOG FIR FILTER A current-mode analog FIR filter is implemented by designing the delay element as a chain of current-mode sampleand-holds. Multiplication is performed using a simple current mirror and addition is performed by tying all the outputs together and thereby dissipates no extra power. An FIR filter has been demonstrated using such an approach in [5]. The delay chain, however, suffers from input signal dependent charge injection that results in a distortion of the input signal /4/$2. 24 IEEE 2223

2 + _ V DD Half-Delay Element Half-Delay Element I BIAS M5 C H Input In Out In I OUT Clock V DD Out Output I IN M4 M3 (b) V REF M1 M2 I in I out I TAIL n L W M1 M2 m L W (a) (c) Fig. 2. (a) Simplified circuit schematic of the current-mode sample-and-hold used in the filter design. (b) Block diagram representation of the full-delay stage using two half-delay stages in a master-slave configuration. (c) Multiplier designed as a current mirror where the filter coefficient is implemented as a ratio of the W/L of the transistors M1 and M2. and the overall filter response. In this work, the concept of zero-voltage switching as proposed in [6] is used with the result that the delay element does not suffer from input dependent charge injection. In the following sub-sections, the delay element and the multiply and accumulate unit are described in more detail. A. Current-Mode Delay Element The delay element is implemented using current-mode sample-and-holds. A single sample-and-hold implements a delay of half a clock period. One of the non-idealities in a sample-and-hold circuit is the charge injected onto the sampling capacitor when the sampling switch opens. Charge injection has been the major limitation in current-mode sampleand-holds. Particulary severe is the input dependence of the injected charge as this leads to distortion, whereas the input independent component of the injected charge merely appears as an offset in the sampled waveform. Several techniques have been proposed to mitigate the effects of charge injection. The use of dummy switches or CMOS switches that partially cancel the charge injection has been proposed in [7]. This technique relies on the accurate matching of an nmos with a pmos switch and the precise control of the rise and fall time of the clock that drive these switches. The use of multiple clock phases that provide charge cancellation through coarse and fine memories have achieved good results [8], [9], [1]. The generation of the multiple clock phases introduces an additional design overhead. The technique of zero-voltage switching as proposed in [6] ensures an input independent charge injection and has been chosen to implement the sample-and-hold. Apart from charge injection, the finite output resistance of the sampling transistor introduces an error as well. This occurs when the drain voltage at which the input is sampled differs from that when the sample is held. It is therefore important that apart from charge injection, the drain voltage of the sampling transistor be maintained constant both during sampling and the hold phase. Zero-voltage switching creates a virtual ground for sampling at the drain of the sampling transistor, thereby minimizing the errors introduced by the finite output resistance of the transistor. Figure 2(a) shows the simplified circuit schematic of a current-mode sample-and-hold. The key to understanding the circuit operation is that the current through both transistors M1 and M2 should equal the tail current I TAIL at all times. During the sampling phase, switch transistors M3 and M4 are closed, which causes the amplifier to set the gate of M2 to a value that allows current I TAIL I BIAS I IN to flow through M2. During the hold phase, transistors M3 and M4 are turned off thereby sampling the gate voltage of M2 across the hold capacitor C H. Now, when the output switch M5 closes, the output current I OUT equals the sampled current I IN,albeit with a signal inversion. The negative feedback around the amplifier ensures that the voltage at its inverting terminal is held close to the reference voltage V REF. The switch transistor M3 therefore opens with a constant potential V REF at its source terminal, injecting a constant amount of charge onto the sampling capacitor independent of the input current. The amplifier is designed to be a simple single stage differential pair. Such a design works well as the amplifier is required to have just a modest gain of 4 db that is easily achieved using a differential pair. Besides, the power dissipation is minimized as well. Figure 2(b) shows the implementation of the full-delay stage from two half-delay stages. Cascading a second half-delay stage such that its clock is in opposite phase with the first implements a full-delay stage. This also corrects the signal inversion of the first sample-and-hold and to a first order cancels the input independent charge injection. 2224

3 B. Multiply and Accumulate Unit The current-mode multiplier is implemented as a simple current mirror where the current mirror ratio implements the filter coefficients. This results in a highly linear multiplier element. The summation is performed by simply tying the outputs of the multiplier together. Owing to KCL, currents flowing into a node automatically add up thereby realizing an accumulator without dissipating any extra power dissipation. Figure 2(c) shows a simple current mirror. The current mirror is designed by first choosing a unit aspect ratio (W/L) for both M1 and M2. Next, a mirror ratio of m/n, is achieved by scaling the aspect ratio of M2 by m and that of M1 by n. The resolution of the coefficients is now determined by the maximum value that one allocates for either m or n. For instance, assuming a maximum value of 1 for both m and n, one can achieve a total of 32 distinct coefficients. Higher resolutions are possible if larger values are used for m and n. Table I summarizes the resolution possible for different maximum value of m and n. As can be observed, the higher the maximum value of m and n, the higher is the precision to which the multiplier coefficients can be set. This however, entails an area and power penalty. Increasing the coefficient precision increases the transistor sizes and this increases the parasitic capacitances, thereby requiring a higher current to achieve a given frequency bandwidth. Also, of importance is the mean squared error (MSE) that results from the quantization of coefficients using such a technique. Maximum values of m and n correspond to a certain bit resolution and this results in a non-linear quantization. The worst resolution occurs for values of coefficients that are either close to or 1 and this results in coefficient quantization noise. In Table I, the worst case MSE due to quantization noise is also summarized for an 8-tap filter case. MSE is defined as, N=7 MSE = (w ideal [i] w quantized [i]) 2 (2) i= where, w represents the coefficient value. For the 5-bit case, a coefficient of.5 or.95 results in the maximum quantization error. Assuming an 8-tap filter with all coefficients as either.5 or.95, one gets a worst-case MSE of.2. For higher bits of precision, a similar analysis is performed by identifying the coefficients that are prone to the worst quantization error and the results are given in Table I. The multiplier structure presented in this paper is well suited for fixed filter applications where the value of the coefficients are known apriori. Programmability can be achieved by implementing the current mirror using floating-gate transistors. Such an approach was adopted in [2] with the result that the multiplier dissipates 531nW/M Hz and exhibits over 2 decades of linear range. III. FILTER IMPLEMENTATION AND RESULTS In the initial investigations, a direct form I FIR filter, also known as the tapped delay line has been designed in a.5µm CMOS process. Two different filters were implemented with TABLE I COMPARISON OF MULTIPLIER PRECISION FOR DIFFERENT MAXIMUM VALUES OF m AND n. Max m or n Bit Resolution 8-Tap Worst Case MSE 1 5 2e e e e-4 TABLE II COMPARISON OF FILTER COEFFICIENTS FOR THE 8-TAP FILTER. Ideal Non-Quantized Quantized Coefficients from the Coefficients Coefficients Filter Impulse Response the first being an 8-tap linear phase filter with symmetric coefficients. Since applications such as audio processing and nonlinear compensation of signals do not require filters with linear phase, a 16-tap non-linear phase filter has been implemented as well. The multiplier was implemented using a bit resolution of 7 bits. Figure 3 shows the simulated frequency and impulse response for the 8-tap filter and Figure 4 shows the corresponding results for the 16-tap filter. The results were obtained at a clock frequency of 2MHz. Also shown in the figures are the ideal responses for both the filters obtained from MATLAB using quantized coefficients. As can be observed, the proposed analog filter matches the ideal responses closely thereby demonstrating the accuracy of the approach. Foran8-tapfilter, the proposed analog approach dissipates a total of 13.26mW of power for a data throughput of 2 mega samples per second (MSPS). The power consumption in the present implementation is dominated by the delay lines. The delay lines consume 12.66mW of power out of the total 13.26mW for an 8-tap filter. It is evident that the multiplication and addition consume negligible power. Also, with the implementation being parallel, to a first order, the power dissipation scales linearly with the number of taps. Table II compares the ideal non-quantized filter coefficients with both the ideal quantized coefficients and that obtained from the impulse response of the analog filter. It is evident both from the Table II and figures 3(b) and 4(b) that the impulse response of the filter matches closely with the quantized version of the ideal filter. As mentioned earlier in Section II, higher precisions of 8 and 1 bits can be achieved at the expense of area and power dissipations. IV. POWER DISSIPATION COMPARISONS Low-power ASIC implementation of digital FIR filters entails a number of design choices. For instance, a symmetric 2225

4 Magnitude (db) Phase (degrees) Normalized Output Filter Tap Position Fig. 3. (a) Frequency and phase response of the designed 8-tap FIR filter plotted along with the filter response obtained using MATLAB with 7-bit quantized coefficients. (b) Impulse response of the 8-Tap filter and that of the filter response obtained using MATLAB. Magnitude (db) Phase (degrees) Normalized Output Filter Tap Position Fig. 4. (a) Frequency and phase response of the designed 16-tap FIR filter plotted along with the filter response obtained using MATLAB with 7-bit quantized coefficients. (b) Impulse response of the analog filter plotted with that of the filter impulse response obtained using MATLAB. TABLE III COMPARISON OF THE PROPOSED FILTER PERFORMANCE WITH EARLIER APPROACHES Parameter Proposed Filter ASIC [11] TI [12] FPGA (TCS) [13] FPGA (CN-RNS) [13] Analog [5] No. of Taps Sampling Frequency 2MHz 2MHz 2MHz 2MHz 2MHz 1MHz Power Dissipation 13.26mW 328mW 4mW mW 21mW 1mW Area.24mm 2.66mm 2 NA NA NA.4mm 2 Supply Voltage 5V 3V 3.3V NA NA 5V Technology.5µm CMOS.35µm CMOS.5µm CMOS NA NA 2.µm CMOS filter can be implemented using a folded FIR filter as opposed to a direct form I implementation with the result that the number of multiplication operations are reduced. Also, there exist a number of architectural choices for the multiplier itself (Booth, Wallace-Dada, Reduced glitch Booth etc.). In [11], an area and power comparison for various multiplier choices has been performed with the result that a Wallace-Dada multiplier with a signed-magnitude representation dissipates the lowest power for a direct form I FIR filter. A commercial digital filter chip has been chosen for the comparison as well [12]. The chip contains 32 multiply and accumulate units that can be used to implement either a 32- tap arbitrary phase filter or a 64-tap linear phase filter. For the sake of completeness, implementation of FIR filters on FPGAs is included in the comparison as well. The best case implementation is that of a carry-save residue number system (CS-RNS) approach as given in [13]. Table III summarizes the results of the analog FIR filtering approach and compares the performance with digital implementations mentioned earlier and with the analog implementation of [5]. From Table I, it can be observed that the 24-tap implementation of an ASIC FIR filter dissipates 328 mw of power. In comparison, the proposed analog filter dissipates, mw, a factor of 8 times lower power dissipation. 2226

5 In comparison with the commercial filter chip, the analog approach dissipates 7.5 times lower power. A 16 times power improvement is achieved when compared to a best case FPGA approach of CS-RNS, while a corresponding implementation using the conventional two s complement (TCS) approach dissipates 3 times more power than the proposed analog approach. In comparison with an earlier current-mode approach, the power dissipation is about 7.5 times lower for a sampling speed that is 2 times faster. A number of avenues exist for further lowering the power consumption of the analog approach. As pointed earlier, the delay chains consume the bulk of the total power dissipation. Future research into low-power current-mode sample-andholds is essential to further reducing the power consumption of the delay lines. Also, as can be observed from III, the current design operates on a 5V supply. Reducing the power supply will reduce the power dissipation further. This is possible as one of the advantages of a current-mode approach is the potential for low-voltage operation. [7] H. Yang, T. Fiez, and D. Allstot, Current-feedthrough effects and cancellation techniques in switched-current circuits, Proceedings of the International Symposium on Circuits and Systems, vol. 2, pp , May 199. [8] J. Hughes and K. Moulding, S 2 I: A two-step approach to switchedcurrents, Proceedings of the International Symposium on Circuits and Systems, pp , May [9], S 3 I: The seamless S 2 I switched-current cell, Proceedings of the International Symposium on Circuits and Systems, pp , May [1] C. Toumazou and S. Xiao, N-step charge injection cancellation scheme for very accurate switched-current circits, Electronics Letters, vol. 3, no. 9, pp , Apr [11] A. Erdogan, E. Zwyssig, and T. Arslan, Architectural trad-offs in the design of low power fir filtering cores, IEE Proceedings on Circuits, Devices and Systems, vol. 151, pp. 1 17, Feb. 24. [12] GC211A-3.3V digital chip, Texas Instruments Datasheet, 2. [13] G. Cardarilli, A. Re, A. Nannarelli, and M. Re, Power characterization of digital filters implemented on FPGA, Proceedings of the International Symposium on Circuits and Systems, pp. V 81 V 84, 22. V. CONCLUSIONS A current-mode analog FIR filter that dissipates much lower power than corresponding digital filters has been presented. Results from an 8-Tap linear phase and a 16-Tap nonlinear phase filter demonstrate the accuracy of the proposed implementation. The analog implementation is low power and accurate and presents a viable alternative to the digital approach. Also, fast analog-to-digital conversion that can now be avoided at the front-end presents further power savings. Currently, the analog delay elements set the power dissipation for the entire filter. Further research in low-power high speed delay elements holds the potential for even greater power reduction in FIR filters. ACKNOWLEDGEMENT The authors would like to thank Sunil Kamath, Dr. David Anderson, Venkatesh Krishnan and Sourabh Ravindran of the Cooperative Analog and Digital Signal Processing lab at Georgia Institute of Technology, Atlanta, GA for helpful discussions. REFERENCES [1] P. Hasler and D. Anderson, Cooperative analog-digital signal processing, Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 4, pp. IV 3972 IV 3975, May 22. [2] R. Chawla, A. Bandyopadhyay, V. Srinivasan, and P. Hasler, A 531nw/mhz, 128x32 current-mode vector matrix multiplier with over 2 decades of linear range, Proceedings of the IEEE Custom Integrated Circuits Conference, pp , Oct. 24. [3] D. Buss, D. Collins, W. Bailey, and C. Reeves, Transversal filtering using charge transfer devices, IEEE Journal of Solid-State Circuits, vol. 8, pp , Apr [4] Y. Lee and K. Martin, A CMOS realization of eight 32-tap transversal filters on a single IC, Proceedings of the IEEE Custom Integrated Circuits Conference, pp , May [5] G. Liang and D. Allstot, FIR filtering using switched current techniques, Proceedings of the International Symposium on Circuits and Systems, pp , May 199. [6] D. Nairn, A high linearity sampling technique for switched current circuits, IEEE Transactions on Circuits and Systems II, vol. 43, pp , Jan