Nonlinear Equalization Processor IC for Wideband Receivers and

Transcription

1 Nonlinear Equalization Processor IC for Wideband Receivers and Sensors William S. Song, Joshua I. Kramer, James R. Mann, Karen M. Gettings, Gil M. Raz, Joel I. Goodman, Benjamin A. Miller, Matthew Herman, Thomas B. Emberley, Larry L. Retherford, Albert H. Horst HPEC 2009 RESEARCH &TECHNOLOGY, INC. 23 September 2009 This work was sponsored by DARPA under Air Force Contract FA C Opinions, interpretations, conclusions and recommendations are those of the authors and are not necessarily endorsed by the United States Government. HPEC

2 Outline Introduction Nonlinear Equalization (NLEQ) applications NLEQ program objective NLEQ processor architecture VLSI NLEQ processors Performance demonstration results Summary HPEC

3 Radar High Dynamic Range Requirements for Military and Commercial Sensor Systems Radar Receiver System Example Jamming Radar Receiver System Interference + Noise Environment Jammer Target Power (db B) Noise Clutter Dynamic Range 80->100 db Small targets at or below noise level Range Radar, ELINT, SIGINT, Comm receiver systems must support high dynamic range operation To detect small targets/signals in interference/clutter environment High signal-to-noise ratio and linearity required HPEC

4 Linearity Concerns in Highly Digitized Arrays and Frequency Channelized Systems Digital Sensor Array Receiver Receiver ADC ADC Receiver e ADC Receiver Receiver ADC ADC Receiver Receiver ADC ADC Receiver ADC Digital beamforming and frequency channelization increase in-band signal-tonoise ratio (SNR) Non-linearity generated spurs and intermods can interfere with small signal detection Power Two-tone input Noise Power Two-tone input Noise Power Two-tone input Intermods Intermods Intermods Noise Frequency Frequency Frequency HPEC Receiver ADC Frequency Channelizer Frequency Channelized Receiver Power Signal In-Band Noise Out-of-Band Noise Frequency F Nyquist

5 Nonlinear Equalization (NLEQ) From Antennas LNA Digital Receiver Digital Receiver 1 Rec Sources of Nonlinearities A/D N Digital Signal Processor HPEC

6 Nonlinear Equalization (NLEQ) Digital Receiver N Digital Receiver 1 Rec A/D LNA Digital Signal Processor Sources of Nonlinearities r (db) Power Before Equalization In-Band Intermodulation Distortions Frequency (bin) HPEC

7 Nonlinear Equalization (NLEQ) Digital Receiver N From Antennas LNA Digital Receiver 1 Rec A/D Nonlinear Equalizer Digital Signal Digital Processor Signal Processor Sources of Nonlinearities Inverts Nonlinearities Power (db) Before Equalization In-Band Intermodulation Distortions Power (db) Dynamic range improvement After Equalization Frequency (bin) Frequency (bin) HPEC

8 Nonlinear Equalization (NLEQ) From Antennas Power (db) LNA Digital Receiver Digital Receiver 1 Rec Sources of Nonlinearities A/D N Before Equalization In-Band Intermodulation Distortions Nonlinear Equalizer Digital Signal Processor Inverts Nonlinearities Power (db) Dynamic range improvement Digital Signal Digital Processor Signal Processor After Equalization +20~25 db BW >1 Teraops < 2 Watts Frequency (bin) Frequency (bin) Nonlinear equalizer processor can reduce nonlinear distortion levels in analog and mixed signal circuitry Equivalent to having devices years ahead of their time HPEC

9 Outline Introduction NLEQ processor architecture Processor architecture Architecture optimization VLSI NLEQ processors Performance demonstration results Summary HPEC

10 NLEQ Polynomial Nonlinear Filter Architecture Pass-through Z -α Pass-through Σ Processing Elements Z -β β Z -β Z -β Z -β FIR X FIR FIR Z -γ 1 FIR Z -γγ 1 Z -γ 1 X X X Σ Parameters to optimize: Number of processing elements Polynomial orders of processing elements Number of taps Delay values Z -γ Ν Z -γ Ν Z Z -γ Ν Z -γ 1 Z -γ Ν HPEC

11 Wideband NLEQ Processor Parameter Optimization Z -α Pass-through Z -β FIR X Z -γ 1 Z Z -γ -γ Ν Ν HPEC Parameter selection 10 filters, 10 taps, 0-3 tap delay, 0-3 group delay, 3 pass through delay

12 Parallel NLEQ Processor Architecture Optimization Distributed Polyphase Block- Floating-Point Residue Arithmetic Architecture Low V T Dynamic Logic IC Layout Distribute P P P P P P P P P P P P P P P P Reassemble e Design Feedback (Performance Trades) Design Feedback (Performance Trades) Sub-processor Task Distribution & Sizing P P P P P P P P P P P P FIR1φ1 FIR1φ2 FIR1φ3 P P P P P P P P P P P P P P P P P P P P P P P P NLP1φ1 NLP1φ2 NLP1φ3 P P P P P P P P P P P P P P P P P P P P P P P P FIR2φ1 P P P P FIR2φ2 P P P P FIR2φ3 P P P P HPEC Design Feedback (Routing Efficiency) IC Architecture and Floor Plan Clocks I/O FIR1φ1 FIR1φN NLP1φ1 NLP1φN FIR1φ2 FIR2φN NLP2φ1 NLP2φN Buses FIRmφ1 FIRmφN NLPmφ1 NLPmφN Memory Control

13 Measured Results: PRN Signal with Amplifier & ADC Distortions Unequalized In-band Typical Response Equalized Pow wer (dbfs) intermods Harmonics Pow wer (dbfs) Non-tonal signal experiment parameters Amplifier in saturation region Max 104 included d in testbed tb system Pseudo-Random Noise (band-limited) input waveform Greater than 25 db dynamic range improvement In-band signal component is not distorted by the equalizer HPEC

14 db ement uction (db) in ur Redudu FDR Improve Spu IF NLEQ Adaptive Equalization Performance Adaptive Equalization Performance Fully Adaptive Partially Adaptive Non-Adaptive Minimal performance losses uses computationally efficient i adaptive algorithm -24 Nominal training temperature Ambient Temperature Ambient Temperature in Degrees ( o C) Celcius Characterized Max 108 device sensitivity to changes in temperature Applied adaptive equalizations Fully temperature adaptive approach achieve good performance Partially adaptive approach can achieve similar performance with much higher computational efficiency HPEC

15 Outline Introduction NLEQ processor architecture VLSI NLEQ processors Enabling technologies NLEQ4000 ultra-wideband processor IC NLEQ500 wideband processor IC Performance demonstration results Summary HPEC

16 Nonlinear Equalizer Processor IC Development Process Non-Linear Equalizer Algorithm/Architecture Distributed Polyphase Residue Arithmetic Distribution P P P P P P P P P P P P P P P P Reassemble EQ FIR Partition FIR #1 Partition FIR #2 Partition FIR #N H 1 H 2 + X(n) Y(n) H J NLEQ Signal Processor IC IC Architecture Clocks I/O FIR1φ1 FIR1φNNLP1φ1NLP1φN FIR1φ2 FIR2φNNLP2φ1NLP2φN Buses FIRmφ1 FIRmφNNLPmφ1NLPmφN Memory Control Architecture Optimization Level of Pipeline Optimal Degree Region of Polyphasi ng Throughput Density Power Efficiency Throughput Density Times Power Efficiency Power (db) 1.5 Tearops 1.2 Watts 500 MHz BW MAX108 Before NLEQ After NLEQ Low Vt Dynamic Logic HPEC Frequency Bin

17 Architectural Comparison of Pentium 4 and MIT LL Processor Dies Pentium 4 Die MIT LL Processor Die Processor Array Single processor 1000 s of parallel processors Multiple caches and memory bus Local memory only Only core runs at high speed Entire die runs at high speed General purpose processing Signal processing functions Large design team (>100) Small design team (<10) HPEC

18 Custom CMOS Circuit Design Standard Cell Full Adder Full Custom Full Adder Pre-designed logic gates only Automatic device placement and routing Large area and power consumption Custom logic and devices sizing Manual device placement and interconnect Small area and power consumption HPEC

19 Full Custom Low Threshold Voltage (V T ) Dynamic Logic Circuits Standard Cell Static Register Full Custom Dynamic Register Low V T Devices P = ½CV 2 f Charge Leakage Design Techniques Frequent refresh Bypass capacitors Signal isolation Guard rings Robust circuits Logic based computation and storage Many devices Charge based computation and storage Fewer devices Large area and power consumption Small area and power consumption HPEC

20 NLEQ4000 Processor IC Wideband NLEQ Processor IC Layout And BGA Package Up to 4,000MSPS Selectable bit widths Up to 12 bits input Up to 16 bits output LVDS and CMOS I/O Programmable coefficients Block floating point residue arithmetic Parameter (IBM 0.13um) Die Size Core 2.6 mm x 3.3 mm 266mW 706mW Chip 6mm x 6mm 453mW 1219mW HPEC

21 NLEQ500 Processor IBM 0.13µm Die BGA Up to 500MSPS Selectable bit widths Up to 18 bits input Up to 22 bits output Low voltage CMOS I/O Programmable configuration and coefficients Block floating point residue arithmetic Yield 14/15 for LowVt and 14/15 for RegVt Parameter Core I/O Chip (IBM CMOS 0.13um) Size 0.65mm x 1.4mm N/A 2.2mm x 2.2mm 6mW 19mW* 25mW* (Vdd=0.6V) (Vdd=1.2V) 122mW 121mW* 243mW* HPEC *With 50 Ohm Load Termination

22 Outline Introduction NLEQ processor architecture VLSI NLEQ processors Performance demonstration results S Summary HPEC

23 MAX108 Demonstration Results MAX108 ADC with NLEQ4000 Without NLEQ4000 NLEQ4000 MAX108 With NLEQ4000 ~21 db linearity improvement demonstrated with NLEQ4000 IC at 1.5GSPS HPEC

24 Measured NLEQ Performance Improvement for Other ADCs Interleaving Architecture ~1 GHz Improved ~17 db Folding Architecture 1.5 GHz Improved ~13 db Flash Architecture ~1.3 GHz Improved ~12 db National Atmel AT84AS008 Entire Receiver Chain 30 MHz BW Improved ~12 db HPEC Maxim 109 LTC 2209

25 X-Band Receiver-on-Chip (RoC) Development Based on NLEQ DSP BPF LO BPF MAX108 Top View ADC NLEQ RoC Bottom View ADC LNA Mixer IF Amp Integrated RoC Die 360mW Linear dynamic range limited by the final IF amplifier NLEQ DSP to linearize the amplifier and ADC High performance and low power achieved with new analog/digital co-design paradigm Single die receiver implementation being explored NLEQ HPEC

26 Summary Linearity enhancement required by DoD/commercial sensor/receiver applications Phased array sensors/receivers Frequency channelized sensors/receivers MIT LL has developed high-throughput low-power nonlinear equalization signal processor ICs Massively yparallel systolic architecture Polyphase distributed arithmetic processing Block floating point residue number arithmetic Full custom low-threshold-voltage dynamic logic Successful demonstration results >20 db linearity improvement NLEQ4000 Up to 4GSPS, <1.25W Up to 12 bit ADCs NLEQ500 Up to 500MSPS, <0.25W Up to 18bit ADCs HPEC