A 65nm CMOS RF Front End dedicated to Software Radio in Mobile Terminals
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1 A 65nm CMOS RF Front End dedicated to Software Radio in Mobile Terminals F. Rivet, Y. Deval, D. Dallet, JB Bégueret, D. Belot IMS Laboratory, Université de Bordeaux, Talence, France STMicroelectronics, Crolles, France
2 OUTLINE Software Radio in Mobile Terminals A Sampled Analog Signal Processor Principle and System Analog Discrete Electronics Modeling Results Perspectives Conclusion 2
3 OUTLINE Software Radio in Mobile Terminals A Sampled Analog Signal Processor Principle and System Analog Discrete Electronics Modeling Results Perspectives Conclusion 3
4 Classical receiving chain 1 chain per standard = 7 to 8 chips in a mobile terminal TV GSM DCS f carrier f carrier 4 UMTS/WiFi frequency frequency
5 Software Radio receiving chain SR receiving chain A/D conversion imposes a high power consumption at RF frequencies and high resolution A total SR receiving chain dedicated to mobile terminals is expected to be feasible in 15 years But Some constraints Effective number of Bits 5
6 OUTLINE Software Radio in Mobile Terminals A Sampled Analog Signal Processor Principle and System Analog Discrete Electronics Modeling Results Perspectives Conclusion 6
7 How to make it feasible 2 Ideas are envisaged: An ANALOG circuit to work directly at RF Frequencies (10GHz at least) Switch from time-domain to FREQUENCY-domain signal processing 2 ways to challenge these ideas An Analog Processor working with VOLTAGE SAMPLES A time to frequency domain conversion ALGORITHM A Sampled Analog Signal Processor (SASP) is chosen to interface antenna and A/D conversion Proposed SR receiving chain 7
8 Software Radio Architecture A principle: The Frequency Translation A way to do it: an Analog Fast Fourier Transform A pipelined FFT is chosen Radix-4 Butterfly algorithm Generic modules are to be implemented analogicaly 8
9 Software Radio Architecture Analog RF signal processing: Anti aliasing filter Sampling (frequency is the parameter of reprogrammability) Avoid interferences and improve FFT calculation Discrete Time signal processing Windowing FFT calculation Spectrum output through voltage samples Signal envelope recover Samples selections Conversion into numerical to DSP 9
10 Discrete Analog FFT Composed by generic stages based on the radix-4 butterfly algorithm Each stage has the same structure IN Real IN Imaginary Delay Line 4 log4(n) Weighting Unit Delay Line 4 log4(n) Matrix Unit Delay Line feedback 4 log4(n) Delay Line feedback 4 log4(n) OUT Real OUT Imaginary DELAY ADD WEIGHT 10
11 Discrete Analog Operations Delay Differential structure A Charge transfer simulation RF IN Chold RF OUT Optimized Layout A Delay Line simulation 11
12 Discrete Analog Operations Adder Voltage samples are converted into current Current are added on one node The currents sum is converted into voltage Each FFT processing stage is composed by a matrix of addition and subtraction ADDER Adder allows to defined in hardware the add/subtract matrix 12
13 Discrete Analog Operations Weighter Clk Weight OUT
14 A Sampled Analog Signal Processor Three discrete analog operations to perform the FFT DELAY ADD WEIGHT The Analog Fast Fourier Transform is performed by basic analog operations 14
15 A Sampled Analog Signal Processor Simulation of 64-sample SASP F sampling = 500MHz F in = 7*500MHz /64 F sampling = 500MHz F in = 7.25*500MHz /64 FFT FFT FFT FFT 15
16 OUTLINE Software Radio in Mobile Terminals A Sampled Analog Signal Processor Principle and System Analog Discrete Electronics Modeling Results Perspectives Conclusion 16
17 Software Radio simulations Frequency Demodulation: BPSK example Bit signatures can be directly recognized into the spectrum 17
18 Software Radio simulations Frequency Demodulation: BPSK example Input Output Samples selection f out =477kHz 500MHz 477kHz : decimation by a ratio of 1000 ADC and DSP work at low frequencies 18
19 Software Radio simulations Frequency Demodulation: QPSK example The four-bit signature can be identified into the spectrum Open window to more complex modulation types: 8-QPSK, 16-QAM, 64-QAM Conclusion Optimized algorithm can be developed to demodulate signal into frequency domain ADC requirements are totally relaxed 19
20 Software Radio simulations Concurrent Reception Direct Reception Several signal envelops can be processed at the same time Military and Security applications: Listen any channel at the same time Commercial applications: Multiapplications devices As a FFT is processed, the SASP displays all the sub-carriers of OFDMmodulated signals. The digital part has just to handle the sub-carriers demodulations. 20
21 Perspectives: From a prototype to a final product Example of the GSM standard with a sample SASP T bit =3.69µs, Channel Bandwitdh=200kHz, Carrier Frequency=900MHz f sampling =2.184GHz f out =200kHz samples 6 samples With f sampling =2.184GHz, 6 samples encoding 8 bits are displayed A «frequency demodulation» algorithm would support a direct demodulation from the processed spectrum 21
22 A Sampled Analog Signal Processor Design of a 64-sample SASP 1200µm Technology: 65nm CMOS STMicrolectronics Die Area: 1.44mm² 1200µm Maximal Frequency: 1GHz RF spectrum range covered: 0-500MHz Power consumption: 360mW 64-sample SASP prototype finalized in a sample SASP 22
23 Conclusion The SASP is an Analog Processor in Software Radio receiving chain. It is technically: Low Power (P<500mW) Low Cost (CMOS technology) Small Die Area (IC<5mm²) Relaxes ADC and DSP constraints The SASP re-invents RF signal processing: Frequency Demodulation (Optimized demodulation) Concurrent Reception (Resources shared) The SASP can be a solution for a true Software Radio architecture dedicated to mobile terminals but many technological challenges remain to be overcome to achieve an industrial product 23
24 Conclusion A sample SASP working at 10GHz is the goal to reach a complete Software Radio Processor Thank you for your attention, Any questions? 24
25 Contact Information Feel free to contact me for more information François RIVET Mail: IMS Lab / 351 Cours de la Libération / Talence Cedex / France PhD. Student IC Design Team Software Radio RFIC Main References «A Disruptive Receiver Architecture Dedicated to Software-Defined Radio», IEEE transactions on Circuits and Systems II 55, 4 (2008) «A Universal Radio Frequency Receiver Architecture Based on Sampled Analog Signal Processing», IEEE MWSCAS 07, Montreal, Canada «A Disruptive Software-Defined Radio Receiver Architecture Based on Sampled Analog Signal Processing», IEEE Radio Frequency Integrated Circuits Symposium, Honolulu, United States, June 2007
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