Tokyo institute of technology Araki-Sakaguchi Laboratory Takafumi NASU

Transcription

1 Tokyo institute of technology Araki-Sakaguchi Laboratory Takafumi NASU 1

2 Background Role of Mixer Classification of Mixer Introduction of Direct Sampling Mixer (DSM) Issues and Objectives Noise analysis of SCF networks Noise Figure (NF) of DSM Conclusion 2

3 Example of receiver block in mobile terminal IMT-2000 RF IMT-2000 BB Receiver circuit is being designed for each standards. Receiver compose of different process. SiP(System in Package) GSM RF GSM BB Filter LNA MIXER ADC DBB Bluetooth RF Bluetooth BB Bipolar CMOS GPS RF ISDB-T RF GPS BB ISDB-T BB big size high power consumption 3

4 Example of receiver block in mobile terminal IMT-2000 RF IMT-2000 BB Multi-standard CMOS 1 chip receiver is desired. GSM RF GSM BB Bluetooth RF GPS RF Bluetooth BB GPS BB Reconfigurable CMOS RF ADC DBB ISDB-T RF ISDB-T BB 4

5 Requirements for multi-standard receiver in wireless communication Small size Low power consumption 5

6 signal level In receiver, signal received at antenna is handed to ADC. In digital stage, transmitted information is demodulated. Information data is very low rate compared with carrier frequency. To reduce the operation rate of ADC, it is necessary to pick out only information from received signal. It is performed by mixer and filter. received signal fc 2fc frequency 6

7 signal level Where is signal output? Intermediate Frequency (super heterodyne) good performance need image rejection in front of mixer image desired fif fif f fif frequency 7

8 signal level Where is signal output? Intermediate Frequency (super heterodyne) Base Band (Direct-conversion) not so good performance (DC offset, flicker noise) no image suitable for multi-standard receiver desired f=frf frequency 8

9 ow is down-conversion performed? Continuous time (Gilbert cell) VDD can not be reduced. Not suitable for CMOS technology VDD current VBB or VIF VRF V/I gm 9

10 signal level ow is down-conversion performed? Continuous time (Gilbert cell) Discrete time (Sampling mixer) RF Sub sampling MOS performs as a switch. MOS f=frf/n (n: integer) Fast switching operation is not needed. olding noise is big issue. BB signal olding noise S/ circuit C buffer RF signal BB or IF 0 fs 2fs 3fs 4fs 5fs frequency 10

11 signal level ow is down-conversion performed? Continuous time (Gilbert cell) Discrete time (Sampling mixer) RF sampling f=frf CMOS in deep submicron technology can adapt to fast switching operation. olding noise can be reduced. RF BB or IF BB signal RF signal MOS C buffer S/ circuit 0 fs frequency 11

12 Direct Sampling Mixer (DSM) Where? Direct-conversion ow? RF sampling DSM is Filter embedded mixer Suitable for multi-standard CMOS receiver desired DSM Mixing and Channel selection ADC frequency can reduce power consumption 12

13 Input voltage is converted to current by transconductans amplifier. Cs integrates current. Integration window is controlled by clock. V/I VRF gm IRF Cs 13

14 Input voltage is converted to current by transconductans amplifier. Cs integrates current. Integration window is controlled by clock. Case 2. frf=2f V/I VRF gm IRF Cs IRF=gm VRF Sampled voltage Vs 14

15 Voltage Gain[dB] VRF V/I gm IRF Cs C V S CI S T 2 0 gm f V V S in g e m V in T j 4 gmt 2C S e jt dt ft sin 2 ft sinc 2 V in 50 0 f=400mz Input Frequency[Mz] CIS performs as sinc filter. Interferences and holding noise from even frequency can be suppressed. owever, Output rate (= frf) is too fast. For ADC, decimation is needed. 15

16 Use two rotating capacitor CR Accumulate the charge N times Output rate = frf(=f)/n V/I VRF S1 S2 Vr1 T gm IRF N T Cr S1 Cr S2 C R V S 1 2 N1 1 z z z CRVR 1 CI sinc 1 Z 1 Z FIR N 1 FIR filter can be achieved by charge accumulation. Vr2 16

17 Voltage Gain[dB] V/I 50 VRF gm IRF S1 S2 0 Cr Cr 1 CI sinc 1 Z 1 Z FIR N Input Frequency[Mz] CI FIR 1 f=400mz, N=4 Charge accumulation performs as not only decimation, but also FIR (anti- aliasing) filter. owever, filter characteristics is not enough for channel selection. 17

18 VRF Add history capacitor C In contrast to CR, C is not reset. At the moment when S1 or S2 become on-state, C shares the charge with CR. V/I gm IRF T S1 S2 Ch Cr Cr N C C R V 1 C z V IIR1 C C R V IIR1 2 IIR1 CI 1 C FIR 1 C C R z IIR N S1 S2 N T IIR filter can be achieved by charge sharing. 18

19 Voltage Gain[dB] V/I VRF gm IRF S1 S2 50 Ch Cr Cr 0 2 CI FIR IIR IIR Sinc FIR 1 C 1 C C R IIR z N Input Frequency[Mz] f=400mz, N=4 IIR 2 Chanel selection can be achieved by charge sharing IIR filter. Bandwidth is defined by capacitance ratio. 19

20 Voltage Gain[dB] BANK A SA(1) SA(2) C R SB(2) SB(1) DUMP v B CI DSM 50 IIR 2 R FIR1 CR C C B IIR1 R IIR2 1 CB 1 C C B z N v in g m C C R BANK B RES C B 0 TA sampling switch SCF network Frequency[Mz] CMOS performs as a switch. Direct Down conversion by charge sampling (no IF) Relaxation of the performance requirement of ADC by decimation and filtering Reconfiguration by changing capacitor set and clock frequency, architecture. 20

21 Noise Figure (NF) of DSM measured from our prototype is over 20dB. Gain of CMOS LNA is around 10dB. Noise component from DSM can not be negligible. Analyzing the noise characteristics of DSM Designing the low noise DSM 21

22 Noise from MOS switches in SCF networks is analyzed. BANK A SA(1) SA(2) 0.18 μm MOS model from TSMC is used. Switches consist of nmos. Simulation result + DUMP C R SB(2) SB(1) C RES C R C B g m V in BANK B V in VCCS R C 0 0 BANK A SA(1) SA(2) V out - DUMP VCVS C R SB(2) SB(1) C RES C R BANK B Simulation parameter C B Calculated value shows good agreement with simulation result. The noise level is in inverse proportion to capacitance value. In practical parameter, noise components from TA is dominant

23 F Assuming that noise from TA is dominant, DSM f SNRin f f Nout f SNR f G f f N f f out in N ( f f GN f f TA 1 1 in ) F TA f Including buffer circuit which is located in next stage, F DSM f F DSM f F buffer G f f f 1 In prototype which was made in 2006, noise characteristics deterioration is caused by gain degradation. F buffer G N TA :internal noise from TA F TA :noise factor of TA :noise factor of buffer :gain of DSM 23

24 DSM can realize a reconfigurable RF circuit, and is suitable for CMOS technology. owever, some issues are remained. noise characteristics, nonlinearity, variety of filtering characteristics.. To achieve low NF, it is necessary to improve the gain of DSM. 24

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26 Voltage Gain[dB] Voltage Gain[dB] f=400mz, N=4 C=20pF, CR=0.2pF, CB=2pF Frequency[Mz] Frequency[Mz] 26

27 Input 400.5Mz Output 500kz Voltage Gain=39dB 300Mz f= 400 Mz 100Mz Voltage Gain=-21dB lab seminar 2008/5/20 27