Receiver Architectures - Part 2. Increasing the role of DSP in receiver front-ends
|
|
- Sarah Stevenson
- 5 years ago
- Views:
Transcription
1 ELT-44007/RxArch2/1 Receiver Architectures - Part 2 Increasing the role of DSP in receiver front-ends Markku Renfors Laboratory of Electronics and Communications Engineering Tampere University of Technology, Finland markku.renfors@tut.fi Topics: - Classification of DSP-based receiver architectures - Characteristics of alternative flexible wideband receiver architectures - DSP for flexible receivers - Digital channel selection & down-conversion techniques
2 ELT-44007/RxArch2/2 Classification of DSP-Based Receiver Architectures Location of ADC (A/D-converter) 1. Baseband or low IF 2. IF 3. RF Analog front-end bandwidth - ADC bandwidth 1. Single channel 2. Few channels 3. Frequency slice 4. Service band (e.g., GSM) 5. Multi-system frequency band (like 2 GHz range) The bandwidths of the analog front-end and ADC may or may not go hand in hand. Some examples below.
3 ELT-44007/RxArch2/3 Narrowband front-end Per-channel down-conversion (0, or IF) - Selectivity in analog part, good IF filters needed. - Per-channel frequency sythesizer needed. - No big demands for ADC dynamic range or jitter. - Sampling rate requirements are such that it is enough to attenuate aliasing to the desired band. - Narrowband (baseband or bandpass) ADC (like SD) can be utilized. RF-stages Mixer IF-stages BP/LP filter ADC LO f IF
4 ELT-44007/RxArch2/4 Wideband front-end, per-channel downconversion so that desired channel is around a fixed center frequency (0 or IF) - Analog front-end simplified in the sense that highly selective IF filters are not needed. - per-channel frequency synthesizer needed. - Selectivity in digital part, with fixed center frequency. - High demands for ADC dynamic range and jitter. - Sampling rate requirements are such that it is enough to attenuate aliasing to the desired band. - Narrowband ADC (like SD) can be utilized. RF-stages Mixer IF-stages BP/LP filter ADC LO f IF B IF
5 ELT-44007/RxArch2/5 Wideband front-end, wideband (like slice or service band) down-conversion so that desired channel is located in a wider frequency range - Analog front-end simplified in the sense that highly selective IF filters are not needed. - Single or few LO frequencies needed for each service band -> simplified synthesizer; fast frequency hopping becomes easier. - Selectivity in digital part, with tunable center frequency. - High demands for ADC dynamic range and jitter. - Sampling rate requirements are such that no aliasing into the whole band is allowed. - Wideband ADC (or SD with tunable center frequency!) needed. RF-stages Mixer IF-stages BP filter ADC LO B IF
6 ELT-44007/RxArch2/6 About the Choice Between Lowpass and Bandpass Sampling Due to the I/Q gain and phase imbalance problems in practical analog circuitry, the wideband downconversion - wideband sampling approach is very difficult to implement at 0 (or low) IF. But utilizing a combination of different techniques for mitigating these effects, the mentioned approach is becoming feasible, but mostly on the basestation side. On the other hand, wideband IF sampling is very challenging due to the apperture jitter and other implementation problems concerning the sampling circuitry (usually track&hold). The ADC requirements (apart from the sampling process) concern mainly the spurious-free dynamic range, and are not so heavily depending on the choice between lowpass or IF sampling. However, the useful ADC bandwidth has a great impact, e.g., on power consumption. So the cost/complexity metrics for per-channel A/D-conversion (usually SD) and multichannel A/D-conversion (usually something else than SD) are quite different.
7 ELT-44007/RxArch2/7 Some Dependencies and Conclusions Considering sampling and A/D-conversion highest signal frequency determines the T/H bandwidth and jitter requirements signal bandwidth (after analog RF/IF/baseband filtering) determines the minimum sampling rate Increasing the degree of bandpass subsampling ( f / f ) leads to c s lower sampling rate more selectivity needed before sampling more noise aliasing => more gain needed before sampling lower processing gain -> more bits from ADC & tighter jitter requirements Implementing the receiver selectivity in DSP-part leads to simplified analog part hard requirements for the T/H and ADC dynamic range Wideband sampling has been mostly considered at IF due to I/Qimbalance problems; direct conversion/low-if becoming feasible, depending on system specs Using IF sampling sets hard requirements for the T/H circuitry and jitter of the sampling clock.
8 ELT-44007/RxArch2/8 Connection to Advanced Broadband Wireless System Developments The latest and future wireless communication systems use increasing bandwidths for data transmission. For example, LTE has the maximum bandwidth of 20 MHz, and up to 100 MHz in LTE-A with carrier aggregation. 5G is targeting to significantly higher bandwidths. Especially, LTE is using frequency-division duplexing, and the spectrum entering the receiver resembles that of a multichannel receiver for more narrowband systems. Some characteristics and comments: - The wide bandwidth makes it possible to utilize fast frequency hopping and other forms of frequency diversity, to enhance the transmitted data rate. - In LTE (and other similar systems) the power levels of the frequency slots of different users are well-controlled (e.g., 20 db maximum variation in the power levels). This is in contrast to, e.g., multichannel GSM receiver, were the dynamic range is much bigger. This makes it feasible to implement the needed wideband receivers for such systems. - Direct conversion architecture is preferred. Actually, for most of the frequency channels, the low-if model is valid. - IQ-imbalance is significant, but not very critical because of the well-controlled power levels. DSP-based IQimbalance compensation is interesting in case of highorder modulations. - In these systems, and in OFDM systems in general, the frequencies at or close to DC in baseband processing are commonly not utilized in order to make direct conversion receiver design easier.
9 ELT-44007/RxArch2/9 About Direct Sampling Architecture In high-performance systems, it is necessary to have some selectivity and gain before sampling. The reasons are signal aliasing noise aliasing Sampling is commonly considered to be more noisy operation than mixing! Sampling directly from the antenna signal is usually not adequate. The Ultimate SW Radio Architecture Antenna a bank of RF filters and LNA s for different frequency bands T/H A/D DSP The needed technologies are not mature for challenging radio system specifications in the frequency bands used in mobile systems! However, direct sampling is already an interesting architecture in various applications o For example, satellite-based positioning (GPS/Galileo) where the dynamic range requirements are greatly reduced comparing with wireless communications.
10 ELT-44007/RxArch2/10 Direct Sampling & Analog Discrete-Time Processing Texas Instruments (TI) has introduced so-called digital radio processor (DRP) concept that is based on direct sampling, together with analog discrete-time processing to implement main part of the channel selectivity, downconversion, and sampling rate reduction. o For example, CIC/running-sum filters can be implemented with switched-capacitor techniques with analog processing. o Then the ADC is operating at relatively low rate and has reduced dynamic range requirements compared to digital direct-sampling approach. TI is marketing DRP-based transceiver chips for GPS, Bluetooth, and GSM/GPRS, i.e., for systems with relatively narrow bandwidth or reduced dynamic range, together with low-order modulation. In such architectures, also the sampling process may be designed to provide frequency selectivity. Then the idea of the sampling process is not anymore just taking instantaneous sample values, but to - Integrate the signal over a finite-length interval - Weighting the input signal by a proper window during the integration interval. Rectangular window results in sinc-response, other kind of windows can be designed for optimized performance.
11 ELT-44007/RxArch2/11 Multimode Receivers In flexible multi-mode receivers, the target is to use common blocks for different systems as much as possible. A long-term target is to make the transceiver configurable for any system. However, presently a combination of a few predetermined systems is more realistic. A realistic approach has the following elements: - Separate RF stages for different systems. - Common IF/baseband analog parts; bandwidth according to the most wideband system. - Common ADC at IF or baseband; fixed sampling rate. - Especially in the terminal side: careful choice of IF frequency & sampling rate to make the downconversion simple. Typically, f IF = (2k+1) f S /4. - Digital channel selection filtering optimized for the different systems. LNA IF 1 filter AGC S&H I DSP IF 2 ADC Q 0,1,0,-1 DSP LO 1,0,-1,0
12 ELT-44007/RxArch2/12 Rephrasing Critical Issues in Modern Receiver Architectures: SWOT Analysis on Flexible Receiver Architectures with Wideband Analog Front-End Alternatives: 1. Multimode direct-conversion receiver 2. Multimode low IF receiver 3. Multimode IF-sampling receiver 4. Wideband IF sampling architecture 5. Wideband direct-conversion/low-if architecture 6. Direct-sampling architecture Common features for 1-3: Analog & A/D bandwidth according to the widest channel bandwidth Common features for 4 and 5: Tunable digital channel selection and down-conversion Interesting mostly for base-station applications
13 ELT-44007/RxArch2/13 1. Multimode direct-conversion receiver Strengths - Simple analog part - Sampling jitter not critical - Narrowband A/D-conversion can be used Weaknesses - DC-offset problems, especially difficult to handle in flexible receiver - 2nd-order intermodulation -> bigger demands for the linearity of the analog parts Oportunities - Fast and flexible DC-offset compensation techniques, facilitated by high resolution A/D-conversion techniques.
14 ELT-44007/RxArch2/14 2. Multimode low IF receiver Strengths - Rather simple analog part - Sampling jitter not critical - Narrowband A/D-conversion can be used - DC-problems avoided Weaknesses - 2nd-order intermodulation -> bigger demands for the linearity of the analog parts - Higher demands for I/Q balance - Multimode concept not very clear (different low-if's for different systems, or very hard demands for I/Q balance) Oportunities - Adaptive I/Q imbalance compensation can be used to loosen the requirements of the analog part.
15 ELT-44007/RxArch2/15 3. Multimode IF-sampling receiver Strengths - Well-known architecture, high-quality analog RF possible - 2nd-order intermodulation not a problem - Narrowband A/D-conversion can be used - DC-problems avoided Weaknesses - Challenging demands for sampling jitter and linearity - IF filter difficult to integrate Oportunities - New technologies for flexible IF/RF filter implementation (e.g., MEMS)
16 ELT-44007/RxArch2/16 4. Wideband IF sampling architecture Strengths - Reduced IF filtering requirements - Simplified frequency synthesizer - Possibility to use common blocks for multiple channels - Facilitates fast frequency hopping/channel switching - DC-problems avoided Weaknesses - Very challenging demands for sampling jitter and linearity - Wideband A/D-conversion needed - 2nd-order intermodulation may be a problem - Lot of DSP power needed - High power consumption Oportunities - Advances in ADC technologies and DSP HW
17 ELT-44007/RxArch2/17 5. Wideband direct-conversion/low-if architecture Strengths - Simplified frequency synthesizer - Possibility to use common blocks for multiple channels - Facilitates fast frequency hopping/channel switching - Rather simple analog part - Sampling jitter not critical Weaknesses - Hard demands for I/Q balance - Multimode concept not very clear (avoiding DC-offset problems in all different systems) - Wideband A/D-conversion needed - 2nd-order intermodulation -> bigger demands for the linearity of the analog parts - High power consumption Oportunities - Adaptive I/Q imbalance compensation can be used to loosen the requirements of the analog part.
18 ELT-44007/RxArch2/18 6. Direct-sampling receiver Strengths - Simplest possible analog part - Highly flexible for multi-standard receivers. Weaknesses - Very hard jitter requirements. - Currently not feasible for demanding system specs or high-order modulation. Oportunities - Novel ideas for sampling and ADCs - Analog discrete-time processing techniques.
19 ELT-44007/RxArch2/19 Case Study on Wideband IF Sampling in GSM Receivers* Introduction Specifications and selectivity requirements for GSM Sampling and quantization requirements as Functions of analog filter bandwidth Requirements for digital filtering * This part is based on the diploma thesis work of Juho Pirskanen carried out at TUT/ICE during years
20 ELT-44007/RxArch2/20 Multi-Standard Receivers When several systems with different bandwidths are desired to be used, we have two basic choices: Several different analog front-ends in the receiver o This is still the typical choice in mobile devices OR Wideband analog front-end and wideband ADconversion Notice that we have basically the same choices also in multi-channel base-station receivers.
21 ELT-44007/RxArch2/21 Wideband GSM Receiver Receiver with wideband front-end and wideband ADconversion o Analog front-end can be simplified o One AD-converter can be used for different systems Performance requirements of the ADC are harder Channelization filtering must be done in digital domain to obtain desired system characteristics.
22 ELT-44007/RxArch2/22 GSM Case: Interference Mask Obtained from the GSM specifications Includes interference signals from adjacent channel out of band blocking intermodulation test
23 ELT-44007/RxArch2/23 GSM Case: Attenuation Requirements Attenuation requirements for GSM can be expressed as ( ) A ( f ) = P ( f ) - P - SIR - A S I sign m P I power of the interference signal P sign power of the desired signal SIR required signal to interference ratio A m extra noise margin
24 ELT-44007/RxArch2/24 GSM Case: ADC Dynamic Range ADC dynamic range requirement can be calculated as dynamic { S ( ) ( )} SNR = max A f + H f A S ( f ) is the attenuation requirement in db H( f ) the amplitude response of the analog filter in db Fourth-order Chebyshev type two filters: f The red squares mark the critical points where the dynamic range requirement is maximized for each filter bandwidth.
25 ELT-44007/RxArch2/25 GSM Case: ADC Dynamic Requirements By combining the above equations and the ADC analysis from p. 33 of Sampling and Multirate Techniques for Complex and Bandpass Signals lecture, and noting that GSM uses constant enevelope modulation, the minimum number of bits can be evaluated by é f SNRdynamic log æ s öù ê ç 2B ú b = è ø ê ú ê 6.02 ú ê ú This is a worst-case model, assuming that the interference comes from a blocking tone signal at the frequency where SNR is maximized. dynamic Below the minimum number of bits is shown as a function of sampling rate and analog bandwidth for two common filter types. Used sampling rates Multiples of GSM symbol rate MHz, MHz and MHz Studied filter types Butterworth and Chebyshev type II filters Used filter orders Fourth and sixth order filters Filter bandwidth From 100 khz to 2.5 MHz
26 ELT-44007/RxArch2/26 GSM Case: Number of Bits Required in ADC Fourth-order Butterworth filters: Sixth-order Chebyshev type II filters: Notice that in practice the minimum number of bits is higher than the lowest values indicated here, in order to be able to carry out the channel equalization properly.
27 ELT-44007/RxArch2/27 GSM Case: Jitter Noise The maximum signal power to be sampled is: ADC max I f { ( ) ( ) 2 } P = P f H f Using the standard white-noise model for the jitter effects, the maximum allowed standard deviation of the timing error (RMS sampling jitter) is given by: T = F S A 2 2 4p fmax ( Psig SIR Am ) - - 2B P ADC
28 ELT-44007/RxArch2/28 GSM Case: Jitter Requirements for f IF =156 MHz The timing jitter requirements when using fourth-order Butterworth filters: The timing jitter requirements when using sixth-order Chebyshev type II filters:
29 ELT-44007/RxArch2/29 GSM Case: Digital Filtering Requirements Channelization and noise filtering requirements for DSP in the GSM case. Sixth order Chebyshev type II analog filter Second order Sigma-delta modulator with 2 quantization bits The total decimation factor can be divided into several stages, e.g., 256 = 64 * 2*2 First stage can be implemented by using CIC-filters Simple structure, no multipliers Good attenuation for aliasing signal bands
30 ELT-44007/RxArch2/30 Wideband GSM Receiver: Conclusions Dynamic requirement of the ADC Highly effected by the analog filter bandwidth Analog filter order and type has only one bit effect on ADC requirement (together 2 bits in some cases) Standard deviation of timing jitter Highly effected by the analog filter bandwidth and used IF frequency (IF sampling) Analog filter order and type has only slight effect When considering GSM/WCDMA receivers The analog bandwidth should be about 2 MHz It is convenient to use common sampling rate for both systems Fractional sampling rate conversion has to be done because the WCDMA chip rate is not an integer multiple of the GSM symbol rate.
31 ELT-44007/RxArch2/31 DSP for Flexible Receivers In advanced SW radio concepts, the selectivity filtering and down-conversion are moved from analog continuoustime part to the discrete-time/dsp part. => Here efficient multirate filtering techniques become very important, also by non-integer factors. It also helps to move as much as possible functionality from the analog or digital front-end to baseband processing. => All-digital synchronization concept becomes very interesting in this context. Some errors due to RF-front-end can be corrected by DSP. Example: Adaptive I/Q imbalance compensation. => DSP-enhanced radio (a.k.a. dirty RF)
32 ELT-44007/RxArch2/32 All-Digital Synchronisation Concept Free-running local oscillators for demodulation and frequency conversion. Free-running sampling clock. Errors are compensated in digital part. => All synchronisation functions can be implemented using digital techniques
33 ELT-44007/RxArch2/33 Digital Channel Selection & Down-Conversion
34 ELT-44007/RxArch2/34 Digital Channel Selection & Down-Conversion Digital Down-Conversion 1. Desired channel centered at fixed IF => Fixed down-conversion Special choices of f IF and f S make things easy. Especially when f IF = (2k+1) f S /4, the signal aliases to f S /4 and down-conversion is very easy. 2. Wideband sampling case => Tunable down-conversion and NCO (numerically controlled oscillator) needed. 3. Stepwise mixing and decimation => Tunable digital down-conversion is possible also without I/Q mixing, or by doing fine-tuning mixing at low rate after decimation. However, it is not easy to find sufficiently efficient and flexible schemes. Channel Selection Filtering - After down-conversion, efficient lowpass decimator structure is needed. - CIC-filters are commonly used in the first decimation stages, FIR-filters and the last stages. Half-band FIR filters also an efficient and fairly common solution. (See Multirate Filtering lecture notes.) Adjusting Symbol Rates - Different systems use different symbol/chip rates. - Common sampling clock frequency is preferred. => Decimaton by a fractional factor is needed. - This can be done at baseband or earlier in the decimation chain. (See lecture notes on Polynomial-based interpolation)
35 ELT-44007/RxArch2/35 CIC-Filters z -1 z z -1 z -1 CIC = Cascaded Integrator - Comb Transfer function and frequency response: ( 2 p / ) S H e H ( z) R N æ - z ö ç1- = ç -1 z è 1- ø ( p S ) ( p ) jp N ( R 1) f / f j f f S sin R f / f - æ ö = e ç Rsin f / f è S ø N Here R is the decimation factor and N is the order of the CIC-filter. A first-order CIC-filter takes the avarage of R consequtive input samples and decimates by R. It is also called moving average or running sum filter. It is important to use modulo arithmetic (like 2's complement) in the implementation, because there will be inevitable internal overflows.
36 ELT-44007/RxArch2/36 CIC-Filters In CIC filter, those frequencies aliasing to 0-frequency are heavily attenuated. For a relatively narrowband signal, low-order CIC-filters are sufficient; more wideband signals neede higher CIC-filter orders Example (for a GSM application): N=2, R=32.
37 ELT-44007/RxArch2/37 NCO-Based Arbitrary Digital Down- Conversion Dedicated processors implementing the following kind of down-conversion and channel selection structure are available from several vendors (like Harris). Sampling rates in the MHz range are possible. However, the power consumption is still too high for terminal applications.
38 ELT-44007/RxArch2/38 Example Using Harris HSP50214 for GSM channel selection filtering. - Input sample rate: 39 MHz - CIC-filter: decimation by 18, order=5 - Two pre-designed FIR half-band filters are used for the next decimation stages. - The final filter stage is an FIR design. - Output sample rate: khz Frequency responses of the filter stages:
39 ELT-44007/RxArch2/39 Example (continued) Overall frequency response and the effects of different stages:
Receiver Architectures - Part 2. Increasing the role of DSP in receiver front-ends
TLT-5806/RxArch2/1 Receiver Architectures - Part 2 Increasing the role of DSP in receiver front-ends Markku Renfors Department of Communications Engineering Tampere University of Technology, Finland markku.renfors@tut.fi
More informationELT Receiver Architectures and Signal Processing Exam Requirements and Model Questions 2018
TUT/ICE 1 ELT-44006 Receiver Architectures and Signal Processing Exam Requirements and Model Questions 2018 General idea of these Model Questions is to highlight the central knowledge expected to be known
More informationELT Radio Architectures and Signal Processing. Motivation, Some Background & Scope
Introduction ELT-44007/Intro/1 ELT-44007 Radio Architectures and Signal Processing Motivation, Some Background & Scope Markku Renfors Department of Electronics and Communications Engineering Tampere University
More informationELT Receiver Architectures and Signal Processing Fall Mandatory homework exercises
ELT-44006 Receiver Architectures and Signal Processing Fall 2014 1 Mandatory homework exercises - Individual solutions to be returned to Markku Renfors by email or in paper format. - Solutions are expected
More informationSome Radio Implementation Challenges in 3G-LTE Context
1 (12) Dirty-RF Theme Some Radio Implementation Challenges in 3G-LTE Context Dr. Mikko Valkama Tampere University of Technology Institute of Communications Engineering mikko.e.valkama@tut.fi 2 (21) General
More informationReceiver Architecture
Receiver Architecture Receiver basics Channel selection why not at RF? BPF first or LNA first? Direct digitization of RF signal Receiver architectures Sub-sampling receiver noise problem Heterodyne receiver
More informationReceiver Architectures
83080RA/1 Receiver Architectures Markku Renfors Tampere University of Technology Digital Media Institute/Telecommunications 83080RA/2 Topics 1. Main analog components for receivers - amplifiers - filters
More informationChannelization and Frequency Tuning using FPGA for UMTS Baseband Application
Channelization and Frequency Tuning using FPGA for UMTS Baseband Application Prof. Mahesh M.Gadag Communication Engineering, S. D. M. College of Engineering & Technology, Dharwad, Karnataka, India Mr.
More informationPLC2 FPGA Days Software Defined Radio
PLC2 FPGA Days 2011 - Software Defined Radio 17 May 2011 Welcome to this presentation of Software Defined Radio as seen from the FPGA engineer s perspective! As FPGA designers, we find SDR a very exciting
More informationCo-existence. DECT/CAT-iq vs. other wireless technologies from a HW perspective
Co-existence DECT/CAT-iq vs. other wireless technologies from a HW perspective Abstract: This White Paper addresses three different co-existence issues (blocking, sideband interference, and inter-modulation)
More informationRF/IF Terminology and Specs
RF/IF Terminology and Specs Contributors: Brad Brannon John Greichen Leo McHugh Eamon Nash Eberhard Brunner 1 Terminology LNA - Low-Noise Amplifier. A specialized amplifier to boost the very small received
More informationECE 6560 Multirate Signal Processing Chapter 13
Multirate Signal Processing Chapter 13 Dr. Bradley J. Bazuin Western Michigan University College of Engineering and Applied Sciences Department of Electrical and Computer Engineering 1903 W. Michigan Ave.
More informationTHE BASICS OF RADIO SYSTEM DESIGN
THE BASICS OF RADIO SYSTEM DESIGN Mark Hunter * Abstract This paper is intended to give an overview of the design of radio transceivers to the engineer new to the field. It is shown how the requirements
More informationLow-Power Decimation Filter Design for Multi-Standard Transceiver Applications
i Low-Power Decimation Filter Design for Multi-Standard Transceiver Applications by Carol J. Barrett Master of Science in Electrical Engineering University of California, Berkeley Professor Paul R. Gray,
More informationAPPLICATION NOTE 3942 Optimize the Buffer Amplifier/ADC Connection
Maxim > Design Support > Technical Documents > Application Notes > Communications Circuits > APP 3942 Maxim > Design Support > Technical Documents > Application Notes > High-Speed Interconnect > APP 3942
More informationTSEK38 Radio Frequency Transceiver Design: Project work B
TSEK38 Project Work: Task specification A 1(15) TSEK38 Radio Frequency Transceiver Design: Project work B Course home page: Course responsible: http://www.isy.liu.se/en/edu/kurs/tsek38/ Ted Johansson (ted.johansson@liu.se)
More informationRadio Receiver Architectures and Analysis
Radio Receiver Architectures and Analysis Robert Wilson December 6, 01 Abstract This article discusses some common receiver architectures and analyzes some of the impairments that apply to each. 1 Contents
More informationPipeline vs. Sigma Delta ADC for Communications Applications
Pipeline vs. Sigma Delta ADC for Communications Applications Noel O Riordan, Mixed-Signal IP Group, S3 Semiconductors noel.oriordan@s3group.com Introduction The Analog-to-Digital Converter (ADC) is a key
More information1 Introduction to Highly Integrated and Tunable RF Receiver Front Ends
1 Introduction to Highly Integrated and Tunable RF Receiver Front Ends 1.1 Introduction With the ever-increasing demand for instant access to data over wideband communication channels, the quest for a
More informationSection 1. Fundamentals of DDS Technology
Section 1. Fundamentals of DDS Technology Overview Direct digital synthesis (DDS) is a technique for using digital data processing blocks as a means to generate a frequency- and phase-tunable output signal
More informationAnalog and Telecommunication Electronics
Politecnico di Torino - ICT School Analog and Telecommunication Electronics B1 - Radio systems architecture» Basic radio systems» Image rejection» Digital and SW radio» Functional units 19/03/2012-1 ATLCE
More informationTHIS work focus on a sector of the hardware to be used
DISSERTATION ON ELECTRICAL AND COMPUTER ENGINEERING 1 Development of a Transponder for the ISTNanoSAT (November 2015) Luís Oliveira luisdeoliveira@tecnico.ulisboa.pt Instituto Superior Técnico Abstract
More informationDECIMATION FILTER FOR MULTISTANDARD WIRELESS RECEIVER SHEETAL S.SHENDE
DECIMATION FILTER FOR MULTISTANDARD WIRELESS RECEIVER SHEETAL S.SHENDE Abstract The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have
More informationRFID Systems: Radio Architecture
RFID Systems: Radio Architecture 1 A discussion of radio architecture and RFID. What are the critical pieces? Familiarity with how radio and especially RFID radios are designed will allow you to make correct
More informationDESIGN CONSIDERATIONS FOR DIRECT RF SAMPLING RECEIVER IN GNSS ENVIRONMENT. Ville Syrjälä, Mikko Valkama, Markku Renfors
DESIGN CONSIDERATIONS FOR DIRECT RF SAMPLING RECEIVER IN GNSS ENVIRONMENT Ville Syrjälä, Mikko Valkama, Markku Renfors Tampere University of Technology Institute of Communications Engineering P.O Box 553,
More informationReceiver Design. Prof. Tzong-Lin Wu EMC Laboratory Department of Electrical Engineering National Taiwan University 2011/2/21
Receiver Design Prof. Tzong-Lin Wu EMC Laboratory Department of Electrical Engineering National Taiwan University 2011/2/21 MW & RF Design / Prof. T. -L. Wu 1 The receiver mush be very sensitive to -110dBm
More informationB SCITEQ. Transceiver and System Design for Digital Communications. Scott R. Bullock, P.E. Third Edition. SciTech Publishing, Inc.
Transceiver and System Design for Digital Communications Scott R. Bullock, P.E. Third Edition B SCITEQ PUBLISHtN^INC. SciTech Publishing, Inc. Raleigh, NC Contents Preface xvii About the Author xxiii Transceiver
More informationResearch and Development Activities in RF and Analog IC Design. RFIC Building Blocks. Single-Chip Transceiver Systems (I) Howard Luong
Research and Development Activities in RF and Analog IC Design Howard Luong Analog Research Laboratory Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology
More informationImplementation of CIC filter for DUC/DDC
Implementation of CIC filter for DUC/DDC R Vaishnavi #1, V Elamaran #2 #1 Department of Electronics and Communication Engineering School of EEE, SASTRA University Thanjavur, India rvaishnavi26@gmail.com
More informationKeywords: CIC Filter, Field Programmable Gate Array (FPGA), Decimator, Interpolator, Modelsim and Chipscope.
www.semargroup.org, www.ijsetr.com ISSN 2319-8885 Vol.03,Issue.25 September-2014, Pages:5002-5008 VHDL Implementation of Optimized Cascaded Integrator Comb (CIC) Filters for Ultra High Speed Wideband Rate
More informationSuperheterodyne Receiver Tutorial
1 of 6 Superheterodyne Receiver Tutorial J P Silver E-mail: john@rfic.co.uk 1 ABSTRACT This paper discusses the basic design concepts of the Superheterodyne receiver in both single and double conversion
More informationPRODUCT HOW-TO: Building an FPGA-based Digital Down Converter
PRODUCT HOW-TO: Building an FPGA-based Digital Down Converter By Richard Kuenzler and Robert Sgandurra Embedded.com (06/03/09, 06:37:00 AM EDT) The digital downconverter (DDC) has become a cornerstone
More informationA 3 TO 30 MHZ HIGH-RESOLUTION SYNTHESIZER CONSISTING OF A DDS, DIVIDE-AND-MIX MODULES, AND A M/N SYNTHESIZER. Richard K. Karlquist
A 3 TO 30 MHZ HIGH-RESOLUTION SYNTHESIZER CONSISTING OF A DDS, -AND-MIX MODULES, AND A M/N SYNTHESIZER Richard K. Karlquist Hewlett-Packard Laboratories 3500 Deer Creek Rd., MS 26M-3 Palo Alto, CA 94303-1392
More informationDesign Of Multirate Linear Phase Decimation Filters For Oversampling Adcs
Design Of Multirate Linear Phase Decimation Filters For Oversampling Adcs Phanendrababu H, ArvindChoubey Abstract:This brief presents the design of a audio pass band decimation filter for Delta-Sigma analog-to-digital
More informationLecture LTE (4G) -Technologies used in 4G and 5G. Spread Spectrum Communications
COMM 907: Spread Spectrum Communications Lecture 10 - LTE (4G) -Technologies used in 4G and 5G The Need for LTE Long Term Evolution (LTE) With the growth of mobile data and mobile users, it becomes essential
More informationWideband Receiver for Communications Receiver or Spectrum Analysis Usage: A Comparison of Superheterodyne to Quadrature Down Conversion
A Comparison of Superheterodyne to Quadrature Down Conversion Tony Manicone, Vanteon Corporation There are many different system architectures which can be used in the design of High Frequency wideband
More informationSession 3. CMOS RF IC Design Principles
Session 3 CMOS RF IC Design Principles Session Delivered by: D. Varun 1 Session Topics Standards RF wireless communications Multi standard RF transceivers RF front end architectures Frequency down conversion
More informationCHAPTER 4 DESIGN OF DIGITAL DOWN CONVERTER AND SAMPLE RATE CONVERTER FOR DIGITAL FRONT- END OF SDR
95 CHAPTER 4 DESIGN OF DIGITAL DOWN CONVERTER AND SAMPLE RATE CONVERTER FOR DIGITAL FRONT- END OF SDR 4. 1 INTRODUCTION Several mobile communication standards are currently in service in various parts
More informationTestData Summary of 5.2GHz WLAN Direct Conversion RF Transceiver Board
Page 1 of 16 ========================================================================================= TestData Summary of 5.2GHz WLAN Direct Conversion RF Transceiver Board =========================================================================================
More informationReal-Time Digital Down-Conversion with Equalization
Real-Time Digital Down-Conversion with Equalization February 20, 2019 By Alexander Taratorin, Anatoli Stein, Valeriy Serebryanskiy and Lauri Viitas DOWN CONVERSION PRINCIPLE Down conversion is basic operation
More informationA 1.9GHz Single-Chip CMOS PHS Cellphone
A 1.9GHz Single-Chip CMOS PHS Cellphone IEEE JSSC, Vol. 41, No.12, December 2006 William Si, Srenik Mehta, Hirad Samavati, Manolis Terrovitis, Michael Mack, Keith Onodera, Steve Jen, Susan Luschas, Justin
More informationTSEK38: Radio Frequency Transceiver Design Lecture 3: Superheterodyne TRX design
TSEK38: Radio Frequency Transceiver Design Lecture 3: Superheterodyne TRX design Ted Johansson, ISY ted.johansson@liu.se 2 Outline of lecture 3 Introduction RF TRX architectures (3) Superheterodyne architecture
More informationAgilent Highly Accurate Amplifier ACLR and ACPR Testing with the Agilent N5182A MXG Vector Signal Generator. Application Note
Agilent Highly Accurate Amplifier ACLR and ACPR Testing with the Agilent N5182A MXG Vector Signal Generator Application Note Introduction 1 0 0 1 Symbol encoder I Q Baseband filters I Q IQ modulator Other
More informationRF Receiver Hardware Design
RF Receiver Hardware Design Bill Sward bsward@rtlogic.com February 18, 2011 Topics Customer Requirements Communication link environment Performance Parameters/Metrics Frequency Conversion Architectures
More informationAdjacent Channel Interference Mitigation Schemes for Software Defined Radio Receiver
Adjacent Channel Interference Mitigation Schemes for Software Defined Radio Receiver July 2008 Anas Bin Muhamad Bostamam DISSERTATION Submitted to the School of Integrated Design Engineering, Keio University,
More informationVLSI Implementation of Digital Down Converter (DDC)
Volume-7, Issue-1, January-February 2017 International Journal of Engineering and Management Research Page Number: 218-222 VLSI Implementation of Digital Down Converter (DDC) Shaik Afrojanasima 1, K Vijaya
More informationFUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART I.1
FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART I.1 Many of these slides were provided by Dr. Sebastian Hoyos January 2019 Texas A&M University 1 Spring, 2019 Outline Fundamentals of Analog-to-Digital
More informationDIGITAL DOWN/UP CONVERTERS FUNDAMENTALS. TEXAS INSTRUMENTS - WIRELESS RADIO PRODUCTS GROUP Joe Quintal
DDC/DUC Fundamentals Application Note Page 1 of 60 DIGITAL DOWN/UP CONVERTERS FUNDAMENTALS TEXAS INSTRUMENTS - WIRELESS RADIO PRODUCTS GROUP Joe Quintal DDC/DUC Fundamentals Application Note Page 2 of
More informationTUNABLE MISMATCH SHAPING FOR QUADRATURE BANDPASS DELTA-SIGMA DATA CONVERTERS. Waqas Akram and Earl E. Swartzlander, Jr.
TUNABLE MISMATCH SHAPING FOR QUADRATURE BANDPASS DELTA-SIGMA DATA CONVERTERS Waqas Akram and Earl E. Swartzlander, Jr. Department of Electrical and Computer Engineering University of Texas at Austin Austin,
More informationThe Loss of Down Converter for Digital Radar receiver
The Loss of Down Converter for Digital Radar receiver YOUN-HUI JANG 1, HYUN-IK SHIN 2, BUM-SUK LEE 3, JEONG-HWAN KIM 4, WHAN-WOO KIM 5 1-4: Agency for Defense Development, Yuseong P.O. Box 35, Daejeon,
More informationIntroduction to Receivers
Introduction to Receivers Purpose: translate RF signals to baseband Shift frequency Amplify Filter Demodulate Why is this a challenge? Interference Large dynamic range required Many receivers must be capable
More informationFabricate a 2.4-GHz fractional-n synthesizer
University of Malaya From the SelectedWorks of Professor Mahmoud Moghavvemi Summer June, 2013 Fabricate a 2.4-GHz fractional-n synthesizer H Ameri Mahmoud Moghavvemi, University of Malaya a Attaran Available
More informationAn All CMOS, 2.4 GHz, Fully Adaptive, Scalable, Frequency Hopped Transceiver
An All CMOS, 2.4 GHz, Fully Adaptive, Scalable, Frequency Hopped Transceiver Farbod Behbahani John Leete Alexandre Kral Shahrzad Tadjpour Karapet Khanoyan Paul J. Chang Hooman Darabi Maryam Rofougaran
More informationAn Overview of the Decimation process and its VLSI implementation
MPRA Munich Personal RePEc Archive An Overview of the Decimation process and its VLSI implementation Rozita Teymourzadeh and Masuri Othman UKM University 1. February 2006 Online at http://mpra.ub.uni-muenchen.de/41945/
More informationDigital Baseband Architecture in AR1243/AR1642 Automotive Radar Devices
Application Report Lit. Number June 015 Digital Baseband Architecture in AR143/AR164 Automotive Radar Devices Sriram Murali, Karthik Ramasubramanian Wireless Connectivity Solutions ABSTRACT This application
More informationADI 2006 RF Seminar. Chapter II RF/IF Components and Specifications for Receivers
ADI 2006 RF Seminar Chapter II RF/IF Components and Specifications for Receivers 1 RF/IF Components and Specifications for Receivers Fixed Gain and Variable Gain Amplifiers IQ Demodulators Analog-to-Digital
More informationKeysight Technologies Pulsed Antenna Measurements Using PNA Network Analyzers
Keysight Technologies Pulsed Antenna Measurements Using PNA Network Analyzers White Paper Abstract This paper presents advances in the instrumentation techniques that can be used for the measurement and
More informationKeywords: GPS, receiver, GPS receiver, MAX2769, 2769, 1575MHz, Integrated GPS Receiver, Global Positioning System
Maxim > Design Support > Technical Documents > User Guides > APP 3910 Keywords: GPS, receiver, GPS receiver, MAX2769, 2769, 1575MHz, Integrated GPS Receiver, Global Positioning System USER GUIDE 3910 User's
More informationBANDPASS delta sigma ( ) modulators are used to digitize
680 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 10, OCTOBER 2005 A Time-Delay Jitter-Insensitive Continuous-Time Bandpass 16 Modulator Architecture Anurag Pulincherry, Michael
More informationFundamentals of Digital Communication
Fundamentals of Digital Communication Network Infrastructures A.A. 2017/18 Digital communication system Analog Digital Input Signal Analog/ Digital Low Pass Filter Sampler Quantizer Source Encoder Channel
More informationDesign of Bandpass Delta-Sigma Modulators: Avoiding Common Mistakes
Design of Bandpass Delta-Sigma Modulators: Avoiding Common Mistakes R. Jacob Baker and Vishal Saxena Department of Electrical and Computer Engineering Boise State University 1910 University Dr., ET 201
More informationHigh Speed & High Frequency based Digital Up/Down Converter for WCDMA System
High Speed & High Frequency based Digital Up/Down Converter for WCDMA System Arun Raj S.R Department of Electronics & Communication Engineering University B.D.T College of Engineering Davangere-Karnataka,
More informationCMOS Analog to Digital Converters : State-of-the-Art and Perspectives in Digital Communications ADC
CMOS Analog to Digital Converters : State-of-the-Art and Perspectives in Digital Communications ADC Hussein Fakhoury and Hervé Petit C²S Research Group Presentation Outline Introduction Basic concepts
More informationA 1MHz-64MHz Active RC TI-LPF with Variable Gain for SDR Receiver in 65-nm CMOS
2017 5th International Conference on Computer, Automation and Power Electronics (CAPE 2017) A 1MHz-64MHz Active RC TI-LPF with Variable Gain for SDR Receiver in 65-nm CMOS Chaoxuan Zhang1, a, *, Xunping
More informationAN-502 APPLICATION NOTE Designing a Superheterodyne Receiver Using an IF Sampling Diversity Chipset by Brad Brannon
a AN-52 APPLICATION NOTE One Technology Way P.O. Box 916 Norwood, MA 262-916 781/329-47 World Wide Web Site: http://www.analog.com Designing a Superheterodyne Receiver Using an IF Sampling Diversity Chipset
More information9 Best Practices for Optimizing Your Signal Generator Part 2 Making Better Measurements
9 Best Practices for Optimizing Your Signal Generator Part 2 Making Better Measurements In consumer wireless, military communications, or radar, you face an ongoing bandwidth crunch in a spectrum that
More informationAntenna Measurements using Modulated Signals
Antenna Measurements using Modulated Signals Roger Dygert MI Technologies, 1125 Satellite Boulevard, Suite 100 Suwanee, GA 30024-4629 Abstract Antenna test engineers are faced with testing increasingly
More informationFundamentals of Data Conversion: Part I.1
Fundamentals of Data Conversion: Part I.1 Sebastian Hoyos http://ece.tamu.edu/~hoyos/ Several of these slides were provided by Dr. Jose Silva-Martinez and Dr. Jun Zhou Outline Fundamentals of Analog-to-Digital
More informationImplementing DDC with the HERON-FPGA Family
HUNT ENGINEERING Chestnut Court, Burton Row, Brent Knoll, Somerset, TA9 4BP, UK Tel: (+44) (0)1278 760188, Fax: (+44) (0)1278 760199, Email: sales@hunteng.demon.co.uk URL: http://www.hunteng.co.uk Implementing
More informationElectronic Warfare Receivers. and Receiving Systems. Richard A. Poisel ARTECH HOUSE BOSTON LONDON. artechhouse.com
Electronic Warfare Receivers and Receiving Systems Richard A. Poisel ARTECH HOUSE BOSTON LONDON artechhouse.com Table of Contents Preface Chapter 1 Receiving Systems and Receiving System Architectures
More informationWideband Spectral Measurement Using Time-Gated Acquisition Implemented on a User-Programmable FPGA
Wideband Spectral Measurement Using Time-Gated Acquisition Implemented on a User-Programmable FPGA By Raajit Lall, Abhishek Rao, Sandeep Hari, and Vinay Kumar Spectral measurements for some of the Multiple
More informationData Conversion Techniques (DAT115)
Data Conversion Techniques (DAT115) Hand in Report Second Order Sigma Delta Modulator with Interleaving Scheme Group 14N Remzi Yagiz Mungan, Christoffer Holmström [ 1 20 ] Contents 1. Task Description...
More informationELEN 701 RF & Microwave Systems Engineering. Lecture 2 September 27, 2006 Dr. Michael Thorburn Santa Clara University
ELEN 701 RF & Microwave Systems Engineering Lecture 2 September 27, 2006 Dr. Michael Thorburn Santa Clara University Lecture 2 Radio Architecture and Design Considerations, Part I Architecture Superheterodyne
More informationImplementation of Digital Signal Processing: Some Background on GFSK Modulation
Implementation of Digital Signal Processing: Some Background on GFSK Modulation Sabih H. Gerez University of Twente, Department of Electrical Engineering s.h.gerez@utwente.nl Version 5 (March 9, 2016)
More informationSAMPLING FREQUENCY SELECTION SCHEME FOR A MULTIPLE SIGNAL RECEIVER USING UNDERSAMPLING
SAMPLING FREQUENCY SELECTION SCHEME FOR A MULTIPLE SIGNAL RECEIVER USING UNDERSAMPLING Yoshio Kunisawa (KDDI R&D Laboratories, yokosuka, kanagawa, JAPAN; kuni@kddilabs.jp) ABSTRACT A multi-mode terminal
More informationCMOS LNA Design for Ultra Wide Band - Review
International Journal of Innovation and Scientific Research ISSN 235-804 Vol. No. 2 Nov. 204, pp. 356-362 204 Innovative Space of Scientific Research Journals http://www.ijisr.issr-journals.org/ CMOS LNA
More informationTSEK02: Radio Electronics Lecture 8: RX Nonlinearity Issues, Demodulation. Ted Johansson, EKS, ISY
TSEK02: Radio Electronics Lecture 8: RX Nonlinearity Issues, Demodulation Ted Johansson, EKS, ISY 2 RX Nonlinearity Issues, Demodulation RX nonlinearities (parts of 2.2) System Nonlinearity Sensitivity
More informationSignal Detection with EM1 Receivers
Signal Detection with EM1 Receivers Werner Schaefer Hewlett-Packard Company Santa Rosa Systems Division 1400 Fountaingrove Parkway Santa Rosa, CA 95403-1799, USA Abstract - Certain EM1 receiver settings,
More informationA Closer Look at 2-Stage Digital Filtering in the. Proposed WIDAR Correlator for the EVLA
NRC-EVLA Memo# 1 A Closer Look at 2-Stage Digital Filtering in the Proposed WIDAR Correlator for the EVLA NRC-EVLA Memo# Brent Carlson, June 2, 2 ABSTRACT The proposed WIDAR correlator for the EVLA that
More informationUtilizzo del Time Domain per misure EMI
Utilizzo del Time Domain per misure EMI Roberto Sacchi Measurement Expert Manager - Europe 7 Giugno 2017 Compliance EMI receiver requirements (CISPR 16-1-1 ) range 9 khz - 18 GHz: A normal +/- 2 db absolute
More informationCase Study: and Test Wireless Receivers
Case Study: Using New Technologies to Design and Test Wireless Receivers Agenda Architecture of a receiver Basic GPS Receiver Measurements Case Study 1: GPS Simulation How Testing Works Simulation vs.
More informationSoftware Defined Radio: Enabling technologies and Applications
Mengduo Ma Cpr E 583 September 30, 2011 Software Defined Radio: Enabling technologies and Applications A Mini-Literature Survey Abstract The survey paper identifies the enabling technologies and research
More informationOutline. Communications Engineering 1
Outline Introduction Signal, random variable, random process and spectra Analog modulation Analog to digital conversion Digital transmission through baseband channels Signal space representation Optimal
More informationRADIO RECEIVERS ECE 3103 WIRELESS COMMUNICATION SYSTEMS
RADIO RECEIVERS ECE 3103 WIRELESS COMMUNICATION SYSTEMS FUNCTIONS OF A RADIO RECEIVER The main functions of a radio receiver are: 1. To intercept the RF signal by using the receiver antenna 2. Select the
More informationAppendix B. Design Implementation Description For The Digital Frequency Demodulator
Appendix B Design Implementation Description For The Digital Frequency Demodulator The DFD design implementation is divided into four sections: 1. Analog front end to signal condition and digitize the
More informationDIRECT UP-CONVERSION USING AN FPGA-BASED POLYPHASE MODEM
DIRECT UP-CONVERSION USING AN FPGA-BASED POLYPHASE MODEM Rob Pelt Altera Corporation 101 Innovation Drive San Jose, California, USA 95134 rpelt@altera.com 1. ABSTRACT Performance requirements for broadband
More informationTSEK02: Radio Electronics Lecture 8: RX Nonlinearity Issues, Demodulation. Ted Johansson, EKS, ISY
TSEK02: Radio Electronics Lecture 8: RX Nonlinearity Issues, Demodulation Ted Johansson, EKS, ISY RX Nonlinearity Issues: 2.2, 2.4 Demodulation: not in the book 2 RX nonlinearities System Nonlinearity
More informationDigital Signal Processing
Digital Signal Processing System Analysis and Design Paulo S. R. Diniz Eduardo A. B. da Silva and Sergio L. Netto Federal University of Rio de Janeiro CAMBRIDGE UNIVERSITY PRESS Preface page xv Introduction
More informationBandPass Sigma-Delta Modulator for wideband IF signals
BandPass Sigma-Delta Modulator for wideband IF signals Luca Daniel (University of California, Berkeley) Marco Sabatini (STMicroelectronics Berkeley Labs) maintain the same advantages of BaseBand converters
More informationHY448 Sample Problems
HY448 Sample Problems 10 November 2014 These sample problems include the material in the lectures and the guided lab exercises. 1 Part 1 1.1 Combining logarithmic quantities A carrier signal with power
More informationTETRA Tx Test Solution
Product Introduction TETRA Tx Test Solution Signal Analyzer Reference Specifications ETSI EN 300 394-1 V3.3.1(2015-04) / Part1: Radio ETSI TS 100 392-2 V3.6.1(2013-05) / Part2: Air Interface May. 2016
More informationUnderstanding Low Phase Noise Signals. Presented by: Riadh Said Agilent Technologies, Inc.
Understanding Low Phase Noise Signals Presented by: Riadh Said Agilent Technologies, Inc. Introduction Instabilities in the frequency or phase of a signal are caused by a number of different effects. Each
More informationISSCC 2006 / SESSION 33 / MOBILE TV / 33.4
33.4 A Dual-Channel Direct-Conversion CMOS Receiver for Mobile Multimedia Broadcasting Vincenzo Peluso, Yang Xu, Peter Gazzerro, Yiwu Tang, Li Liu, Zhenbiao Li, Wei Xiong, Charles Persico Qualcomm, San
More informationDevelopment of Signal Analyzer MS2840A with Built-in Low Phase-Noise Synthesizer
Development of Signal Analyzer MS2840A with Built-in Low Phase-Noise Synthesizer Toru Otani, Koichiro Tomisaki, Naoto Miyauchi, Kota Kuramitsu, Yuki Kondo, Junichi Kimura, Hitoshi Oyama [Summary] Evaluation
More informationTechnician License Course Chapter 3 Types of Radios and Radio Circuits. Module 7
Technician License Course Chapter 3 Types of Radios and Radio Circuits Module 7 Radio Block Diagrams Radio Circuits can be shown as functional blocks connected together. Knowing the description of common
More informationMobile & Wireless Networking. Lecture 2: Wireless Transmission (2/2)
192620010 Mobile & Wireless Networking Lecture 2: Wireless Transmission (2/2) [Schiller, Section 2.6 & 2.7] [Reader Part 1: OFDM: An architecture for the fourth generation] Geert Heijenk Outline of Lecture
More informationReconfigurable Low-Power Continuous-Time Sigma-Delta Converter for Multi- Standard Applications
ECEN-60: Mixed-Signal Interfaces Instructor: Sebastian Hoyos ASSIGNMENT 6 Reconfigurable Low-Power Continuous-Time Sigma-Delta Converter for Multi- Standard Applications ) Please use SIMULINK to design
More informationA Simulation of Wideband CDMA System on Digital Up/Down Converters
Scientific Journal Impact Factor (SJIF): 1.711 e-issn: 2349-9745 p-issn: 2393-8161 International Journal of Modern Trends in Engineering and Research www.ijmter.com A Simulation of Wideband CDMA System
More informationDigital Front-End for Software Defined Radio Wideband Channelizer
Digital Front-End for Software Defined Radio Wideband Channelizer Adedotun O. Owojori Federal University of Technology, Akure Dept of Elect/Elect School of Eng & Eng Technology Temidayo O. Otunniyi Federal
More information6.976 High Speed Communication Circuits and Systems Lecture 20 Performance Measures of Wireless Communication
6.976 High Speed Communication Circuits and Systems Lecture 20 Performance Measures of Wireless Communication Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott
More information