The Loss of Down Converter for Digital Radar receiver

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1 The Loss of Down Converter for Digital Radar receiver YOUN-HUI JANG 1, HYUN-IK SHIN 2, BUM-SUK LEE 3, JEONG-HWAN KIM 4, WHAN-WOO KIM 5 1-4: Agency for Defense Development, Yuseong P.O. Box 35, Daejeon, KOREA 5: Division of E & CE, Chungnam National University, Daejeon, KOREA Abstract - With the development of digital processing technology, digital receivers have wide applications in radar systems as well as wireless communications systems. In the digital receivers with intermediate frequency (IF) sampling technique, the analog-to-digital converter (ADC) directly converts IF signal into digital format prior to detection. And the digital signal processor (DSP) using Hilbert transform or the digital down converter (DDC) using the direct digital synthesizer extracts in-phase (I) and quadrature (Q) components from the digital data. In this paper, a digital radar receiver with GC4016 DDC chip is presented. We propose the operating modes and design parameters of the DDC satisfying system requirements and analyze the DDC loss. Key-Words: - radar, digital radar receiver, digital processing, digital down converter (DDC), GC4016, operating mode, design parameter, DDC loss, 1 Introduction The conventional radar receiver is composed of the analog components. Only after signal detection, the detected base-band signal is converted into digital format by ADCs. But the analog components have the common disadvantages of temperature sensitivity, drifts in component values and mismatch between I and Q components, and they restrict the performance of radar systems [1]. Compared with the analog radar receivers, digital radar receivers have two significant advantages as follows: 1) Because digital radar receivers use DDS as local oscillator (LO), they have the characteristics of fast switching, excellent phase noise and extraordinary flexibility [1]. 2) Digital radar receivers, which use IF sampling technique, convert the IF signal into digital format prior to detection. DSP or DDC computes I and Q components of the IF signal in digital domain. Therefore, the increased stability over temperature and time completely eliminates problem due to analog circuits [1,2]. In this paper, we design the digital radar receiver which uses GC4016 DDC chip to compute I and Q components of the IF signal. We propose the Operating modes and design parameters of the DDC satisfying system requirements and finally analyze the system loss due to the DDC. 2 Design of digital radar receiver As shown in Figure 1, digital radar receiver converts the IF signal into digital format prior to the detection. DSP or DDC is used to extract baseband I and Q components from the digital data. The digital radar receiver designed in this paper uses a GC4016 DDC chip as the DDS. Fig. 1 Digital radar receiver. T able 1 shows the radar parameters related with design o f the digital radar receiver. IF frequency is 60MHz, the waveform is linear frequency modulation (LFM) of 140 ISSN:

2 ba ndwidth 2.5MHz, ADC sampling frequency is 48MHz and the rate of the base-band I and Q co mponents is respectively 4MHz. From these pa rameters, decimation factor of the DDC should be 12. Table 1 Radar parameters related with DDC. Parameters Value (MHz) IF frequency 60 Bandwidth * 2.5 ADC sampling frequency 48 I & Q sampling frequency 4 * Waveform = LFM 2.1. GC4016 DDC [3] The GC4016 DDC chip contains four identical downconversion circuits A, B, C and D. Each down co nverter accepts a real sample rate up to 100MHz. F igure 2 shows the block diagram of the single ch annel. Each channel down converts a selected carrier fr equency to zero, decimates the signal rate by a pr ogrammable factor raging from 32 to 16,384 and th en re-samples the channel to adjust the sample rate up or down by an arbitrary factor. P FIR filter have decimation factor of 2. These filters are used to compensate for the droop in the pass-band o f the CIC filter and minimize folding of frequency sp ectrum due to decimation. Especially, split I/Q mode or wideband down-convert mode is applicable to widening bandwidth of the output signal Split I/Q mode Two channels work together in the split I/Q mode to double the output bandwidth of the down converter. As shown in Figure 2, single channel can process two co mponents. In the split I/Q mode, the real half of the co mplex output data is processed in one channel and th e imaginary half in the other. Therefore, the CIC has a minimum decimation 4 instead of 8 and a maximum d ecimation 2,048 instead of 4,096 in this mode. Typically the chip is configured in the split I/Q mode so that channels A and B are combined as one down converter and C and D are combined as the other Wideband down-convert mode It is possible by combining all four channels in the wideband down-convert mode to maximize the output bandwidth. This mode uses the chip in the split I/Q mode described in previous section. The delay of one input sample into PFIR filter will offset the decimation by two so that the channel A and B outputs are the real an d imaginary parts of the even time samples and the C and D outputs are the real and imaginary parts of the o dd time samples. In this mode, the channel A and B outputs should be delayed by one sample. Fig. 2 The down converter channel. As shown in Figure 2, each down-converter con tains a numerically controlled oscillator (NCO) and a mixer to down convert the signal to base-band, fo llowed by a 5-stage cascade integrate comb (CIC) fi lter, a coarse finite impulse response (CFIR) filter of 21 -tap and a precise FIR (PFIR) filter of 63-tap. The C IC filter reduces the sample rate by a programmable fa ctor ranging from 8 to 4,096. The CFIR filter and 2.2. GC4016 DDC operating mode and design values. In this design, the wideband down-convert mode is used to extract I and Q components of 2.5MHz from the IF signal of 60MHz using sampling frequency of 48MHz. The channel A outputs are the I components of the even time samples, the channel B outputs are the Q co mponents of the even time samples, the channel C outputs are the I components of the odd time samples an d the channel D outputs are the Q components of the o dd time samples and then the PFIR filter effectively d oes not decimate the signal. Because decimation fa ctor of the CFIR filter is 2, the CIC filter should h ave the decimation factor of 6. Therefore, the total 141 ISSN:

3 de cimation factor is 12 and the sampling rate of I and Q components becomes 4MHz respectively. In ad dition, the channels A and C should have a zero degree phase shift and the channels B and D should have a +90 degree phase shift. If an ADC samples the signal, which has carrier fr equency of 60MHz, at 48MHz, the frequency spectrum is represented as Figure 3. In order to extract th e base-band components, the spectrum located at 12MHz should be down converted to zero. Therefore, the tuning frequency of the NCO must be 12MHz. Fig. 4 Structure of the CIC filter for GC4016. Fig. 5 Frequency response the CIC filter for R=6. Fig. 3 Frequency spectrum at ADC outputs. 3 The Filter Characteristics and Loss Figure 4 shows the basic structure of the CIC decimation filter used in GC4016 DDC and its stage is five. As shown in Figure 4, the integrator section of the CIC filter consists of 5 ideal digital integrator stages operating at the high sampling f s and its comb section consists of 5 ideal digital comb stages operating at the low sampling rate f s / R where R is the integer decimation factor. The system function for the CIC filter having configuration of Figure 5 referenced to the high sampling rate is 5 R 5 1 (1 ) ( ) = = R z k H z z 1 5 (1 z ) k = 0. (1) F igure 5 shows the frequency response of the CIC decimation filter for R=6 [4,5]. The CFIR filter in this paper uses one of the coefficient sets for the wideband down-convert mode, which are listed in Reference 3. The coefficient set of the filter is shown in Table 2. Figure 6 shows frequency response of the CFIR filter and its cutoff frequency is about 2.5MHz. Though the bandwidth of the base-band signal is assumed as 1.4MHz considering Doppler shift, overlapping of direct and complex conjugate parts of the signal spectrum in the useful frequency is not appeared. Table 2 Coefficient values of CFIR filter. Tap number Coefficient values h(1)=h(21) 47 h(2)=h(20) -102 h(3)=h(19) -1,184 h(4)=h(18) -1,247 h(5)=h(17) 1,487 h(6)=h(16) 3,243 h(7)=h(15) -1,798 h(8)=h(14) -7,760 h(9)=h(13) 15 h(10)=h(12) 20, ISSN:

4 h(11) 32,767 If all filters of DDC have ideal characteristics, magnitude of the complex components at DDC output becomes rectangular waveform when pulsed signal is injected at DDC input. But, in case of using real filters, magnitude of the complex components is distorted. Figure 7 shows magnitude of the base-band signal at GC4016 DDC output, when filters, which have frequency character istics of Figure 5 and Figure 6, are applied to GC4016 DDC. LFM waveform of 2.5MHz bandwidth is used, it has 10us pulse width and range straddling is not occurred. Magnitude distortion of the complex components depends on the filters used in the DDC. This distortion is the same effect that a window function is applied to the input signal of pulse compressor shown in Figure 1. Applied weighting function, processing gain (PG), which is defined as the ratio of output signal-to-noise ratio to input signal-to-noise ratio, is given by w( nt) S o / No n PG = = Si / N 2 i w ( nt) n. (2) In the Equation (2), w(nt ) is weighting function [6]. Finally, because weighting function loss is defined as the decrease of PG due to applying weighting fu nction, DDC loss can be computed as the decrease of P G due to distortion of the magnitude at DDC output. F igure 8 shows DDC loss of the digital radar receiver d esigned in this paper. The loss is smaller than 0.1dB and decreases as pulse-width increases. 2 Fig. 6 Frequency response of the CFIR filter. Fig. 8 Loss of the DDC according to pulse width. Fig. 7 Magnitude of the DDC output (PW : 10us). 4 Conclusions In this paper, digital radar receiver with a GC4016 DDC chip has been presented. We have proposed the operating modes and design parameters of the DDC satisfying system requirements. And DDC loss has 143 ISSN:

5 been analyzed. The loss depends on responses of the filters used in the DDC. The loss can be computed as the decrease of PG due to distortion of the magnitude at DDC output. The digital radar receiver with GC4016 DDC chip in this paper has DDC loss smaller than 0.1dB. References [ 1] Yuanbin Wu and Jinsen Li, The Design of Digital Radar Receivers, IEEE AES Magazine, pp , January [ 2] Zifegn Li et al., Design of A Programmable Digital Down-Converter Structure, IEEE Canadian Conference on Electrical and Computer, IEEE CCECE 2003, vol. 1, pp , May [3] Texas Instruments Inc., GC4016 Multi-standard Quad DDC Chip Data Sheet Revision 1.0, Dallas in Texas, [4] G. Girau et al., FPGA Digital Down Converter IP for SDR Terminals, Signals, Systems and Computers 2002 Conference Record of the thirtysixth Asilomar, vol. 2, pp , November [5] E.B. Hogenauer, An Economical Class of Digital Filters for Decimation and Interpolation, IEEE Trans. On Acoustics, Speech and Signal Processing, vol. ASSP-29, pp , April [6] F.J. Harris, On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform, Proceedings of the IEEE, vol. 66, pp , January ISSN:

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