Analog to Digital Converters

Transcription

1 Analog to Digital Converters ADC review ADC Types Pipelined Data Converter Design Basic concepts eview existing approaches Pipelined Design Strategies 1

2 Analog to Digital Converters Most widely used mixed-signal IC Topic of considerable research interest Emphasis on improving speed, resolution, energy efficiency and yield Performance dominantly determined by soft-yield considerations Statistical analysis often tedious, simulations challenging, engineers itimidated Major challenges looming in moving the ADC to sub-1.5v processes Concern about even operating, maintaining existing performance potential Major reason analog friendly processes are evolving Major challenges in realizing in practical SOC applications Deeply embedded structures difficult or impossible to test Many ADC and DAC in some SOC chips likely Enabling component for many existing and potential applications Many other product opportunities if ADCs that press the performance umbrella can be designed 2

3 Operation of ADC X in ADC n X out CLK f CLK X EF resolution: n N=2 n output codes 3

4 Operation of ADC X in ADC n X out CLK dc Transfer Characteristics f CLK X EF Ideal ADC C N-1 Output Code C k C 2 C 1 C 0 X 0 X 1 X 2 X k X N-2 Input X EF 4

5 dc Transfer Characteristics Ideal ADC C N-1 Output Code C k C 2 X LSB C 1 C 0 X 0 X 1 X 2 X k X N-2 Input X EF Transitiion Point or Break Point 5

6 dc Transfer Characteristics Actual ADC C N-1 Output Code C k C 2 C 1 C 0 X 0 X 1 X 2 X k X N-2 Input X EF Break points not uniformly distributed Order can even be perturbed Some output codes may be missing 6

7 Ideal Spectral esponse to Sinusoidal Excitation Output fundamental Noise Floor f sig f Input Signal Nearly Full-Scale For full-scale input, quantization SN in db given by SN=6.02n

8 Actual Spectral esponse to Sinusoidal Excitation Output Second harmonic SFD peak harmonic Third harmonic f sig 2f sig 3f sig 4f sig 5f sig Distortion introduced by nonideal ADC THD and SFD characterize distortion f 8

9 Typical Spectral esponse Output f sig f 9

10 Effective number of Bits Signal to Noise + Distortion ratio will deviate from that of ideal ADC This results in a reduction of the effective number of bits the ADC can resolve ENOB (effective number of bits) used to characterize how an ADC really resolves excitations ENOB can be defined many ways, popular definition relative to SN if only quantization noise is present: SN=6.02n+1.76 n eff = SND ENOB generally frequency dependent 10

11 SFD SFD esponse to Frequency-Dependent Sinusoidal Excitation f NYQ f 11

12 Spectral esponse to Frequency-Dependent Sinusoidal Excitation n eff n ideal f NYQ f 12

13 Alternate Linearity Metrics - Ideal ADC C N-1 end point fit line Output Code C k C 2 C 1 C 0 X 0 X 1 X 2 X k X N-2 Input X EF 13

14 Alternate Linearity Metrics - Ideal ADC Integral Nonlinearity (INL) C N-1 Output Code C k C 2 C 1 C 0 X 0 X 1 X 2 X k X N-2 Input X EF C 2 X0 X 1 X 2 X k C 1 X N-2 X EF C 0 INL(x) = XOUT (x) Fit Line 14

15 INL of Actual ADC C N-1 Output Code C k Endpoint Fit Line INL(x) C 2 C 1 C 0 X 0 X 1 X 2 X k X N-2 Input X EF 15

16 Code Density INL of ADC C N-1 Output Code C k C 2 INL k Endpoint Fit Line C 1 C 0 T 0 T 1 T 2 T k T N-2 T N-1 Accumulated Tallies Not quite the same as the INL but widely used at test 16

17 Design for Yield in ADCs Many of the key specs of an ADC are limited by soft yield Many engineers attempt to avoid addressing yield issues at design The success of a part will generally depend upon the statistics associated with the design Statistical analysis is often tedious but bit payback possible Yield loss is dramatic for even modest changes in statistics Much of the statistical yield loss can be taken care of with design through area allocation and placement strategies 17

18 Yield Issues Example -String ADC V EF V IN Decoder n V OUT Assumptions: -string Ideal Only errors due to offset voltage of comparators 18

19 Example -String ADC V EF V IN Decoder n V OUT If V EF = 5V, determine the yield if the offset voltage is gaussian with a standard deviation of 10 mv if n =7. Assume the device meets performance specs if the trip point is within.5 LSB of The ideal trip point. 19

20 Example -String ADC If V EF = 5V, determine the yield if the offset voltage is gaussian with a standard deviation of 10 mv if n=7. Assume the device meets performance specs if the trip point is within.5 LSB of the ideal trip point. Solution: 5V VLSB = = 39mV and. 5VLSB = 19. 5mV 7 2 Consider trip point k The probability that trip point k meets the.5 LSB spec is given by p VOS mv = If x n =x/σ where σ = 10mV x= f(x) dx -19.5mV 19.5mV 1.95 p = f n x= 1.95 ( x n ) dx n = 2F(1.95) 1 = 2* =

21 Example -String ADC If V EF = 5V, determine the yield if the offset voltage is gaussian with a standard deviation of 10 mv if n=7. Assume the device meets performance specs if the trip point is within.5 LSB of the ideal trip point. Solution: Thus, the soft yield is Y = p 127 = = This soft yield of 0.13% would be unacceptable in almost all situations epeat the yield if the offset voltage of the amplifier has a standard deviation of 5mV instead of 10mV 21

22 Example -String ADC If V EF = 5V, determine the yield if the offset voltage is gaussian with a standard deviation of 5 mv if n=7. Assume the device meets performance specs if the trip point is within.5 LSB of the ideal trip point. Solution: p VOS mv = If x n =x/σ where σ = 5mV x= f(x) dx 3. 9 p = fn (x)dx = 2F( 3. 9) 1 = 2 * = x= 3. 9 Y = p 127 = = This factor of 2 change in the offset voltage increased the soft yield from 0.13% to 98.8%! 22

23 Example -String ADC What would be the yield if two of the previous -string ADCs were combined to increase the resolution to 8 bits if VOS remains at 5mV? V EF V IN V EF V IN 7-bit Decoder n V OUT 7-bit Decoder 8 X OUT This is a very simple modification that would take minimal effort to make! 23

24 Example -String ADC If V EF = 5V, determine the yield if the offset voltage is gaussian with a standard deviation of 5 mv if n=8. Assume the device meets performance specs if the trip point is within.5 LSB of the ideal trip point. Solution: 5V VLSB = = 19. 5mV and. 5VLSB = 9. 75mV 8 2 If x n =x/σ where σ = 5mV p = fn (x)dx = 2F( 1. 95) 1 = 2 * = x= Y = p 255 = = 1. 51E 6 This seemingly modest change change has a dramatic affect on yield. 24

25 Design for Yield in ADCs A statistical analysis of soft yield is very important if undesirable surprises are to be avoided Even modest changes in specifications can have dramatic affects on yield When a statistical problem starts to occur, it often does so in a relentless way Area dependent standard deviations of performance paramaters often require a factor of 4 increase in area for a factor of 2 reduction in standard deviation A factor of 2 change in standard deviation is generally required for every additional bit of resolution 25

26 Design for Yield in ADCs It is often very tempting to assume the entire error budget can be attributed to each nonideality in an ADC because it may appear to make the analysis easier but it almost certainly will make the design easier But the real yield is dependent upon the combined yield loss mechanisms, not one of the individual yield loss mechanisms! Develop a realistic error budget and use it wisely! 26

27 Major Types of ADCs Oversampled or Delta-Sigma Flash Pipelined Cyclic or Algorithmic 2-step or 3-step flash Successive Approximation Folded 27

28 Oversampled or Delta-Sigma Very accurate at low speeds Use noise shaping to dramatically reduce in-band quantization noise Not applicable at high frequencies Widely used at low frequencies and use expanding as digital feature sizes in a process continue to shring 28

29 Flash Very fast More than 7-bits a challenge, more than 8- bits seldom used Large area for 6 or more bits and area increases with 2 n Widely used in high-speed low-resolution applications 29

30 Pipelined Speed close to that of flash Can get high resolution (14b or a little higher) More area efficient than flash for higher resolution levels Considerable research interest and widespread use in industry 30

31 Successive Approximation Slow Small and low power dissipation easonably good resolution Competitor for oversampled converters but not as popular 31

32 Folded High speed and low resolution Competes in same performance domain as flash Some companies use flash and others prefer folded 32

33 Pipelined Data Converters 33

34 eview of ADC Contributions Consider ISSCC, JSC, CICC and VLSI Symposium 34

35 esolution/performance vs Clock Speed above 10 MHz eported ADC Performance 2000-present (ISSCC, JSC, CICC, VLSI Symp) esolution ENOB (INL) esolution Clock frequency (MHz) 35

36 ENOB versus Clock Speed (above 10MHz) eported ADC Performance 2000-present (ISSCC, JSC, CICC, VLSI Symp) 5 V bipolar esolution ENOB Clock frequency (MHz) 36

37 ENOB versus supply voltage (above 10MHz) 16 eported ADC Performance 2000-present (ISSCC, JSC, CICC, VLSI Symp) 14 esolution ENOB Supply Voltage (volts) 37

38 Low Voltage(<=2V) ADCs (>= 5 MHz) Low Voltage High-Speed ADC Performance esolution (ENOB) V 1.2V 1.4V 2V 1.8V Little in the literature above 10 bits Little in the literature at low voltages 1.2V 1.8V 1.8V Frequency (MHz) 38

39 Standard Pipelined ADC Architecture V ref CLK V in S/H Stage 1 Stage 2 Stage 3 Stage k Stage m-1 Stage m n 1 n 2 n 3 n k n m-1 n m Pipelined Assembler Vres 1 Vres 2 Vres 3 Vres k Vres n-1 D n 39

40 Pipelined Converter Stage V ink Clk Stage k Vref V resk n k V INk S/H AMP V ESk C LK ADC DAC wn k V EF D OUTk 40

41 Pipelined Converter Stage V INk S/H AMP V ESk C LK ADC DAC wn k V EF D OUTk Generally combined into one switched-capacitor gain stage 41

42 Simplified Pipelined Stage V INh AMP V ESh ADC DAC n 1 V EF D OUTh Generally omitted on last stage 42

43 Pipelined Data Converter Ideal Output Example: 1 bit/stage, h = n V EF V in Stage 1 1 bit/stage V res1 Stage 2 1 bit/stage V res2 Stage n 1 bit/stage V resk d1 d2 dn C LK Staggered Depth Shift egister D OUT = <d1 d2 dn> D out n V OUT = V n EF i= 1 d 2 i i 43

44 Pipelined Data Converter Ideal Output V EF V in Stage 1 1 bit/stage V res1 Stage 2 1 bit/stage V res2 Stage n 1 bit/stage V resk d1 d2 dn C LK Staggered Depth Shift egister D out n D OUT = <d1 d2 dn> V OUT = V n EF i= 1 d 2 i i Functional form of output particularly attractive and simple Similar relationship for any integral number of bits/stage 44