DAC & ADC Testing Fundamental

Transcription

1 DAC & ADC Testing Fundamental

2 Outline Specifications of DAC Specifications of ADC Test methodology Static specification Histogram method Transfer (and compare) method Dynamic specification FFT Polynomial Fitting 2

3 Resolution and Accuracy Analog signal input A/D Digital codes output Digital codes input D/A Resolution is a design parameter rather than a performance specification. It only indicates what the theoretical accuracy can be, it does not imply accuracy to a given level Accuracy is used to describe how close a converter comes to meeting its theoretical resolution Accuracy in a converter is limited by Theoretical quantization noise Non-linearity in the transfer function Additional sources of noise in the converter circuitry Analog signal output 3

4 Introduction of DAC Characteristic curve Analog Output 7 Δ 6 Δ 5 Δ 4 Δ 3 Δ 2 Δ 1 Δ 0 A out = V F. S. n i= 1 D 2 i i, where D i is input code Digital Code 4

5 FSR and LSB Size FSR (Full Scale Range) The maximum extremes of output signal for a DAC Current or voltage Devices whose output does not cross through 0 are called unipolar, while those with ± output polarities are bipolar Ideal FSR = Specified by Specs. Actual FSR = Measure Output[ Full LSB (Least Significant Bit) size Scale] Measure Output[ Zero Scale] Ideal LSB is calculated from the specified FSR When testing, an LSB is an expected average value based on the actual length of the transfer curve 5

6 General Specifications of DAC Static specifications Offset error Gain error Differential non-linearity (DNL) Integral non-linearity (INL) Monotonicity Dynamic specifications Settling time Maximum conversion rate Rising/Falling Time Clock Feedthrough Power Supply Rejection Ratio (PSRR) 6

7 Specifications of Special DAC For current output DAC Compliance test For video DAC Glitch Impulse test For high resolution DAC SNR/THD/SFDR test For multi-dacs Crosstalk/Match test 7

8 Offset Error Offset Error Difference between the ideal and actual DAC output values when the zero or null level digital input code is presented to the device Offset Analog Output Error 7 Δ 6 Δ 5 Δ 4 Δ 3 Δ 2 Δ 1 Δ 0 = Measured Zero Scale Output Ideal Zero Scale Output Caused by comparator input offset voltage or current Expressed in %FS or in fractional LSB Digital Code 8

9 Gain Error Analog Output 7 Δ 6 Δ 5 Δ 4 Δ 3 Δ 2 Δ 1 Δ 0 Difference between the measured output when full scale input code is presented and the ideal full scale output Gain Error = Measured Full Scale Output Offset Error Scale Factor Error Ideal Caused by errors in reference voltage, ladder resistor values, or amplifier gain, Digital Code FSR 9

10 Differential Non-Linearity (DNL) Analog Output (LSB) DNL is defined as the difference in the output voltage at a specific input as compared to the output at the previous input minus 1 device LSB DNL DNL i = = DNL 1 = 1LSB [ V () i - V ( i 1) ] real Sign LSB real 1, i = 0 DNL 5 = -0.5LSB K 2 n 1 n ( DNL ) Max( DNL ), i = 0 K 2 1 i i Digital Code 10

11 Integral Non-Linearity (INL) Analog Output (LSB) INL 1 = 1LSB INL 6 = -1LSB Digital Code The deviation of the actual converter output from a straight line drawn between the end points of the converter s inputoutput transfer function INL i = [ V () i - V ( i) ] V ( i) real LSB ideal = real LSB i, i n = 0 K 2 1 INL = Sign n ( INL ) Max( INL ), i = 0 K 2 1 i i 11

12 Monotonic Analog Output (LSB) Non-monotonic Digital Code A monotonic curve has no change in sign of the slope DNL 1 LSB Non monotonic Monotonic DNL < 1 LSB 12

13 Settling Time (I) Analog Output Full Scale Settling Band 50% 0 Settling Time T 1 T 2 Input code from 0 to full scale (dependent on devices) Output settles to within settling band, e.g. ± 0.5 LSB Settling time = T 2 -T 1 DAC speed = (Settling time) -1 Time 13

14 Settling Time (II) [Alternative definition] If slew rate not list in specification Settling time = Delay time + Slew time + Ring time Else Settling time = Ring time 14

15 Maximum Conversion Rate Analog Output Full Scale 0 0 Ramp code (0 to 2 n-1 to 0) test with maximun DAC operating frequency, e.g. 135MHz DAC Most likely the inverse of time required to change from zero scale to full scale output Maximum Conversion 2 n -1 0 Rate = 1 t settle Digital Code 15

16 Rise/Fall Time Analog Output Full Scale 90% Settling Value 10% 0 T 1 T 2 Rising Time Input code from 0 to full scale, Rising time = T 2 -T 1 Input code from full scale to 0, T 3 T 4 Falling Time Time Falling time = T 4 -T 3 16

17 Clock Feedthrough Analog Output Full Scale V pp_out A measurement of clock transition affects output value Input code = Full Scale Clock feedthrough = peak-to-peak value of V out, e.g., 2mV pp or V 20log V pp _ out FS _ out in db, e.g.-30db Time 17

18 PSRR Test ex. 100mV pp, 20KHz sine wave Input code A measurement of immunity of IC to power noise PSRR 1 : : 1 V V = V pp _ out FS _ out pp _ V V DD DD V DD DAC Vout: Full Scale ex. 5mV pp, like noise 18

19 Compliance Voltage Test Caused by the increasing of output voltage DAC V out I out F.S. Current 0.5 LSB Test setup Load x Compliance Voltage V out Code Full Scale DAC + - V out Current Meter, I Voltage Source,V 19

20 Glitch Caused by asynchronous switching Load Load Vout Vout 8I 4I 2I I 8I 4I 2I I Code 0111 Code 1000 Vout -8 Δ -7 Δ Time 20

21 Glitch Test Input code: 8 mv Vout Area1 011K1 100K0 4mv 2mv Area3 + 1 LSB Settling value 0 Area2-1 LSB -5mv 2ns 2ns 1.5ns Time Glitch impulse = 1 2 ( 2ns)( 6mV ) ( 2ns)( 3mV ) + ( 1.5ns)( 2mV ) = 2.5 pv sec Summation is used in DSP-based ATE

22 Frequency Domain Analysis Fundamental Vout: sine wave Digitizer digitized sine wave FFT Amplitude(dB) (a) (b) (c) Harmonic Noise (d) (e) (a) SFDR (spurious-free dynamic rang) (b) SNR (Signal to noise ratio) (c) SNDR (signal to noise and distortion ratio) (d) Dynamic range (e) Average noise level Frequency 22

23 THD and THD+N THD (Total Harmonic Distortion) A ratio of the sum of the amplitude at all harmonic frequencies to the one at the fundamental frequency In practice the sum is limited to seven or nine harmonic terms A negative quantity THD+N (Total Harmonic Distortion plus Noise) Combine the power of noise and the harmonic frequencies 23

24 Dynamic Range A measure of the capability of detecting small input signal Signal Power DynamicRan ge = Maximum Minimum Detectable Power For an audio DAC, it indicates the ability to reproduce low level signals It is calculated by inverting the polarity of the THD+N (-60dB input) and adding 60dB (unit : db) 24

25 SNR and SNDR SNDR (signal to noise and distortion ratio) A ratio of the amplitude at the fundamental frequency to the sum of the ones components at all other frequencies Include noise and distortion SNR (Signal to noise ratio) A subset of SNDR, in which the components for harmonic distortion are not included For an audio DAC, it can be measured with all input data set to zero (no fundamental and harmonic frequencies) (ref: EIAJ CD-DA Std.) 25

26 SNR/THD/SFDR Test Input code: digitized sine wave code V out : sine wave DAC Full Scale Digitized and FFT 26

27 Inter Modulation Distortion (IMD) A test for non-harmonic product terms that appear in a device signal due to undesired modulation of two frequency components of a signal The test is performed by putting a summed two sinusoid tone into a device and looking for frequency components in the sum and difference frequency Second IMD product terms are found at (f 1 ±f 2 ) 27

28 Crosstalk DAC1 V1out or DAC2 V2out V1out: Full Scale V Crosstalk= 20log V pp _ out FS _ out in db 28

29 Match DAC1 V1out DAC2 V2out V1out = V2out = Full Scale Match= V1 V1 FS _ out FS _ out V 2 + V 2 2 FS _ out FS _ out 29

30 Introduction of ADC Characteristic curve output code /8 2/8 3/8 4/8 5/8 6/8 7/8 (1lsb) (2lsb) (3lsb) (4lsb) (5lsb) (6lsb) (7lsb) F.S.(full scale) input level n Di A in = VF. S. + V i i=1 2 offset, where D i is output code 30

31 FSR and LSB Size FSR (Full Scale Range) The maximum extremes of output signal for a ADC Current or voltage Devices whose output does not cross through 0 are called unipolar while those with ±output polarities are bipolar LSB (Least Significant Bit) size Def.1: LSB Vin ( FST ) V in ( ZST ) = N FSR Def. 2 : LSB = N V in (FST) is the full scale transition point V in (ZST) is the zero scale transition point 31

32 Static Specifications of ADC Offset error Gain error Differential non-linearity (DNL) Integral non-linearity (INL) Missing codes Static noise Hystersis error 32

33 Offset Error The difference between the ideal zero point value and the calculated zero point value Offset Error = Vin = Vin ( Zero Scale) Vin( Ideal Offset Point) ( ZST ) 0.5 LSB if Ideal Offset Point 0 Device = Usually expressed as LSBs, volts or percentage of full-scale range (%FSR) 33

34 Gain Error output code /8 2/8 3/8 4/8 5/8 6/8 7/8 ideal real F.S.(full scale) input level Gain Error = FSR Device FSR ideal It is dominated by errors in the converter s reference voltage 34

35 Differential Non-Linearity (DNL) output code DNL i real width ideal width 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 input level ideal real F.S.(full scale) DNL is the difference between adjacent transition points in an actual ADC and an ideal one DNL DNL i = = real widthi ideal width ideal width Sign n ( DNL ) Max( DNL ), i = 0 K 2 1 i i i i = real widthi ideal width i n 1, i = 0 K

36 Integral Non-Linearity (INL) output code align INL 1 INL 2 INL 3 INL 4 INL 5 INL 6 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 F.S.(full scale) input level A measure of maximum deviation of the actual transition points in an A/D s transfer function from the ideal curve INL i INL n = INLi 1 + DNLi = DNLi, i = 0 K 2 1 = Sign n ( INL ) Max( INL ), i = 0 K 2 1 i i j= 1 i 36

37 Histogram test for DNL and INL Uses a linearly increasing or decreasing signal as the input to the ADC under test A 14 bit ADC ramp histogram 37

38 Missing Code Test output code Input Signal: Ramp Full Scale Clock Timing Test Steps: 1. Count the number of each code: n i 2. Check n i > n th 38

39 Static Noise Definition Input Output k A/D h ± ΔL Sampling Little concern in high-speed applications 39

40 Hysteresis Error Hysteresis Error in an ADC causes the voltage at which a code transition occurs to be dependent upon the direction from which the transition is approached It is usually caused by hysteresis in the comparator 40

41 Dynamic Specifications of ADC SNR and SNDR Total harmonic distortion (THD) Inter-modulation distortion (IMD) Spurious-free dynamic range (SFDR) Effective number of bits (ENOB) Dynamic Deviation 41

42 SNR and SINAD SNR is a ratio of the signal amplitude to the noise level When the harmonics are included, the S/N specification is referred to as the Signal-to-(Noise + Distortion) or SINAD Both signal-to-noise specifications exclude any DC offset from the noise component SNR = 6.02n ( db) where, n = number of bits of resolution 42

43 Total Harmonic Distortion (THD) THD relates the RMS sum of the amplitudes of the signal's harmonics to the amplitude of the signal THD 2 2 V f 2 + V f 3 + L = 2 V f 1 1/ 2 where V f1 is the amplitude of the fundamental and V fi is the amplitude of the i-th harmonic If the output of an ADC is fed to a perfect DAC V OUT = a + a 2 3 ( V ) + a ( V ) + a ( V ) + L 0 1 in 2 in 3 in ( cosωt) 1+ cos 2ω = 2 2 t ADCs produce harmonics of an input signal because an ADC is an inherently nonlinear device The THD will decrease if the transfer curve of the ADC more closely resembles a straight line 43

44 Inter-Modulation Distortion (IMD) IMD results when two frequency components in a signal interact through the non-linearities in the ADC to produce signals at additional frequencies An input signal with frequency components at 600Hz and 1kHz (left) suffers severe IMD after A/D conversion (right) 44

45 Dynamic Range and Spurious-Free Dynamic Range (SFDR) Dynamic range is defined as the ratio (usually in db) of the maximum signal size to the minimum signal size For an ideal ADC, it is 20log(2 bits -1) SFDR is the ratio of signal amplitude to amplitude of the highest harmonic or spurious noise component 45

46 Effective Number of Bits (ENOB) ENOB is a specification that is closely related to the SNR ENOB = SNR Some manufacturers define the ENOB using the SINAD instead of the SNR ENOB generally decreases at high frequencies The ENOB specification combines the effects of many of the other dynamic specifications Errors resulting from dynamic differential and integral non-linearity missing codes total harmonic distortion aperture jitter 46

47 Dynamic Deviation Definition Input Output k A/D h ± ΔL Sampling Be used to evaluate dynamic performance of ADC 47

48 Histogram Test A statistical number of samples of the input sinusoid are taken and stored as a record The frequency of code occurrence in the record is plotted as a function of code For an ideal ADC, the shape of the plot would be the PDF of a sine wave The PDF of a sine wave is given by P( V ) = π A 1 2 V A is the sine wave amplitude V is the input voltage 2 48

49 Histogram Test -- DNL Differential non-linearity Differential Non Linearity = actual P( nth code) 1 ideal P( nth code) actual P(nth code) is the measured probability of occurrence and ideal P(nth code) is the ideal probability of occurrence for code bin n The ideal probability of occurrence 1 P( n) = sin π 1 N 1 N 1 ( 2 ) ( ) 1 B n 1 2 B n A 2 N sin A 2 n is the code bin number B is the full-scale range of the ADC A is sine wave amplitude N is the number of ADC bits N 49

50 Histogram Test -- Input Frequency and Example The input and sample frequencies must be relatively independent In realistic, using an input frequency that has a large common divisor with the sample frequency, Ideally, the period of the greatest common divisor should be as long as the record length Example A 100,000-sample histogram for a 9.85MHz sine wave input All discontinuities are less than 1LSB 50

51 Histogram Test -- Examples Large differential non-linearities and numerous missed codes are apparent 51

52 Histogram Test -- Input Waveform Code Bin Code Bin Number of Occurence t 127 t Code Code Bin Code Bin Number of Occurence t 127 Sinusoidal waveform is easier to generate accurately and stably with most signal generator t Code 52

53 FFT Test -- Setup Basic principle Evaluation system 53

54 FFT Test -- Spectrum Interpretation Fundamental Non-linear Distortion from A/D C Quantization Error form A/D C or digitizer FFT Spectrum obtained from A/D C output Random Noise Uncertainty: Timing Jitter Phase Noise Aperature Error 54

55 FFT Test -- Example FFT plots for 0.85MHz data quantized by perfect (a) 10-bit and (b) 6-bit ADCs SNR = 6.02n (a) (b) 55

56 FFT Test -- Example (cont.) Distortion increases with increasing frequency FFT plots for the input frequencies of (a) 9.85MHz and (b) 0.95MHz (a) (b) 56

57 Case Study 3.3V 8bit 135MHz Video D/A C HI bit DAC 57

58 Test Circuit DPS1_GND DPS2_GND DPS1_P(3.3V) 10 μ 0.1μ DPS1_GND(0V) PMU2 MEASURE1_1?Ω VHFMEAS1_1?Ω?Ω Vcca Gnda Out Out 3.3V 135MHz 8bit D/A C D 7... D 0 Vddd Gndd Clk Vref Vcomp 0.1μ 10μ Digital Pins DPS2_P(3.3V) DPS2_GND(0V) Digital Pin 58

59 Linearity Test D/A C output for digital ramp code input DNL = lsb INL = lsb 59

60 Timing Test Settling, Rising, Falling time Rising time = 2.5ns Falling time = 3 ns Settling time = 20 ns with ±1lsb settling band 60

61 Clock Feed Through Test Impedance unmatching Clock feed through Vp-p = 25mV Clock feed through = db 61

62 Glitch Impulse Test ± 0.25 lsb Glitch impulse = 0.51 pvsec. Since this is a Segment D/A C 62

63 PSRR Test Vp-p = 7.33 mv Vout = 718mV Power supply modulated by 20KHz, 100mVp-p sine wave PSRR = %/%ΔVdd 63

64 SNR/THD/SFDR Test Input code: digitized sine wave code FFT Fin = Data rate x cycles / #points Fin/Fs = M cycles / 2 n SFDR: 62.11dB SNR: db THD: db 64

65 Compliance Voltage Test Compliance Voltage Test Output Current (ma) Output Voltage Full_I = 18.5 ma Compliance Voltage =1.7 V 65

66 Case Study 3.3V 10bit 30MHz A/D C AD bit ADC 66

67 Test Circuit DPS1_GND DPS2_GND DPS1(3V) 10 μ 0.1μ AGND AVDD 0.1μ DPS2(3V) 10 μ Digital Pins Digital Pin DPS1_GND DRVDD D0 : : D9 (MSB) DRGND DGND CLK 3.3V 10bit 30MHz A/D C VIN VRLS VRLF VRHF VRHS DVDD Source 1-1 Source 3-1 PMU1(0V) PMU2(2V) 0.1μ 10 μ DPS1(3V) 67

68 Linearity Test A/D C output for Triangle wave input Overflow Underflow 68

69 DNL Test Statistic Analysis DNL #148 69

70 INL Test INL 70

71 SNR/THD/ENOB Test 1MHz sine wave (with socket) FFT SNR : THD : SINAD : ENOB : #cycle = 69, #point =

72 SNR/THD/ENOB Test (cont d) 4.43MHz sine wave (with socket). FFT SNR : THD : SINAD : ENOB : #cycle = 303, #point =

73 SNR/THD/ENOB Test(cont d) 10MHz sine wave (with socket). FFT SNR : THD : SINAD : ENOB : #cycle = 683, #point =

74 Reference (1/2) Specifying A/D and D/A Converters, National Semiconductor Corp. Application Note (AN-156), February 1976 Scott Wayne, Getting the Most from High Resolution D/A Converter, Analog Devices Inc. Appliction Note (AN-313), 1983 The Fundamentals of Mixed Signal Testing, Soft Test Inc. Larry Gaddy and Hajima Kawai, Dynamic Performance Testing of Digital Audio D/A Converters, Burr-Brown Corp. Application Bulletin (AB-104), May 1997 Jim Williams, Component and Measurement Advances Ensure 16-Bit DAC Settling Time, Linear Technology Corp. Application Note 74, July 1998 Using the Analog to Digital Converter, Microchip Technology Inc. Application Note (AN- 546), 1994 Larry Gaddy, Selecting an A/D Converter, Burr-Brown Corp. Application Bulletin (AB- 098), April 1995 Mark Sauerwald, Designing with High-Speed Analog-to-Digital Converter, National Semiconductor Corp. Application Note (AD-01), May 1988 Leon G. Melkonian, Dynamic Specifications for Sampling A/D Converters, National Semiconductor Corp. Application Note (AN-769), May 1991 IEEE Standard for Performance Measurements of A/D and D/A Converters for PCM Television Video Circuits, ANSI/IEEE Standard

75 Reference (2/2) Dynamic Tests for A/D Converter Performance, Burr-Brown Corp. Application Bulletin (AB-072) Walt Kester, James Bryant, Grounding in High Speed Systems, Analog Devices Inc. William C. Rempfer, The Care and Feeding of High Performance ADCs: Get All the Bits You Paid For, Linear Technology Corp. Application Note (AN-71), July 1997 Bill Travis, EDN Hands-On Project: Demystifying ADCs, EDN, pp.26, March 27, 1997 Bill Travis, Remystifying ADCs EDN, October 9, 1997 David A. Johns and Ken Martin, Analog Integrated Circuit Design, John Wiely & Sons, Inc R. W. Stewart and E. Pfann, Oversampling and Sigma-Delta Strategies for Data Conversion, Electronics & Communication Engineering Journal, February 1998 Brian Black, Analog-to-Digital Converter Architectures and Choices for System Design, Analog Devices Inc. Analog Dialogue 33-8,