Data Converters. Технически семинар 21.Октомври.2016 гр. Хисаря 1

Transcription

1 Data Converters Технически семинар 21.Октомври.2016 гр. Хисаря 1

2 Contents: Short product line update ADC architectures - SAR - Pipeline - Flash - Delta-Sigma / Modulator and Decimation ADC Oversampling when and why DAC architectures - R-2R - Resistor string - Voltage (current) source multiplying DAC - Current steering DAC Tools and Resources 2

3 The Signal Chain The Real World #1 Amplifier #2 Data Converter #1 Interface Wireless Connectivity Temperature Pressure Position Speed Flow #1 Power Management #2 Embedded Processing Humidity Sound Light Identification Amplifier #1 #2 Data Converter Clocks & Timing #1 Logic 3

4 TI Data Converters At a Glance 4

5 TI Data Converters At a Glance 5

6 TI Data Converters At a Glance TI offers a variety of data converters, both ADCs and DACs to fit all customer specific applications ADC solutions that provide high accuracy and resolution, fast signal processing, multiple analog inputs and low power. DAC solutions that provide high precision, fast speed, low settling time and audio optimized outputs. Parameter Resolution Value 8 24 Bits # of Channels 1 24 Channels Sampling Rate 10 SPS 5 GSPS Power 200µW 4.4W INL SNR SFDR Interface Size ± 0.09 LSB ±10 LSB 40dB 111 db 42 db 100 db SPI, I 2 C, Parallel, LVDS, JESD204B 1.5x1.5mm 19x19mm (WxL) Parameter Resolution Value 8 20 Bits # of Channels 1 16 Channels Sampling Rate Settling Time Power INL Output Type Interface Size 500 SPS 2.5 GSPS 400 ps 2 ms 15µW 2W ± LSB ± 65 LSB Current, Voltage (Buffered and Unbuffered) SPI, I 2 C, Parallel, LVDS, JESD204B 1.5x1.5mm 14x52mm (WxL) 6

7 ADC Architectures Converter Resolution (bits) Σ Delta Sigma Or Sigma Delta (Oversampling) SAR Successive Approximation Pipeline 8 Conversion Rate K 10K 100K 1M 10M 5G SPS 7

8 ADC Architectures Features SAR Delta-Sigma Pipeline Cost $ 0,53 USD 48,25 USD $$ 0,90 USD 299,00 USD $$$ 3,00 USD 1079,82 USD Power Scales w/ Sample Rate Constant Constant / Scaled With Sample Rate Package Size Smaller Larger Larger Resolution Lower Higher Lower Speed Higher Lower Highest Bandwidth Medium Low High Latency Low High High Application Motor Control/Positioning, Industrial Automation, Test and Measurement Medical (ECG, EEG, Blood Pressure, etc.), Audio, Test and Measurement, Motor Control Wireless/Wireline Communications, Medical Imaging, Radar Systems, Data Acquisition 8

9 ADC Checklist To find the right ADC Architecture? ΔΣ, SAR or Pipeline? SPEED (Sample Rate) and RESOLUTION bits Analog Supply Voltage AVDD Reference Voltage VRef Digital Supply Voltage DVDD Analog Input AiN Number of Channels Muxed or Simultaneous Single Ended or Differential Unipolar or Bipolar Input Voltage Range Output Code Input Voltage Digital Output DOUT Interface: Serial/SPI I²C Parallel LVDS: Serialized or Parallel JESD204B 9

10 Architectures: Speed, Resolution, and Latency Analogy Trying to handle the truth (note: deepness of color is resolution and no converters were hurt for this example) Delta Sigma 16 to 24 bits of resolution Typically Slow 10SPS to 105kSPS Long Latency If I was a camera I would have my aperture open longer SAR 8 to 18 bits of resolution ~50kSPS to 4MSPS No latency If I was a camera I would be have fast shutter speed Pipeline 8 to 14 bits of resolution Up to over 200 MSPS Some clock cycle latency I want to be a video camera when I grow up

11 ADC Successive Approximation Register (SAR) Architecture V IN S/H f S + - Clock FS: Full Scale FS SAR and Control Logic D/A Converter MSB LSB Ref Data Out An N bit SAR converter takes N cycles to complete a conversion. Think Binary Search. From most to least significant bit (MSB to LSB) simple compare functions are done and, when a bit is a 1, that amount of voltage is subtracted from the input signal. SAR s are workhorse converters easy to use simple to understand but are limited in both resolution and speed. FS 2 TI has MANY SAR ADCs! 0 MSB LSB

12 Latency: SARs have none Snapshot ADS bits 4MSPS OK, just a little Acquisition Time Conversion Time = 150ηs Aperture delay = 2ηs If it was a 12 bit pipeline with 2 bits/stage, you would need: 150 ηs Conv t Delay = 6.6MSPS X 6 clock cycle delay = 40MSPS

13 ADC Pipeline Architecture Pipeline converters are another high speed architecture. Several lower resolution converters are put together to result in a fast conversion time. Generally lower power and lower cost than Flash converters, the main disadvantage of a Pipeline converter is that it takes as many clock cycles as there are stages to output the data resulting in latency. STAGE 1 STAGE N ANALOG INPUT SAMPLE HOLD AMPLIFIER ADC DAC + - Sample Hold Amplifier Σ x4 ADC DAC + - Sample Hold Amplifier Σ x4 ADC REGISTER REGISTER Flash ADCs TI has many Pipeline converters! PARALLEL DIGITAL OUTPUT

14 ADC Pipeline Architecture (Flash ADC) Vin Vref Decode Digital Output

15 ADC Pipeline Architecture Data Latency The sample must propagate through the entire pipeline before all its bits are available for combining in the digital-error-correction logic, data latency is associated with pipelined ADCs.

16 Analog Input Bandwidth of a Pipeline ADC 0 G - Gain - dbfs ADS f - Input Frequency - MHz ADS bit, 40-MSPS Pipeline ADC FPBW approx. 550 MHz Full-power BW

17 Delta-Sigma Overview What is a delta-sigma ADC? A 1-bit converter that uses oversampling (can be multi-bit) No DNL Delta = comparison with 1-bit DAC Sigma = integration of the Delta measurement What is the advantage of delta-sigma? Essentially digital parts which result in low cost High resolution What are the disadvantages? Limited frequency response Most effective with continuous inputs Latency

18 The Delta-Sigma Modulator Delta Sigma Signal input, X 1 X + X 3 2 X 4 - Difference Amp X 5 Integrator VMax + - Comparator (1-bit ADC) To Digital Filter 1-bit DAC 4

19 Delta-Sigma Overview Benefits of oversampling: 1. Relaxed antialiasing filter requirements easier to design Pass band (Transition region)

20 Delta-Sigma Overview Benefits of oversampling: 2. The resulting noise power is spread evenly over the complete spectrum. Band of interest

21 The Frequency Domain FFT Signal amplitude Power SNR = 6.02N dB ; (for an N-bit ADC Sine wave input) Quantization Noise Average noise floor (flat) F S / 2 Frequency F S

22 Tests / Oversampling (Quantization error ) Noise Power Output from the filter OSR = 1

23 Oversampling by K Times FFT Power Oversampling by K times SNR = 6.02N dB ; (for an N-bit ADC Sine wave input) Same total noise, but spread over more frequencies Average noise floor k F S / 2 Frequency k F S

24 The Digital Filter Ideal digital filter response Oversampling by K times Power SNR = 6.02N dB + 10 log(fs/2*bw) Noise removed by filter BW k F S / 2 Frequency k F S

25 Noise-Shaped Spectrum Signal Amplitude SNR = 6.02N dB Power The integrator serves as a highpass filter to the noise. The result is noise shaping k F S / 2 Frequency k F S

26 Delta-Sigma Overview Benefits of oversampling: 3. The integrator serves as a high-pass filter to the noise, i.e. noise shaping. Signal amplitude Power Digital filter response HF noise removed by the digital filter k F S / 2 k F S

27 Delta-Sigma Overview

28 1 st order Σ Modulator CLK Vin(t) Integrator Dout(t) D/A 4

29

30 3 rd order Σ Modulator 4

31 Averaging Filters DC input levels Full-scale 0V Delta-Sigma Modulator 1-bit data streams 1-bit data 1/2 full-scale input 1/4 full-scale input 3/4 full-scale input Average 0 Average 1 Average 1 = = = In this case, 4 samples of the 1-bit data were averaged, but any number of samples could have been chosen.

32 Averaging Filters Digital decimation filter operation (example 7 samples / bit ) Output from one bit ADC: x 0 3 x 1 3 x 0 4 x 1 2 x 0 5 x 1 3 x 0 4 x 1 i.e. 0 i.e. 1 i.e. 1 i.e. 1 Output decimation filter ( 7) Decimation, or rate reduction filter. i.e. averages the values and produces n-bit result at a lower frequency.

33 AC Specs SNR (Signal-to-Noise Ratio) RMS value representing the ratio of the amplitude of the desired signal to noise power below one half the sampling frequency. Measure of the strength of a signal to background noise. Contributes to the overall dynamic performance of the device at higher frequencies and affects the linearity at those frequencies. In the audio world, a low signal-to-noise ratio means the device has lots of hiss and static, while a high rating means clear-sounding audio. Fundamental Signal First Harmonic SFDR Second Harmonic THD (Total Harmonic Distortion) The ratio of the sum of the powers of all harmonic frequencies above the fundamental frequency to the power of the fundamental frequency. Average Noise Floor THD is usually expressed in db.

34 AC Specs ENOB (Effective Number Of Bits) - The number of bits achieved in a real system. Is another way of specifying the SNR. ENOB = (SNR-1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this ENOB number of bits. SFDR (Spurious Free Dynamic Range) - The headroom available in an FFT plot. Fundamental Signal First Harmonic SFDR It is the distance in db between the fundamental input and the worse spur. Second Harmonic Average Noise Floor

35 Tests / Oversampling Definitions: Експериментатор : Физик, който експериментира. Теоретик: Физик, който НЕ експериментира. Fundamental SFDR Oversampling: Signal First Harmonic The process of sampling a signal with a signal with a sampling Second Harmonic frequency significantly higher than the Nyquist rate. Oversampling benefits: 1. Much easier Low Pass Filter 2. Improving of the SNR Average Noise Floor

36 Tests / Oversampling Easier Low-pass filter Sampling frequency = fs fs 2*fs Fundamental Signal Sampling frequency = 2*fs Oversampling ration 2 First Harmonic f SFDR Second Harmonic Band of interest fs 2*fs Average Noise Floor

37 Tests / Oversampling Noise sources: Shot noise (статичен) Thermal noise Power Supply Variations VREF variations Phase Noise (sampling frequency jitter) Quantization noise To reduce the noise: Thoughtful board layout baypass capacitor on VREF Oversampling and averaging

38 Tests / Oversampling Number of Samples The input signal is a constant DC voltage The system can be affected From oversampling & averaging Number of Samples N-2 N-1 N N+1 N+2 A Histogram of a System that can be affected from Oversampling and Averaging Techniques. DC Input with White Noise. ADC Codes ADC Codes i.e. If the combined sources of noise in the resultant ADC codes approximates White noise, then oversampling & averaging is a good idea. The noise is correlated Non-linear TF (PS noise, poor INL, ) The oversampling & averaging May not be helpful Histogram of ADC Samples not Optimal for Oversampling and Averaging Techniques.

39 Tests / Oversampling Sensor Analog Input Input interface OpAmp X(t) 10-bit ADC X(n) EXAMPLE: MSP430F1232 Incl. 10-bit ADC - 200ksps, internal Vref=2,5V, 100ppm/ºC TL084ID JFET, IIB = 30pAtyp, THD 0,003%, GBW = 3MHz E(n) Oversampling & Averaging OpAmp role: Amplification/attenuation scaling Vin to ADC input DC offset or level shifting Filtering Buffering (very, very, very high Zin) - impedance matching ADC in may load the source, affecting it - reducing the effect of Cout (ADC Sample and Hold is a cap load) - single-ended to differential

40 Tests / Oversampling MatLab 6.0 (late autumn 2005)

41 Tests / Oversampling EXAMPLE Test Results Gain = 1, Full scale range OSR SNR ENOB Gain = 32, Full scale range OSR SNR ENOB Gain = 235, Full scale range OSR SNR ENOB Gain = 420, Full scale range OSR SNR ENOB

42 Tests / Oversampling EXAMPLE Test Results 12 11, ,5 ENOB 10 9,5 9 8, OSR Gain=1 Gain=32 Gain=235 Gain=420

43 TI DAC Technologies Instrumentation and Measurement Typically for Calibration Converter Resolution Σ Industrial Settling Time (µs) Number of Out put DACs Resistor String Inexpensive R-2R More accurate -Trimmed at final test Typically Voltage out MDAC s (dig control gain/atten, Waveform gen.) Resistor String & R-2R High Speed Video and Communication Update rate (MSPS) Typically 1 Output but a few 2 Output Current out Current Steering Settling Time- µs 1/UpdateRate Setling time

44 DAC Architectures Features String R-2R MDAC Cost $ $$ $$$ Power Low High High Package Size Smaller Larger Larger Resolution Lower Higher Higher Linearity Bad Good Good Settling Time High Medium Low Buffered Integrated Buffer Built In Optional Buffered/Unbuffered No Buffer; Need External Buffer Glitch Energy Low High High Application Walkie-Talkie, ATM machines, Dome Control, 3-wire Field transmitter, PLC MRI scanners, pulse oximetry, mass spectrometer DC load, pulse oximetry 44

45 DAC Checklist To find the right DAC Architecture? Resistor String or Current Steering? Settling Time and RESOLUTION bits Analog Supply Voltage AVDD Reference Voltage VRef : Int or Ext Digital Supply Voltage DVDD Digital Input DIN Interface: Serial/SPI I²C Parallel LVDS: Serialized or Parallel JESD204B Output Code Input Voltage Analog Output AOUT Voltage or Current Buffered or Unbuffered? 45

46 R-2R Architecture R R R R R R R R 2R 2R 2R 2R 2R 2R 2R 2R 2R - + ANALOG OUTPUT ( V OUT ) LSB MSB V R E F + small. Only 2*N resistors required - tight resistor matching required - not inherently monotonic

47 Resistor String DAC Architecture V REF R R R R R R R R 7/8 V REF 6/8 V REF 5/8 V REF 4/8 V REF 3/8 V REF 2/8 V REF VFB 1/8 V REF V + - V OUT = V REF Σ(b i /2 i ) LSB MSB 1 0 1

48 Typical Block Diagrams of a Resistor String DAC V REF VFB DAC REGISTER REF(+) RESISTOR STRING - + V OUT REF(-) Buffered output GND (a) V REF DAC Latch x2 V OUT Data Clock / W E Control and Interface Fixed gain C S Buffer (b)

49 A Voltage source multiplying DAC Fast. Settling times of 100ns or less

50 A Current source multiplying DAC Vcc 1mA 0,5mA 0,25mA 0,125mA MSB LSB

51 Current Steering DACs 2 N -1 Current Sources I I I I OUT Switches determined by digital input Iout + Iout = const I OUT

52 Product Nomenclature ADCs Prefix ADS1xxx Web site price: 0,53 USD to 3299,49 USD Type Delta-Sigma ADCs DACs Prefix DAC1xxx Web site price: 0,38 USD to 109 USD Type Delta-Sigma DACs ADS120x Delta-Sigma Modulators DACx5xx String DACs AMC1xxx Isolated Delta-Sigma Modulator DAC76xx R-2R DACs ADS78xx/ADS8xxx ADS4xxx/ADS5xxx/ ADS6xxx SAR/Nyquist ADCs High-speed (>10 MSPS) DAC77xx DAC88xx R2R High-voltage DACs Multiplying DACs AMC78xx ADCxxxx/LMxxxxx Integrated Precision ADCs and DACs High-speed (>10 MSPS) TLC/TLVxxx DAC5xxx/ THS5xxx String DACs High-speed DACs TLC/TLV5xxx Precision (<=10 MSPS) DAC3xxx High-speed DACs THSxxxx ADCxxx Precision (<=10 MSPS) Precision (<=10 MSPS) AMC78xx Integrated Precision ADCs and DACs 52

53 Tools & Resources Design Tools Anti-Aliasing Calculation Tool for A to D Converters ADC Harmonic Calculator Op Amp to ADC Circuit Topology Calculator Jitter and SNR Calculator for ADCs Loop Filter Calculation Tool Low Cost Loop-Powered 4-20mA Transmitter EMC/EMI Tested Analog Front End (AFE) for Merging Units and Multi-Function Protection Relays Digitally Tunable MDAC Based State Variable Filter 53

54 Tools & Resources 54

55 Tools & Resources 55

56 Tools & Resources 56

57 Tools & Resources Compatible with: 97 Design Kits & EVMs 122 Related devices Designed to support the entire TSW14xx series of data capture and pattern generation 57 cards, including the TSW1400EVM and TSW14J56EVM

58 Tools & Resources 58

59 Tools & Resources Compatible with: 86 Design Kits & EVMs 119 Devices 59 capture and pattern generation card

60 Tools & Resources 60 capture and pattern generation card

61 Tools & Resources 61 capture and pattern generation card

62 Tools & Resources 62 capture and pattern generation card

63 Tools & Resources Compatible with: 21 Design Kits & EVMs 21 Devices JESD204B 63 capture and pattern generation card

64 Tools & Resources Compatible with: 21 Design Kits & EVMs 21 Devices JESD204B 64 capture and pattern generation card

65 Tools & Resources Compatible with: 21 Design Kits & EVMs 21 Devices JESD204B 65 capture and pattern generation card

66 Tools & Resources 66

67 Tools & Resources 67

68 Tools & Resources 68

69 CONCLUSION 69