EE 435. Lecture 40. ADC Design

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1 EE 435 Lecture 40 AD Design

2 Nyqyist Rate Usage Structures. Review from last lecture. 0 Resolution 6 SAR Pipeline 8 4 Flash K 0K 00K M 0M 00M G 0G Speed

3 . Review from last lecture. SAR AD LK IN REF DA n DA ontroller DA ontroller may be simply U/D counter Binary search controlled by Finite State Machine is faster SAR AD will have no missing codes if DA is monotone Not very fast but can be small

4 AD Types Nyquist Rate Flash Pipeline Two-Step Flash Multi-Step Flash yclic (algorithmic) Successive Approximation Folded Dual Slope Over-Sampled Single-bit Multi-bit First-order Higher-order ontinuous-time All have comparable conversion rates Basic approach in all is very similar

5 Flash AD REF IN R R X OUT R d k n : n Encoder n R R L

6 Flash AD with Front-End S/H X IN S/H Flash AD n X OUT LK

7 locked omparator REF Regenerative omparators Φ d k Differential IN DAk Φ Regenerative Feedback Single-Ended Large offset voltage (00m or more)

8 locked omparator DAk OUT IN Φ A Preamplifier with offset compensation Ideally removes all offset effects May not have a large enough gain Regenerative latch often used

9 locked omparator DAk OUT IN Φ A DAk OUT IN Φ A Preamplifier with offset compensation and regenerative latch Gain of preamplifier may still not be large enough

10 Flash AD Summary Flash AD ery fast Simple structure Usually locked Bubble Removal Important Seldom over 6 or 7 bits of resolution Flash AD has some really desirable properties (simple and fast) Wouldn t it be nice if we could derive most of the benefits of the FLASH AD without the major limitations To be practical at higher resolution, must address the major limitation of the FLASH AD Major Limitation of FLASH AD at higher resolutions? Number of comparators increases geometrically --- n

11 AD Types Nyquist Rate Flash Pipeline Two-Step Flash Multi-Step Flash yclic (algorithmic) Successive Approximation Folded Dual Slope Over-Sampled Single-bit Multi-bit First-order Higher-order ontinuous-time All have comparable conversion rates Basic approach in all is very similar

12 Two-Step Flash AD X IN Flash S/H AD DA + Flash AD n n LK LK LK MSB Digital Assembler LSB n X OUT an operate asynchronously (either after first S/H or even w/o S/H)

13 Two-Step Flash AD with Interstage Gain X IN Flash S/H AD DA + A Flash AD n n LK LK LK MSB Digital Assembler LSB n X OUT

14 Three-Step Flash AD with Interstage Gain and S/H X IN Flash S/H 0 AD DA + + A Flash S/H DA AD A S/H Flash AD 3 n n n 3 LK LK3 LK0 MSB LK5 LK LK4 Digital Assembler n X OUT S/H frees first stage to take another sample during second stage conversion This has a pipelining capability

15 Three-Step Flash AD with Interstage Gain X IN Flash S/H 0 AD DA + + A Flash S/H DA AD A S/H Flash AD 3 n n n 3 LK LK3 LK0 MSB LK5 LK LK4 Digital Assembler n X OUT X INk Flash AD k DA k + A k S/H k X OUTk LK n k LK Digital Assembler

16 Pipelined AD X IN S/H Stage r Stage r Stage k r k Stage m r m n n n k n m X OUT =<n :n : :n m >

17 Pipelined AD LK X IN S/H Stage r r Stage r Z - Z - Stage k Z - k Stage m Z - r m n n n k n m Shift Register n X OUT

18 Pipelined AD Stage k Pipeline Stage X INk + A k S/H k X OUTk ADk DAk n k d k REF LK

19 Pipelined AD Stage k Pipeline Stage X INk + A k S/H k X OUTk ADk DAk n k d k REF LK Usually Realized as Single S Block

20 Pipelined AD Stage k Pipeline Stage X INk + A k S/H k X OUTk ADk DAk n k d k REF LK Usually Realized as Flash AD (often simple comparator if n k =)

21 Pipelined AD Stage k Pipeline Stage for bit/stage X INk + S/H k X OUTk ADk DAk d k REF LK O REF IN IN 0 REF IN IN 0

22 Transfer haracteristics for bit/stage O REF IN IN 0 REF IN IN 0 OUT DD IN SS DD SS

23 onsider the following circuit Φ IN OUT X Φ + Φ T

24 onsider the following circuit Φ IN OUT X Φ + During IN OUT + Φ

25 onsider the following circuit During IN OUT + Φ Q Q IN IN

26 onsider the following circuit Φ IN OUT X Φ + During Φ X + OUT

27 onsider the following circuit Q Q IN IN OUT X + During Φ X IN X IN T Q X IN X IN IN T F Q Q Q Define Q T to be the charge transferred from during phase Φ Define Q F to be the total charge on during phase Φ

28 onsider the following circuit During Φ X + OUT F IN X Q F Q F IN X OUTF F IN X

29 onsider the following circuit Φ IN REF Φ d k OUT REF Φ d k OUTF IN X If = = and = - X REF OUTF IN REF

30 onsider the following circuit Φ IN REF Φ d k OUT Likewise REF Φ d k OUTF IN X If = = and OUTF = X IN REF REF

31 Observe Φ IN REF Φ d k OUT REF Φ d k O REF IN IN 0 REF IN IN 0

32 -bit/stage Pipeline Implementation Φ INk + S/H k OUTk IN REF Φ d k OUT DAk REF Φ d k REF d k LK O REF IN IN 0 REF IN IN 0

33 -bit/stage Pipeline Implementation INk REF ADk INk d k d k

34 End of Lecture 40

EE 435. Lecture 41. ADC Design

EE 435. Lecture 41. ADC Design EE 435 Lecture 4 ADC Design Nyqyist ate Usage Structures. eview from last lecture. 0 esolution 6 SA Pipeline 8 4 Flash K 0K 00K M 0M 00M G 0G Speed . eview from last lecture. SA ADC C LK IN EF DAC n DAC