Data Converters. Nyquist-rate A/D Converters. Overview. Flash ADC. Resistor values. Flash converters. Time-interleaved converters. Two-step converters

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1 Data Converters Overview Flash converters Nyquist-rate A/D Converters Time-interleaved converters Two-step converters Pipeline converters Pietro Andreani Dept. of Electrical and Information Technology Lund University, Sweden Folding and interpolating converters Successive-approximation converters Other converter architectures Data Converters Nyquist-rate A/D Converters Flash ADC Fastest conversion: compares the input with n - adjacent quantization levels; output is thermometric needs a decoder for binary output ery high speed, low-to-medium resolution i,, n i<..., Resistive r, i < ref, n ref, ref,( ladder Resistor values Each comparator presents a time-varying load to the ladder charge redistribution after each conversion the unit resistance must be low enough to allow the ladder to pull back all node voltages to the correct values with en error below ½ LSB before the latch phase simulation determine the optimal value for minimum power consumption Data Converters Nyquist-rate A/D Converters 3 Data Converters Nyquist-rate A/D Converters 4

2 Clock distribution over metal wires Step response of metal wires Recall the error due to sampling jitter: χ < χtj dt The timing error must be less than ½LSB = fs / n+ a -bit ADC with signal at 0MHz requires a clock jitter below ps! Clock distribution to the S&H (or T&H) is an issue, because of the distributed time constants in the metal wires! d slope E t for 0 t T Assume a step with a finite slope, ei ( t < TR E for t = TR The step response is given by E σ σt r t t erfc e T R 4t ο <,, ( e t t t T out r r R, 4t ( < σ (, σ, with R σ < RCL u erfc x x, y e dy 0 u <, ο The time constant of the line is roughly T, and it is easy to see C < σ 4 that it does not depend on the width of the interconnection (if larger, R u decreases, but C u increases by the same amount). Typically, R u C u is in the order of a few tens of as λm, leading to T C of ps in presence of a few hundreds of microns of interconnection (however, is this delay a real problem?) Data Converters Nyquist-rate A/D Converters 5 Data Converters Nyquist-rate A/D Converters 6 Clock distribution sensitivity to disturbances R m C ff m T fs u < 40 ς ς; u < 0.5 λ ; R < 50 slope = 0.98 FS /ps slope = 0.8 FS /ps sampling instant with noise, 3 Χ 0 0 χ j < < < 35.7 fs slope 0.8 Distortion and INL Already discussed with resistive DACs: a linear resistivity gradient in the resistance ladder causes INL; the reduced cell pitch in b) is better than a), and even better is the folded layout in c) Matching in modern technologies is % 0- bits without trimming Temperature drift across the ladder can cause INL as well (temperature coefficients as high as %/ºC are possible) noise pulse A noise pulse of 0m FS (e.g. caused by digital switching noise) at the crossing threshold (normalized amplitude of 0.5) results in a jitter of 0. fs and 35.7fs, respectively Less steep slope higher sensitivity to noise χ j more compact Data Converters Nyquist-rate A/D Converters 7 Data Converters Nyquist-rate A/D Converters 8

3 Offset in comparators The different offsets os at the input of two contiguous comparators change the respective quantization interval from Δ to Δ i : os Χ Χ <, <Χ,, od ΧL < Χth ( L and i thr, i thr, i, os, i os, i, For example, an 8-bit flash with FS requires 8 ρ ; 0.6m for a 99.9% yield (i.e., = 3.3ρ ) os os The offset is mainly caused by the pre-amplifier in the comparator; if the transistors in the input differential pair have near-minimum length, the mismatch in threshold voltage (Χ th ) and device length (ΧL) are much larger that those in width and conductivity the inputreferred total offset (usually, a few m) is calculated (next slide) as gs, od thr I < g with Χ < Data Converters Nyquist-rate A/D Converters 9 ds m th A th WL (long-channel expression) Offset in comparators II Explicit calculation for the offset introduced by ΧL: the ideal MOS current equation is W W Χ ds ds ox od ox L Χ I I C C od Ids L Χ < λ λ < L,ΧL L L L Χ I < I ds This is the current error at the output of the amplifier; since it is small, the equivalent Χ in at the input of the amplifier is calculated as in a standard small-signal analysis: ΧIds Ids ΧL od ΧL Χ Ids < gm Χin Χ in < < < g g L L ds Data Converters Nyquist-rate A/D Converters 0 ΧL L In bipolar implementations, the overall offset is often much lower than in CMOS, because of better intrinsic matching + exponential voltage-current relation m m Offset auto-zeroing Offset auto-zeroing II Offset is often too large offset cancellation (auto-zeroing) is needed os os - + ε az - os + - os - + ε az Ε az Two-phase approach during, opamp in unity-gain configuration C os is charged to os - ; during we have at the opamp input: If the offset does not change perfect cancellation; also /f noise is removed white noise is instead doubled, because uncorrelated! Charge injection is an issue (switch in feedback path critical); however, offsets below m are possible (with fully differential architectures) Εaz az ( az ( az ( Ε < Ε, Ε, Ε, Ε, in, opamp os az os az Data Converters Nyquist-rate A/D Converters One input is the S&H output, the other is one of the ladder taps the difference between input and reference is not calculated by a differential pair, but by the previous voltage subtraction on C os at node A! The par. cap. between A and GND is charged to and then to the ladder must charge/discharge quickly enough these capacitances (slowest taps are at the middle of the resistance ladder, as we have already seen) Data Converters Nyquist-rate A/D Converters

4 Example ladder settling Simplified example (n=8) tap #80 takes }5.6ns to settle to less than ½LSB from its nominal level of 0.35 after the ADC converted an input of if this is too long, and the next input is close to 0.35, there may be an error notice also that tap #44 is not constant despite is its exact nominal value this because the ladder must (dis)charge all other nodes as well, and some additional charges must pass through tap #44 as well R < 5 ς, C < 6.5 ff i Data Converters Nyquist-rate A/D Converters 3 Metastability error If the signal in at the input of a comparator is not large enough, the comparator output may be undefined at the end of the latch phase possible error in the output code Input signal pre-amplified during Ε amp, and positive-feedback regenerated during Ε latch even a small input results in a digital output Metastability probability error: P E < < Positive feedback with time constant: σ L < Cp gm tr out, d A σ o in L A o ine 0 is the minimum output voltage for valid logic levels, and period of the latch phase, typically equal to f s Data Converters Nyquist-rate A/D Converters 4 tr e tr, σl is the Metastability error II Practical limits At reasonably low frequencies, the error probability is very low. The comparator must ensure an almost certain output for in > ½ LSB P E must be lower than a given maximum for n <, leading to n, o f sσ L o E < E,max sln FS A PE,max A o FS σl o n P e P f For example, if, n< 8, σ < 0, A < 0, P < 0, 0 3, 4 o FS L o E,max the maximum sampling frequency becomes f s in < < 93MHz 7σ L FS The speed and resolution of flash converters depend on a number of practical limits: ) Small unit resistors in the resistive divider improve resolution and speed, but require higher power and a voltage reference with low impedance from DC to f s very difficult to realize ) Exponential increase in complexity and power consumption with # bits (especially power cannot grow beyond a given budget) 3) Effectiveness of comparators, in terms of metastability probability error at high frequencies, the gain of the pre-amp (i.e., ratio of output signal (at the end of pre-amp phase) to input signal) does not have enough time to reach its low-frequency value Data Converters Nyquist-rate A/D Converters 5 Data Converters Nyquist-rate A/D Converters 6

5 Practical limits pre-amp gain At high frequencies, the dynamic gain of the pre-amp is determined by the current delivered by the pre-amp to C p, yielding a voltage ramp across Φ amp (without reaching its maximum value) the final value of the output voltage is T ing ck ma, < out, pre amp ingm, A ( C <, f C g in ma, out, pre, amp C p p ck p gma, A0 < f C More bits more gain needed more g m,a much more current (x4 for more bit, or for doubling the sampling speed) Example: 7-bit 500MHz flash that needs a pre-amp gain of 0; MOS overdrive od =00m, C p =0.4pF. Since gm < Ids od, we obtain for the diff-pair Idiff, pair < Ids < gmod < A0 fckc p od <.6mA which means that 00mA are needed only in the pre-amp stages ck p Practical limits load on S&H Another important limitation is due to the capacitive load on the input S&H from the par. caps of all comparators, C The total charge on these caps after sampling the ladder taps is n C p ref A full-scale input voltage drains an equal amount of charge from the S&H; this charge must be provided in a fraction of the sampling period; the peak current that the S&H must deliver is which is easily larger than 0mA. n p I = f C Χ n S& H, pk s p in,max To summarize, it is impractical to design an 8-bit flash with > 500MS/s, or a 6-bit flash with > GS/s (however, these numbers improve along with the CMOS technology, of course!) Data Converters Nyquist-rate A/D Converters 7 Data Converters Nyquist-rate A/D Converters 8 A real-life example Overview A. arzaghani et al., A 0.3-GS/s, 6-Bit Flash ADC for 0G Ethernet Applications, ISSCC 03 (Broadcom) 4-channel interleaving Flash converters Time-interleaved converters Two-step converters Pipeline converters Folding and interpolating converters Successive-approximation converters Other converter architectures Data Converters Nyquist-rate A/D Converters 9 Data Converters Nyquist-rate A/D Converters 0

6 Time-interleaved converters Increase the conversion rate by having N converters working in parallel the equivalent conversion rate is N times that of the single converter; the S&H must work at full rate; or, there can be #N S&H working at the reduced rate, but with a very high precision in the distribution of the phases. Important remark: gain and offset errors in each ADC, which are usually of minor weight, are very important here, because they become dynamic errors! Accuracy requirements clock If #N S&H working at the reduced rate, and clock misalignment across the ADCs looks like clock jitter, but with N T S periodicity. If the clock misalignment between the K th and st channel is χ k, the error introduced is δ d nt < χ n< in K in ck, K K ; dt nt which, for the sinusoidal input < A sin ϖ t(, becomes in in in nt ( < A nt ( δck, K χk inϖin cos ϖin The power of the error due to clock misalignment becomes, as a function of the input power and N: P < P χϖ N δckk, in k in Furthermore, because of the down-sampling of the input with a clock error at frequency fs N, the clock misalignment gives rise to images located at kfs fin N Data Converters Nyquist-rate A/D Converters Data Converters Nyquist-rate A/D Converters Accuracy requirements offset Offset identical offsets in all ADCs have no major impact; offset mismatch causes tones offset on a signal channel causes a pulse of amplitude equal to the offset tones at f N and its multiples Interleaved converter is for large bandwidths signal occupies a large fraction of the Nyquist interval even tones at relatively high frequencies are likely to fall into the signal band Worst case alternate sequence of positive and negative offsets os square wave of amplitude os st harmonic with amplitude 4 os ο ; SFDR with full-scale input sine wave becomes οfs SFDR < 0 log 8 If the SFDR requirement for maximum input equals the SNR, the offset mismatch should obey the relation 4 Χ ο os os LSB ο Χ< Χ< 4 6 S os Accuracy requirements gain error Identical gain errors in all ADCs have no major impact; gain mismatch between the channels causes tones worst case if gains alternate between (+ε G ) and (-ε G ), which gives rise to an error equal to the multiplication of the input signal with a square wave of amplitude ε G at f s / (or its sub-multiples) Largest spur tone occurs at f s / ±f in (or f s /4 ±f in,...), and has amplitude resulting in A 4 < δ A ο spur G in ο SFDR < 0log 4 δ G Thus, even with ε G as low as 0.%, the SFDR is not higher than 58dB Bottom-line: time-interleaved ADCs always need trimming/calibration if high resolution is desired Data Converters Nyquist-rate A/D Converters 3 Data Converters Nyquist-rate A/D Converters 4

7 Overview Sub-ranging / Two-step converter Flash converters Time-interleaved converters Two-step converters Pipeline converters Folding and interpolating converters Successive-approximation converters Other converter architectures K= sub-ranging; K> (e.g. M ) two-step K possible clocking scheme (fast!) Data Converters Nyquist-rate A/D Converters 5 Data Converters Nyquist-rate A/D Converters 6 Advantages # comparators much reduced: if 8-bit and M=N=4, we need 4 comparators instead of 8 in the full flash!, ( < 30, < 55 The spared area and power are much more than what is needed in the DAC and residue generator If K= M, the dynamic range of the amplified residue equals that of the input signal coarse and fine ADCs can share the same reference S&H loaded only by M, comparators Conversion rate is in principle reduced, as -3 clock periods are needed per conversion However, since the speed of the S&H is the bottleneck in mediumresolution full-flash ADCs, the clock of the sub-ranging can actually even end up being faster, as the reduced capacitive load of the S&H enables a faster S&H Accuracy requirements For medium resolutions, the quantization step is m or more the capacitance required to keep kt/c smaller than ½ LSB is not very large For instance, if C=0.5pF, kt C < 90λ up to 0b, the input capacitance is not a problem in the S&H design The residue is given by for ( < K, i i, ; ; i res in in DAC coarse in coarse Ideally, the residue is a saw-tooth with amplitude between 0 andfs K Below is instead the residue with a real coarse ADC and an ideal DAC M K < M Data Converters Nyquist-rate A/D Converters 7 Data Converters Nyquist-rate A/D Converters 8

8 Accuracy requirements II A residue outside the range of the LSB ADC results in all zeros (ones) until its input re-enters the boundaries (after the MSB ADC has changed) The DAC, on the other hand, generates the subtractive term a DAC error alters the residue as in the figure below (where the ADC is ideal) Important: shift caused by DAC lasts an entire tooth accuracy demands on the DAC are more stringent than on the ADC (whose errors are easier to correct, as they are localized around the break points either by inserting extra thresholds outside the 0- FS region, or with the same technique that will be discussed later for pipeline ADCs) Residue conversion Possible situations for the fine conversion, with 4-bit LSB depending on the errors affecting the residue ideal repeats both 0000 and repeats, misses 0000 and 000 misses 0000 and Data Converters Nyquist-rate A/D Converters 9 Data Converters Nyquist-rate A/D Converters 30 Overall picture ADC errors (middle curve) only around MSB transitions; after - LSB from MSB transitions, the response is again on the ideal interpolation line DAC errors affect whole LSB range Two-step as a non-linear conversion The generation of the residual is equivalent to the action of a non-linear block Χ DAC Χ DAC Χ DAC The non-linear operation alters the signal spectrum by generating extra tones a narrow-band input can spread over the whole Nyquist range amplifier and fine ADC must work well above Nyquist in order to avoid degradation in the LSB conversion The spectrum of the residue is only weakly correlated with the input (provided the amplitude is a few MSBs at least) distortion in the LSB blocks look more like white noise than tones linearity of the residue generator is not critical SDR and SFDR set by coarse ADC and DAC Data Converters Nyquist-rate A/D Converters 3 Data Converters Nyquist-rate A/D Converters 3

9 Flash converters Time-interleaved converters Two-step converters Pipeline converters Overview Folding and interpolating converters Successive-approximation converters Other converter architectures From two-step ADC to pipeline ADC Cascade of individual stages, each performing one of the elementary functions required by a sequential algorithm The pipeline unwinds over space and time what would be performed over time by a purely sequential scheme The simplest sequential scheme is the two-step algorithm, which uses two clock periods, one for MSBs and one for LSBs the pipeline version delivers MSBs and LSBs in one clock period, in this way: the first stage yields the MSBs of the current signal sample, while the second stage yields the LSBs of the previous sample Typically, pipeline ADCs are multi-step (> ) Data Converters Nyquist-rate A/D Converters 33 Data Converters Nyquist-rate A/D Converters 34 Pipeline ADC Successive approximation with pipeline each stage of the pipeline generates or more bits, plus the difference between input voltage and internal DAC voltage accuracy of analog signal must comply with the desired # of bits (in general, different stages may deliver different # of bits) Digital logic combines the bits coming from K stages outputs at full rate, but with a delay (latency) of K+ clock cycles not a problem, unless the ADC is inside a feedback loop Generic pipeline stage The subtraction of DAC from in gives the quantization error, which, after amplification, determines the new residue voltage ζ <, (, j K j b res j res DAC j The dynamic range of the residue equals that of the input if, for an n j -bit n DAC, the gain is j this is very frequently the case, as it allows the use of the same reference voltage in all stages b 7 -b 6 timing example for a 0-b, 5-stage, -b per stage pipeline ADC the 6 th clock cycle is used by the digital logic to combine the 0 bits and make them available at the output Data Converters Nyquist-rate A/D Converters 35 Data Converters Nyquist-rate A/D Converters 36

10 Residue generation (a) input between - R and R, bit the DAC adds ½ R when the input is negative, and subtracts ½ R when the input is positive; with K=, the residue varies again between - R and R (b) 3 bits the amplitude of the quantization error is at most ± R /8, and K=8 makes the residue vary again between - R and R -b DAC Accuracy requirements Accuracy requirements are of course greater in the first few stages most demanding is the input S&H Non-idealities of ADC, DAC, and K cause limitations similar to those studied in the two-step ADC threshold errors in the ADC cause the residue to be either greater or lower than full scale at the break points b R R/ R R/ - R H = R / L =- R / However, the residue generator can still correctly provide the difference between the analog input and the quantized signal from the DAC the error will be generated by the ADC in the next stage, since this ADC will not be able to correctly convert residues outside ± ref this observation is the basis of the digital error correction technique to be treated next 3b Data Converters Nyquist-rate A/D Converters 37 Data Converters Nyquist-rate A/D Converters 38 Accuracy requirements II Digital error correction We observed that in the two-step ADC the DAC errors modified the residue over a whole LSB segment, impacting the INL also in the pipeline ADC the accuracy of any DAC, referred to the input of the pipeline, must be better than the required INL, and better than LSB to ensure monotonicity (after a few stages, DAC linearity is of minor concern) If the interstage gain has an error, G< χg, the slope of the residue is either increased or decreased, causing an error that is zero in the middle, and maximum at the endings of the segments at the break points, the error inverts its sign, giving rise to a step change which, referred to the input, must again comply with INL and monotonicity requirements n j ref Χ < χg We observed that the dynamic range of the residue can exceed the reference, but no error is made until the following ADC cannot convert correctly an out-of-range signal Reduce the interstage gain? Difficult, as an attenuation different from / is difficult to account for Add additional levels to the ADC of the stage? Good idea, because: ) the redundant levels avoid generating out-of-range residues, and ) provide info to the digital domain (hence the name of the technique) to fully compensate for the ADC error Consider a -b DAC, which usually requires an ADC with threshold to ensure enough redundancy, at least thresholds are needed Since a -b ADC needs threshold and a -b ADC needs 3, the use of thresholds is referred to as a.5-b conversion (very popular) It is possible to apply the same approach to multi-bit DACs Data Converters Nyquist-rate A/D Converters 39 Data Converters Nyquist-rate A/D Converters 40

11 Digital error correction II The input is divided into 3 regions: one below the lower threshold th,l, one between the two thresholds, and one above the upper threshold th,h if the separation of the two thresholds is large enough, a signal below th,l is certainly negative, and above th,h is certainly positive Uncertainty arises in the middle region close to the zero crossing, an error may lead to a residue exceeding the limits The residue generator adds ref / if the ADC provides a certain 0, and subtracts ref / if the ADC provides a certain but does not add anything in the uncertainty region here the residue is the simple amplification by of the input Digital error correction III Errors χ th,l, χ th,h on the thresholds change the value of the residue at the break points, but the residue remains within ± ref if χ th,l (χ th,h ) is lower than th,l ( th,h ) (assuming that th,l and th,h are close to the midpoint, i.e. to zero in the figure) in the case below, the input range for certain 0 diminishes, and increases for certain (of course, th,h should be lower than ref /, and th,l higher than - ref /, if the residue should remain within ± ref which is easily accomplished) The info provided by the.5-b converter is a flag in the LSB position, which is set to when the uncertainty region is detected the whole code becomes: 00 for certain 0; 0 for certain ; and 0 for uncertainty. Data Converters Nyquist-rate A/D Converters 4 Data Converters Nyquist-rate A/D Converters 4 Digital error correction I The digital logic sums the outputs, taking into account the weight of each stage the gain of each stage is the weight of the uncertainty flag is equal to the MSB in the next (lower) stage adders are needed In the example below, notice that the uncertainty in the 3 rd stage is corrected by the 0 of the next two stages, while both the 0 of the 4 th stage and the 0 of the 5 th stage become 0 The last, 6 th stage does not have an extra threshold, as its uncertainty cannot be resolved by further comparisons -b.5-b Digital error correction example Assume ± ref = ±, and in = ref (/4 + /8 + / ) ref = = 000 If th,l = -0.5, th,h = 0.5, we have the following residue sequence: , , 0.33, 0.66, , 0.064, corresponding to the binary outputs: 0, 00, 0, 0, 00, 000, as expected If now shift on thresholds: th,l = -0.30, th,h = 0.0, the sequence becomes , , 0.33, , , 0.064, corresponding to the binary outputs: 0, 00, 0, 00, 00, still 000! With thresholds th,l = -0.0, th,h = 0.30, the sequence becomes , , 0.33, 0.66, 0.53, 0.064, corresponding to the binary outputs: 00, 0, 0, 0, 0, again 000!! Data Converters Nyquist-rate A/D Converters 43 Data Converters Nyquist-rate A/D Converters 44

12 Dynamic performance The dynamic performance depends on slew-rate and bandwidth of S&H and residue generator a step with amplitude out becomes a ramp during slewing, and turns into an exponential when feedback takes over the equations are (as already derived in an earlier lecture) out ( t < SR t t ; t slew, t, tslew ( σ out < out,χ = slew t e t t Χ < SR σ; t < SR, σ; σ < αϖ slew out T feedback factor Behavioral simulations Much faster than transistor-level simulations, give a good starting point for the design here, the achievable SFDR and SNR vs. the slew-rate of the key blocks are estimated the different impact of the different blocks is also very easy to determine The next stage S&H samples after T S /, and the (non-linear) settling error becomes, TS, tslew ( σ Χ <Χ e err It is important to have a small error in the first stages, but in later stages is less important, because the input-referred error is divided by the gain of all preceding stages op-amps in later stages do not need to be as highperforming it is possible to save power Data Converters Nyquist-rate A/D Converters 45 Data Converters Nyquist-rate A/D Converters 46 Residue generator: op-amp f T and feedback amplifier An amplifier is needed for residue generation Consider an amplifier, built with a feedback factor β around an op-amp having a unit-gain frequency of f T :, in t( A s( α A s( out t( ϖ T The (linear) time response to an input voltage step is: A fb ϖ s( (, t σ out ( t < in ( t, e (; σ < < αϖ οα f T out t A s < < < t αa s in ϖt s ϖt s ϖt < < αϖ s αϖ s s αϖ T T T T Accuracy and clock frequency ( An n-bit ADC needs an accuracy better than, n (= ½LSB ), which means that the settling time is set by the inequality ( σ, t sett σ, n e ; t = n ln We may assume that the time allowed for settling is half a clock cycle; thus TCK οα ft < = tsett fck ; < f t n ln CK φ f f = T CK = sett sett n ( ln οα ( Data Converters Nyquist-rate A/D Converters 47 Data Converters Nyquist-rate A/D Converters 48

13 Example: from op-amp f T to conversion bandwidth For instance, if we have <800MHz, then οα f ( σ < < 0.398ns For a 9-bit ADC requiring clock periods per conversion we have: With an anti-aliasing filter margin of one octave (i.e., a factor of ), the signal band is T t < σ n ln < 0.398ns ns sett fck fck < 64 MHz fsampling fs < < 8MHz t sett f T Residue generator Capacitors are used for both sampling and D/A conversion; the residue is where the DAC control bits are thermometric from the ADC An amplification of n n gives rise to a feedback factor α < to keep the time constant σ independent of n, the unity-gain frequency of the op-amp must grow as n more than 3 bits per stage not suitable for high conversion rates N i <, res in DAC N fb fs, fb fs S f, f < f f < f < S B B B MHz sampling residue Data Converters Nyquist-rate A/D Converters 49 Data Converters Nyquist-rate A/D Converters 50 Residue generator II With bit α=/3 ( caps are needed at the input to implement the gain x) speed can be improved with the flip-around circuit shown below, where α=/, since input and feedback capacitance are equal (however, is the op-amp really open-loop during sampling?) If C U ()=C U (), the input voltage is doubled (one cap changes polarity compared to the other), but the gain for DAC is only - it is necessary to double the value of the references. A real-life example D. ecchi et al., An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS, JSSC 0 (Broadcom) distortion, mainly 3 rd -order, dominated by (band-pass) PGA before ADC sampling residue Data Converters Nyquist-rate A/D Converters 5 Data Converters Nyquist-rate A/D Converters 5

14 Flash converters Time-interleaved converters Two-step converters Overview Folding Two-step dynamic range divided into MSBs, with linear input-output relations inside each MSB An equivalent non-linear transformation is the folding of a straight line shown below folding once around FS /: bit; twice around FS /4: bits; three times around FS /8: 3 bits; and so on Pipeline converters Folding and interpolating converters Successive-approximation converters Other converter architectures The number of intervals required to quantize the folded signal diminishes accordingly after an M-bit folding, only N-M - comparators are needed for the N-bit conversion Obviously, it is necessary to know from which folded segment the input is coming, to determine the MSBs Data Converters Nyquist-rate A/D Converters 53 Data Converters Nyquist-rate A/D Converters 54 Folding II Real folding The M-bit folder produces two signals: the analog folded output, and the M-bit code identifying the segment used in the folded response The gain stage possibly boosts the dynamic range of the analog folded output to FS The N-bit ADC determines the LSBs, and finally the logic block combines MSBs and LSBs to deliver N+M bits Any circuit implementing folding in not able to achieve infinitely sharp transitions corners are always more or less rounded The error is estimated by unfolding the folded response monotonicity is sure, but INL may be high In general, working on different segments results in different delays Folding is normally used for high conversion rates and medium-high resolutions finite bandwidth and slew-rate in folding block are crucial Data Converters Nyquist-rate A/D Converters 55 Data Converters Nyquist-rate A/D Converters 56

15 Double folding Double folding avoids the issue of the non-linear regions present in simple folding higher linearity, but also higher complexity Two transfer characteristics, out-of-phase by ¼ of the folding period one is always in the linear region The logic must decide which of the two characteristics should be used Current folding with BJTs 4-segment folding of input current if I in is zero, bias currents I E flow into one branch, into the other the diff. output voltage out,d is zero If now 0 < I in < I E, the current through Q is reduced, and we have out, d < RI When I in becomes higher than I E, the current through Q is zero and some current flows through D and is taken from Q, obtaining out, d <, RL Iin, IE ( When D becomes active, the output voltage becomes positive again, to return to negative when D 3 is turned on Notice that the input voltage must increase by one diode voltage for every active cell dynamic range at input sets the limit to the number of cells L in Data Converters Nyquist-rate A/D Converters 57 Data Converters Circuits for Data Converters 58 Current folding with MOS 8-segment folding of input current the use of comparators is more efficient than MOS diodes; the comparator detects an increase of the source voltage of the respective MOS switch, and turns on the switch the threshold B should be slightly higher than A - tn,h however, the + and - inputs of each comparator should be swapped in the figure below! Comparators increase complexity and power consumption, but the voltage drop across the switches is small, and many cells can be cascaded oltage folding Segments (here: 4) generated by the linear region in the transfer function of a differential pair T for BJT, od for MOS too small! extended with degeneration resistors by as much as I S R D, as the diff. pair becomes fully unbalanced for an input voltage of IS RD od ( the differential output voltage changes by IR S L Data Converters Circuits for Data Converters 59 Data Converters Circuits for Data Converters 60

16 Interpolation Interpolation value intermediate between two other values With voltages implemented with resistors, or capacitors a) and b) With currents implemented with current mirrors c) Accuracies of 0.% can be expected with good layout Interpolation in flash converters Comparators substituted with pre-amp reduced # pre-amps and ref. voltages (but not # latches) cap. load on the S&H diminishes less power consumption, higher speed; fewer ref. voltages less chargepumping effect less stringent settling limit Often used with 4 or 8 resistors (not just as here) inter R R < R R Ε ( < inter C C C C W L( W L( W L( W L( < ; <,, i, i ( I < I, I inter Data Converters Nyquist-rate A/D Converters 6 Data Converters Nyquist-rate A/D Converters 6 Interpolation in flash converters II To preserve linearity, the pre-amp output should saturate only for an input higher than the closest upper threshold, and lower than the closest lower threshold. The overlapped non-saturated regions, interpolated by the resistors, determine zero-crossings mid-way between the pre-amps zero crossings. Far from the zero crossings, the slope of the interpolated curve diminishes, but then the differential signal is already large enough for the latch. Data Converters Nyquist-rate A/D Converters 63 o o (i-) o (i) o (i+/) o (i+) o (i-/) ref (i-) ref (i) ref (i+) linearity region for o (+/) pre-amps outputs in Folding with interpolation Multiple interpolators take the place of the fine flash converter (a) shows the interpolation between two folded responses ( F and F ), shifted by half segment; the shape of the interpolated segment is more rounded than the generating signals; but, again, it is important that it is linear only close to the zero crossing (b) interpolating F and - F yields a second set of zero crossings, detected by additional comparators (c) if R = 3R, the zero crossing is at ¼ distance from the zero crossing of F multiple interpolations can yield a sufficient number of crossings to obtain the LSB conversion avoids the use of an explicit flash ADC, possibly increasing the conversion rate Data Converters Nyquist-rate A/D Converters 64

17 A real-life example Overview R. C. Taft et al., A.8.0GS/s 0b Self-Calibrating Unified-Folding-Interpolating ADC with 9. ENOB at Nyquist Frequency, ISSCC 009 (National Semiconductors) Flash converters Time-interleaved converters Two-step converters Pipeline converters Folding and interpolating converters Successive-approximation converters Other converter architectures Data Converters Nyquist-rate A/D Converters 65 Data Converters Nyquist-rate A/D Converters 66 Successive-approximation converter bit converted per clock cycle (plus or cycles for signal sampling + settling) Binary search reduced complexity and power, but lower conversion rate The MSB distinguishes between input signals that are above or below FS /; depending on this result, the threshold for determining the nd bit is either FS /4 or 3 FS /4; and so on (below: 3-b conversion) The voltages used in the comparisons are generated by a DAC driven by a successive-approximation register (SAR) SAR timing diagram After signal S&H, the SAR sets the MSB to ; if the comparator confirms, the is retained, otherwise is set to 0; then the nd bit is processes, and so on until all bits have been generated; then a new signal sample is processed Data Converters Nyquist-rate A/D Converters 67 Data Converters Nyquist-rate D/A Converters 68

18 SAR algorithm The name of the algorithm comes from the fact that the voltage from the DAC is an improving approximation of the voltage from the S&H occasionally, the error can be larger than in the previous step (as from 4 th to 5 th bit below), but the final error is surely not larger than successive divisions by of the full-scale amplitude Example below: search path for S&H = FS (= 0/56 FS ) S&H = FS Algorithm with error If there is an error in the bit evaluation, the error propagates along all successive steps for instance, this may happen if DAC changes from a level well below S&H to a level just above S&H (4 th clock period below) if the comparator recovery from overdrive is not fast enough, an error may occur in the case below, we end up with a conversion error of LSBs. Occurs typically at the beginning of the conversion, when overdrive is large Error correction techniques expand the search range near the end, to accommodate for initial inaccuracies however, extra clock cycles needed S&H = Data Converters Nyquist-rate A/D Converters 69 Data Converters Nyquist-rate A/D Converters 70 Charge-redistribution SAR-ADC The charge sampled at the beginning of the conversion is redistributed on the capacitor array, to obtain a top-plate voltage close to zero at the end Binary-weighted capacitances + one comparator only one activedevice block, which is not even particularly critical very attractive for nanometer CMOS processes! During Φ S, sampling array connected between in and ground total charge becomes: C < n C tot u in Charge-redistribution SAR-ADC conversion MSB bottom plate of largest capacitance n, C to ref, rest of the array to GND superposition yields the voltage on u the top plate: comp ( ref <, This voltage is the difference between MSB and input only necessary to compare it to zero = GND, very convenient; if MSB=, the connection of the largest cap to ref is kept during the nd comparison; otherwise it is restored to ground in Data Converters Nyquist-rate A/D Converters 7 Data Converters Nyquist-rate A/D Converters 7

19 SAR-ADC conversion II Thus, during the second comparison, the top plate voltage becomes ref ref comp < MSB, 4 which is used to find the nd bit; and so on for all bits The parasitic capacitance at the top plate attenuates the generated voltage by a factor : n Cu < n C C u p in SAR-ADC conversion good features reduces the voltage value, but not its sign, which is the relevant info this is a consequence of pre-charging the top-plate to zero the top-plate voltage is zero at sampling, and almost zero at the end of the conversion The input common-mode range of the comparator is zero without using op-amps or OTAs Only the comparator and charging/discharging the array determine the power consumption very power efficient (however, this does not take into account the generation of REF ) Auto-zeroing of the comparator to avoid offset errors comparator is connected as a unity-gain buffer and used to pre-charge the top plate during sampling Capacitive attenuation can be used to limit the capacitive spread in the array Data Converters Nyquist-rate A/D Converters 73 Data Converters Nyquist-rate A/D Converters 74 Example of SAR-ADC F. Borghetti et al., A Programmable 0b up-to-6ms/s SA-ADC Featuring Constant FoM with On- Chip Reference oltage Buffers, ESSCIRC 006 (Univ. Pavia, Italy, and DTU, Denmark) CMOS Technology 0.3 µm P6M Core area [mm ] 0.75 Power Supply []. Power consumption [mw] 3. Sampling frequency [MS/s] 5.5 INL/DNL [LSB] 0.6/0.55 ENOB [bits] 9. HD3 IM3 [dbc-fs] 7 FoM [pj/conversion] Data Converters Nyquist-rate A/D Converters 75 Power-efficient SAR ADCs Since the publication of Maloberti s textbook, a number of charge-sharing SAR ADCs have been proposed, which can improve the power efficiency of the standard SAR ADC, even by a very large amount! (see. Hariprasath et al., Merged capacitor switching based SAR ADC with highest switching energy-efficiency, Electronics Letter, ol. 46, No. 9, pp. 60-6, 9 th April 00) Data Converters Nyquist-rate A/D Converters 76

20 Energy consumption, conventional SAR (slightly modified) Example with 3-bit SAR Energy consumption I : is it really necessary? The same is found for - : <? All C are charged to ref - in ; then the top plates are switched to GND, and thus + becomes equal to ref - in (because charge is not lost); then the MSB is switched to ref, and by superposition we obtain: 4C 3 <, ( <, 4C 4C ref in ref ref in 3 <,, ref ip Data Converters Nyquist-rate A/D Converters 77 3, ref in The ΧQ that ref must deliver for switching 4C in the upper half is Thus, considering that the lower half draws as much from ref as the upper half, the total energy delivered by ref is E < ΧQ < 4C (half is stored in the caps, half is lost in the series resistance (no matter how small it is)) 3, same amount of ref on both sides! ref ip 3 Ζ ( Χ Q< 4C Χ,Χ < 4C,,, 0,, < C a b ref ref in ref in ref Data Converters Nyquist-rate A/D Converters 78 ref ref Energy consumption II Energy consumption III Again, we look at how much charge ref must deliver for the switching 5 3 Χ Q < Χ Q < C,,, 0,, < 5C 4 tot ref ref in ref in ref 3 3, ref in, ref ip , ref in, ref ip, ref in, ref in Χ Q < Χ Q< 4C,,,,, C,,, 0,, < C 4 4 tot ref ref in ref ref in ref ref in ref in ref Data Converters Nyquist-rate A/D Converters 79 Data Converters Nyquist-rate A/D Converters 80

21 Energy efficiency of conventional SAR It has been recognized that the conventional capacitor array switching scheme of the SAR ADC is energy inefficient Since much of the energy is consumed in switching the capacitors in capacitor array, it is important to find more efficient ways of operating it The so-called merged capacitor switching technique allows an amazing improvement of the energy efficiency SAR with merged capacitor switching (MCS) Again, example with 3-bit SAR Sample the input directly at the comparator input the MSB comparison does not consume any energy from ref or cm, and 4C can be removed as well! Thereafter, bit after bit, cm is set to either ref or GND in the top array (and the opposite in the bottom array) Data Converters Nyquist-rate A/D Converters 8 Data Converters Nyquist-rate A/D Converters 8 Merged capacitor switching (MCS) II(a) If cm = ref /, all switching is symmetrical around cm, which does not have to source or sink charge (some C is pulled up by ref cm = cm on one side, and the same C is pulled down by cm on the other side) ref cm < Χ,Χ ΧQ ΧQ Χ Q < 0 cm Merged capacitor switching (MCS) II(b) The first UP and DOWN transition are symmetrical, and consume the same amount of energy detailed calculations, in ref cm ip, cm Χ Q < C,,,, ref cm ( top, ref ref in ref cm cm in < C, Χ Q < C,,,, cm ref ( top, cm cm in ref cm cm in < C, Χ Q < C,,,, < C bot, cm cm ip cm cm ip cm Same results (swapping top and bot) Data Converters Nyquist-rate A/D Converters 83 Data Converters Nyquist-rate A/D Converters 84

22 Merged capacitor switching (MCS) II(c) Merged capacitor switching (MCS) III ref If cm < Χ Q < C, ( < C ref ref cm ref Χ Q < C, < 0 cm cm ref The energy consumed by ref is E < Χ Q < C ref ref ref ref 3 3, 4 4 in ref cm 3 ip, 4 cm, in ref cm ip, cm 3, 4 in ref cm 3, 4 4 ip ref cm Χ Qtop 3 3 < C ref, in ref, cm, ref, in ref, cm C ref, in ref, cm, cm, in ref, cm 4 4 < C ref, cm 4 4 Χ Q bot < 0 Χ Q < C ref 8 we focus solely on ref Χ Qtop 3 < C ref, in ref, cm, ref, in ref, cm 4 < Ccm Χ Qbot 3 < C ref, ip ref, cm cm ip cm 4 4,,, 3 < C ref, cm ( 4 5 Χ Q < C ref 8 Data Converters Nyquist-rate A/D Converters 85 Data Converters Nyquist-rate A/D Converters 86 Merged capacitor switching (MCS) I Merged capacitor switching (MCS) conventional MCS E avg, conventional E avg, MCS n : i< n : i<, C n, i i ref, C n, 3, i i ref E avg, conventional E avg, MCS : 6 Behavioral simulations of 0-b SAR with different switching schemes More than 93% power saving! Data Converters Nyquist-rate A/D Converters 87 Data Converters Nyquist-rate A/D Converters 88

23 Example of of advanced SAR-ADC SA-ADC Overview P. Harpe et al., An Oversampled /4b SAR ADC with Noise Reduction and Linearity Enhancements Achieving up to 79.dB SNDR, ISSCC 04 (TU Eindhoven, The Netherlands) Flash converters Time-interleaved converters Two-step converters Pipeline converters Data-Driven Noise Reduction Noise reduction on the noise-critical bit-cycles by voting on multiple repetitive comparator decisions Folding and interpolating converters Successive-approximation converters Other converter architectures Data Converters Nyquist-rate A/D Converters 89 Data Converters Nyquist-rate A/D Converters 90 Cyclic (or algorithmic) converter Uses the same cell for converting one bit per clock cycle n+ clock periods to convert n bits; the voltage at the output of OTA is the same as the residue of the first stage of a -b per-stage pipeline: OTA < in, REF < in, REF sig REF Integrating converter (dual slope) The integration capacitance is charged by the input voltage over a time of N clock cycles, and then we count the number k of clock cycles that the reference voltage needs to discharge it. ery slow method, but if the signal bandwidth is narrow, it can yield a very high number of bits. Notice that the conversion accuracy is independent of the time constant RC (to the first-order). C R out Tsig out TREF t T T RC RC sig REF out <, sig < REF k, sig < N REF N Tclk ktclk Data Converters Nyquist-rate A/D Converters 9 Data Converters Nyquist-rate A/D Converters 9