Phase-Change Via-Based Reconfiguration of RF, Analog and Mixed-Signal Circuits

Transcription

1 SRC E-Transfer Workshop April 10 th, 2012 Phase-Change Via-Based Reconfiguration of RF, Analog and Mixed-Signal Circuits Jeyanandh Paramesh Electrical & Computer Engineering

2 SRC Task Overview Anticipated primary result Validate technology and transformation techniques for configurable RF vias based on phase change materials Develop configurable RF IC building blocks such as inductors Develop configurable RF circuits such as LNA s, VCO s and PA s based on phase change vias Other funding: DARPA MEMS-Instrumented Self-Configuring IC s Collaborations IBM PC-CMOS Chip Fabrication Data Storage Institute, Singapore Phase-change layer deposition Slide 2

3 Outline Introduction Phase change material choices for RF Reconfigurable planar inductors Reconfigurable LC VCO Design Fabrication & integration Characterization Reconfigurable low-offset CMOS comparator Phase-change based non-volatile look-up table Slide 3

4 Introduction Slide 4

5 People Cheng-yuan Wen Larry Pileggi Jeyanandh Paramesh Greg Slovin Eng-Keong Chua James Bain Ed Schlesinger Slide 5

6 Phase-Change Materials Amorphous state High impedance Crystalline state Low impedance Proposed for NVM s in early 1960 s by Ovshinsky Material: Chalcogenides Ge X Sb Y Te Z, e.g., GST, GeSb Applications CMOS-based non-volatile memories NV-RAM Re-writeable DVD s and CD s (contrast in reflectivity) Slide 6

7 Temperature Phase Transformation Amorphizing pulse Melting point (~600C) Crystallizing pulse Glass transition point (~200C) Time Two distinct phases Amorphous with high R OFF Crystalline with low R ON R OFF /R ON ~ 10 3 to To transform to crystalline (R ON ) Heat PC material above crystallization temperature Allow PC material to cool gradually, allowing it to crystallize To transform to amorphous (R OFF ) Hear PC material above melting point Quench (Cool) PC material rapidly, allowing no time for crystallization Transformation is reversible Slide 7

8 Phase-Change Vias Via structures commonly used in NVM Electrode Electrode Electrode SiO 2 Electrode Si Mushroom cell Phase change SiO 2 Si Line cell Typically implemented low in metal stack e.g., between transistor contact and M1 Slide 8

9 Phase-Change Vias: CMU structure A: Cu Cu B: Cu Phase change (Ge 50 Te 50 ) SiO 2 Si State of phase-change via makes or breaks connection between nodes A & B Thick top metal for low trace resistance Structure necessary for transformation in RF Slide 9

10 Phase-change Chip Fabrication SiO M 1 (Cu) SiO 2 2 Si PC via (GeTe) TiW SiO 2 M 2 (Cu) Si coated with 10 µm SiO 2 Sputter 500 nm Cu to form M 1 (underpass) Sputter 80 nm SiO 2 and pattern to define vias locations Sputter 100 nm GeTe and 60 nm TiW to form PC vias Sputter 480 nm SiO 2 and lift-off Sputter 2 µm Cu to form M 2 (inductor layer) Slide 10

11 Phase-change material choices for RF Slide 11

12 RF Apps: Current Multiband XCVR Front-end Module CMOS RF/Analog Chip CMOS Digital Chip LNA ADC LNA LNA ADC LNA Configurable Digital Signal Processor PA PA DAC PA DAC PA Slide 12

13 Phase-change Via Reconfigurable Multiband XCVR LNA 90 o Phase-change Configuration PLL PA 90 o Slide 13

14 Tri-band Reconfigurable LNA Concept ~1.2V in 130nm CMOS 2nH 2nH 0.6nH In Re-configurable transistor bank L max L mid L min 64μm/0.18μm 64μm/0.18μm 32μm/0.18μm S1 256μm/0.12μm 128μm/0.12μm 64μm/0.12μm PC vias L max 9nH 3nH 0.75nH 0.45nH 0.2nH 0.15nH S2 S3 L mid L min Slide 14

15 Choice of Phase-change material for RF L 1 L 2 L 1 L 2 R ON C L 1 L 2 R ON or (R OFF ) R OFF Need low on resistance C 0L1 0L1 Q: R R R C 1 2 on Need relatively high R OFF. Need low C Slide 15

16 Choice of Phase-change material for RF Ideally want material with low r ON and high r ON /r OFF ratio GST originally proposed for CMOS NVM Need huge A PC with GST to maintain Q of configurable inductors This causes three problems Large parasitic capacitance degrades SRF Large PC area Need high power to transform PC via Large thermal capacitance of via prevents fast quenching required to turn via OFF Requires new material Slide 16

17 ρ (Ω-m) Material Requirements st transition R ON too high Common for PCRAM 1 st transition 2 nd transition Non-volatile memory Medium ρ OFF /ρ ON. Fast transition Ge 2 Sb 2 Te 5 ρ OFF (10 Ω-m) ρ ON (10-3 Ω-m) (first knee) Temperature ( C) ρ ON (10-5 Ω-m) (second knee) Simone Raoux et al., Direct observation of amorphous to crystalline phase transitions in nanoparticle arrays of phase change materials, JAP, 102, (2007) Slide 17

18 ρ (Ω-m) PC Material Comparison GST 2 nd drop GST 1 st drop Ge 15 Sb 85 GeTe GeTe best suited for RF 18 Slide 18

19 Reconfigurable Inductors Slide 19

20 Switched Inductor Approaches (I) Series Inductor S1 L max PC vias S2 S3 L mid L min PC Via in signal path Has to carry bias + signal current Unwanted crystallization Slide 20

21 Switched Inductor Approaches (II) Coupled inductor L 2 Φ 2 R 1 M 12 SW G S i 1 P 2 G P 1 L 1 i 2 P 1 L 1 L 2 R 2 P 2 Φ 1 If SW is ON, opposite Φ 2 induced by i 2 Effective flux at P 1 reduced L eff decreased ω k12l2 L eff = L 1 (1 - b b = 0 or 1 ) '2 2 2 R ω k 2 +ω 12L2L 2 L eff = L 1 (1 - b ) b = 0 or 1 '2 2 2 R 2 2 ', M k L L 2 +ωl 2 L1ω k12l2 R2 ' R eff = R 1 + b 2 2 ', M R 12 = 2 k R L R1 L 2 SW '2 2 2 L1 R ω k 2 +ω 12L2LR 2 ' R eff = R 1 + b 2 R 2 = R 2 + RSW '2 2 2 R 2 +ωl Slide 21

22 Comparison If the mutual inductance that is switched is higher than the series inductance switched in, then coupled version better than series version for identical L-ratio Mutual inductance switching works better for smaller inductance switching ratios (~ 2:1) Series inductance switching works better if large inductance ratios are desired Ref: Kossel et. al., JSSC Feb 2009 Slide 22

23 Inductance (nh) Quality Factor (Q) 1 st Gen Reconfigurable Inductor (2.28) (2.11 GHz, 2.3) in series 5.53nH 8X in series outer spiral outer spiral 0.74nH (0.75) (2.9 GHz, 0.94) Freq (GHz) Quality factor is low Design uses values of Ge 15 Sb 85 from literature ** Freq (GHz) Simulation Measurement Ge 50 Sb 50 used instead no reports of prior characterization in literature ρ off ρ on R off /R on (Ω-m) Ge 50 Sb 50 (sheet films) x10-4 (annealed) Ge 50 Sb 50 (patterned devices) 1.7x x10-4 (probe transformation) Ge 15 Sb 85 (sheet films) x Slide 23

24 2 nd Generation Reconfigurable Inductor PC via 100 µm P 2 L 2 SW Regular via L 1 1 µm P 1 Slide 24

25 Current (A) Single GeTe via Measurement PC via Ω GSG port 1 GSG port point measurement w/ source meter Source I GeTe via 31.5 kω Voltage (V) V Sense V Slide 25

26 Transformation & Characterization PC switch SW PC switch transformation + - PC switch SW Pulse generator P 1 P 2 PC switch Measurement + Source meter - PC via PC via Regular via Slide 26

27 PC switch Resistance (Ω) Transformation Pulse Sequence 100K 10K 1K kω 1 st crystallization 151 Ω 31 Ω 18.1 kω 1.53 kω 4 th amorphization 421 Ω 3 rd amorphization 2 nd amorphization nd crystallization 1 st amorphization 1 Ω 2 µs 2 µs 2 µs ms µs 5 ns 9.7 V 5 ns 5 ns 3.8 V 5 ns V 0.2 µs V V µs Slide 27

28 RF Measurement L & Q PC switch SW SW G S R 1 G VNA L 1 L 2 P 2 P 1 R 2 P 1 P 2 Measure S-parameters Extract inductance & Q from S-parameters Slide 28

29 Inductance (nh) Inductance (nh) Inductance measurement Simulation As-deposited Re-amorphized Measurement Simulation (fully turned on) Frequency (GHz) Frequency (GHz) Slide 29

30 Quality Factor Quality Factor Quality Factor measurement Simulation As-deposited Re-amorphized Frequency (GHz) simulation (fully turned on) Measurement Frequency (GHz) Slide 30

31 Reconfigurable LC VCO Slide 31

32 Need for Switched-Resonator VCO Switching from high to low frequency with fixed L: g 1 R s m 2 2 RP L start-up bias current & power increases as frequency If L is set to optimize for low frequency: PN 10log 2kTF Rs 1 4 LC V rms Vrms ~ VDD at low frequency If bias current is kept constant, Vrms remains roughly at VDD since VCO is voltage limited C decreases PN increases Trade-offs become worse in wide-tuning oscillators Slide 32

33 Switch Requirements for Analog, Digital & RF Requirement CMOS Switch PC (GeTe) via Switch R OFF /R ON > 10 4 R ON 1 Ω NFET Area 360 μm 2 NFET C parasitic 430 ff PC via Area 0.2 μm 2 PC via C parasitic 3 ff ** *Assume minimum feature size = 50 nm **C parasitic dominated by electrodes C gd PC via Probe access PC via switch C P C C db CMOS switch R P C Slide 33

34 Heterogeneous Integration PC/CMOS/N-MEMS PC switch Integrate CMOS and phase-change process Flip-chip bonding Navigate to reconfiguration points Reconfigure with MEMS tri-tip probe RF VCO MEMS chip PC inductor CMOS chip (face down) Pad for I/O, power, etc Phase-change chip (face up) Solder bond Slide 34

35 PC chip CMOS chip Cross-section of Integrated System Si substrate CMOS chip metal stack 17μm Solder Ball MA 4 μm thick top metal M3 M1 Si substrate Slide 35

36 Floorplan IBIAS VCONT VDD VDD VCONT IBIAS CLK CLK GND GND DATA_IN VDD2 DATA_OUT GND OUT GND Inductor on PC chip Coupling controlled Inductor on CMOS chip Coupling controlled GND OUT GND GND OUT GND Inductor on CMOS chip Series connection Inductor on PC chip Series connection GND OUT GND DATA_IN VDD2 DATA_OUT GND GND CLK VDD IBIAS VCONT VDD VCONT CLK IBIAS Slide 36

37 Example Schematic: Series L on PC Chip I bias V cont V DD V out V SS PC switch Solder bumps PC chip CMOS chip GSG pads CMOS switch 8C 8C 4C 2C C 4C 2C C V O + Buffer V O - Slide 37

38 Inductors on CMOS Chip CMOS inductor CMOS inductor Solder bumps PC switch Two layers stacked Solder bumps PC switch PC via PC via R PCVIA R PCVIA C PCVIA C pad C PCVIA C pad C trace,pc L trace,pc R trace,pc C trace,pc L trace,pc R trace,pc R solder R solder Ctrace,CMOS L trace,cmos R trace,cmos C trace,cmos L trace,cmos R trace,cmos Inductor CMOS Inductor CMOS To NFET To NFET Slide 38

39 Inductors on PC Chip Bond pads on CMOS chip Bond pads on CMOS chip PC switch PC switch Solder ball Solder ball R PCVIA R PCVIA C PCVIA C pad C PCVIA C pad Inductor PC Inductor PC R trace,pc R trace,pc C trace,pc L trace,pc C trace,pc L trace,pc C trace,cmos R solder C trace,cmos R solder L trace,cmos R trace,cmos To NFET L trace,cmos R trace,cmos To NFET Slide 39

40 Inductor Details in Each VCO IND on CMOS/ Coupling controlled IND on PC/ Coupling controlled IND on CMOS/ Series Connection IND on PC/ Series Connection L nh 1.75 nh 1 nh 1.04 nh L nh 0.12 nh 1.57 nh 1.75 nh L OFF 0.40 nh 1.20 nh 4.31 nh 4.30 nh L ON 0.25 nh 0.87 nh 0.93 nh 0.99 nh k Coupling controlled Series Connection L OFF = L 1 L ON = L 1 (1 k 2 ) L OFF = L 1 + L 2 + 2k L 1 L 2 L ON = L 1 Slide 40

41 Inductance (H) Inductance (H) Inductance (H) Inductance (H) Simulated L s and Q s 2E E E-08 8E-09 4E E-09 3E-09 2E-09 1E-09 IND on CMOS/Series Connection PC SW ON PC SW OFF 0 0 5E+09 1E E+10 2E+10 Frequency (Hz) IND on PC/Coupling Controlled PC SW ON PC SW OFF Q Q 2E E E-08 8E-09 4E-09 1E-09 8E-10 6E-10 4E-10 0 IND on PC/Series Connection PC SW ON PC SW OFF 0 0 5E+09 1E E+10 2E+10 Frequency (Hz) IND on CMOS/Coupling Controlled PC SW ON PC SW OFF Q Q E+09 1E E+10 2E+10 Frequency (Hz) 2E E+09 1E E+10 2E+10 Frequency (Hz)

42 Flip Chip Test Chip 50 μm x 50 μm Solder Bumped Pads 100 μm pad pitch 30 μm solder ball diameter Top Chip Bottom Chip Top Chip Bottom Chip Successfully Flip Chipped Device Bottom Traces Top Traces Slide 42

43 Integration of CMOS with PC wafers PC Device Wafer CMOS Chip Slide 43

44 PC Device Wafer Zoom-In electroplated tin bumps Bond pads for connection to CMOS inductor PC vias RF probe pads for PC transformation 25x35 µm 100 µm Slide 44

45 Bonded CMOS and PC Chips VCO supply & bias 100 µm Coupling controlled IND on CMOS chip VCO RF out Slide 45

46 PC switch transformation with GSG probes Inductor on CMOS chip GSG probes Inductor on PC chip GSG probes 25 µm 2 PC bridges in parallel 25 µm Slide 46

47 VCO Output Spectrum PC OFF state PC ON State Note: 12 db Amp used at output in this measurement Slide 47

48 Frequency (GHz) Power (dbm) Tuning Characteristics & Output Power (GSG1) PC SW ON PC SW OFF ! 1.3 db cable/connector loss not de-embedded PC SW ON PC SW OFF Control Code/Band Index Control Code/Band Index VCO with series connected inductor on CMOS Phase-change reconfiguration switches have one bridge In each PC state (amorphous or crystalline) Discrete frequency tuning with switched capacitors controlled by scan chain Continuous frequency tuning with varactors Some codes missed due to blown buffer at input to scan chain Slide 48

49 Frequency (GHz) Continuous Varactor Tuning (GSG1, PC OFF) PC SW OFF V tune (V) Band 1 Band 2 Band 3 Band 4 Band 5 Band 6 Band 7 Band 8 Band 9 Band 10 Band 11 Band 12 Band 13 Band 14 Band 15 Band 16 Multiple bands missed due to scan chain failure Slide 49

50 Frequency (GHz) Continuous Varactor Tuning (GSG1, PC ON) 4.4 PC SW ON Band 0 Band 1 Band 2 Band 9 Band 10 Band 11 Band V tune (V) Band 13 Band 14 Band 15 Slide 50

51 Phase Noise (dbc/hz) Phase 1 MHz Offset PC SW ON PC SW OFF Control Code/Band Index Slide 51

52 Phase Noise: PC ON State, Band 15 Band 15: V tune = 0V, Vdd 2 = 0V IND on CMOS/Series Connection/PC switch ON state Slide 52

53 Phase Noise: PC OFF State, Band 12 Band 12: V tune = 0V, Vdd 2 = 0V IND on CMOS/Series Connection/PC switch OFF state Slide 53

54 Reconfigurable VCO Summary In-house process developed with new (GeTe) material with ultra-low R ON. Reconfigurable inductors demonstrated Heterogeneous process flow developed CMOS chip with four VCO flavors designed and bonded to PC chip All four VCO s are functional One VCO has been characterized exhaustively PC transformed a few times Reliability, retentivity and performance with repeated cycling to be characterized Slide 54

55 Reconfigurable Low-offset CMOS Comparator Slide 55

56 PCRAM Cells in CMOS Process M 1 TiN M 1 CA WL BL CA GST TiN Poly CA GST layer n + n + gnd Substrate Cross-section of PCRAM mushroom cell Ge 2 Sb 2 Te 5 (GST) phase-change layer R OFF /R ON 10 2, R ON 30KΩ Slide 56 Slide 56

57 Mismatch in Differential Pairs Systematic mismatch Layout dependent Alleviated by careful design Random mismatch Need mitigation techniques Most common approach is Pelgrom sizing IN+ IN- M 1, V th1, M 2, V th2, (W/L) 1 (W/L) 2 CLK 1 ( W / L) V ( V V ) V 2 ( W / L) os GS th th 1 ( V V ) V OS 2 ( W / L) 2 GS th 2 2 W / L V 2 th Slide 57 Slide 57

58 Dynamic Latched CMOS Comparator VDD Latch Widely used in flash ADCs Power efficient High speed Reducing offset voltage relies on good matching CLK OUT- OUT+ CLK Challenging in sub-100nm technology nodes IN+ IN- CLK Diff-pair Slide 58

59 Calibration Techniques Pelgrom sizing Redundancy Select ONE from N elements Statistical element selection Select k from N elements To Latch IN+ IN+ IN+ CLK CLK SEL 1 CLK IN+ IN- IN- IN- IN- SEL 2 SEL 3 Diff-pair 1 Diff-pair 2 CLK Diff-pair 3 SEL N Diff-pair N Slide 59

60 Comparator with Parallel Diff-pairs VDD CLK OUT- OUT+ CLK IN+ IN- IN+ IN- IN+ IN- V OS1 V OSN V OS8 CLK Diff-pair 1 Diff-pair N Diff-pair 8 Slide 60

61 SES Comparator with PCRAM VDD CLK OUT- OUT+ CLK IN+ IN- IN+ IN- IN+ IN- V OS1 V OSN V OS8 CLK Diff-pair 1 CLK Diff-pair n CLK Diff-pair 8 BL 8 BL n BL 8 PCRAM Switch PCRAM Switch PCRAM Switch WL 1 ~WL 25 Slide 61

62 PCRAM Cell Array Implementation BL 1 BL 2 One PCM switch BL 8 WL 23 WL 1 WL 2 WL 24 WL 25 Controlled by WL decoder Slide 62

63 Tunable Pulse for Transformation Tunable pulse rise/fall time, amplitude and pulse width Use thick gate device for high amplitude pulse Vdd PG Amorphization pulse I f I r I r Crystallization pulse t width, in Output pulse I f Input pulse Slide 63

64 MUX Bit-line Control Signal Generation DEC BL control inputs 8 BL 1 ~BL 8 Xform BL (2.5V) Xform EN Bring 1 BL to high from 8 BLs during Xformation Disconnect all BLs during normal operation Slide 64

65 Word-line Control Signal Generation 5 WL control inputs DEC Pulse 5 Input Generator Pulse WL 1 ~WL 25 Xform EN Sending pulse to WLs sequentially during Xformation Bring all WLs to high during normal operation Slide 65

66 Vos (mv) Measured Offset Voltage (comparator A) Vos = 0.5mV when differential pairs are configured as ( ) Trial index Run all possible combinations of selecting 4 out of 8 (70 trials) V OS =+28.5mv by Pelgrom sizing (select all) 8 C 4 Slide 66

67 Vos (mv) Measured Offset Voltage (comparator B) Trial index Vos = +1.5mV when differential pairs are configured as ( ) & ( ) Vos = -1.5mV when differential pairs are configured as ( ) & ( ) Run all possible combinations of selecting 4 out of 8 V OS =-5.5mV by Pelgrom sizing (select all) Slide 67 Slide 67

68 Non-volatile Look-up Table Slide 68

69 Conventional Look-up Table Conventional LUT store logic functions in SRAM cells Significant leakage power Vdd Input b 0 -b n-1 Decoder Replace SRAM cells with PCRAM cells Comparable size No standby power Non-volatile SRAM Cell SRAM Cell MUX output SRAM Cell Programming Block Address A 0 -A n-1 Slide 69 Slide 69

70 PCRAM-based LUT Top phase-change cell array V top = 2.5V/1V for Xform/Operation PC P1 PC P2 PC P3 PC P4 PC P5 PC P6 PC P7 PC P8 WL WL WL WL WL WL WL WL BL P1 BL P2 BL P3 BL P4 BL P5 BL P6 BL P7 BL P8 C C C C C C C C B B B B A A A A Out B B B B C C C C C C C C BL N1 BL N2 BL N3 BL N4 BL N5 BL N6 BL N7 BL N8 WL WL WL WL WL WL WL WL PC N1 PC N2 PC N3 PC N4 PC N5 PC N6 PC N7 PC N8 Bottom phase-change cell array V bottom = 2.5V/0V for Xform/Operation Slide 70

71 PCRAM-based LUT Xform Mode Top phase-change cell array V top = 2.5V PC P1 PC P2 PC P3 PC P4 PC P5 PC P6 PC P7 PC P8 WL pulse BL P1 BL P2 BL P3 BL P4 BL P5 BL P6 BL P7 BL P8 C C C C C C C C B B B B A A A A Out WL pulse B B B B C C C C C C C C BL N1 BL N2 BL N3 BL N4 BL N5 BL N6 BL N7 BL N8 PC N1 PC N2 PC N3 PC N4 PC N5 PC N6 PC N7 PC N8 Bottom phase-change cell array V bottom = 2.5V/0V for Xform/Operation Slide 71

72 2.5 V PCRAM-based LUT Operation Mode Top phase-change cell array V top = 1V PC P1 PC P2 PC P3 PC P4 PC P5 PC P6 PC P7 PC P8 C C C C C C C C B B B B A A A A Out B B B B C C C C C C C C PC N1 PC N2 PC N3 PC N4 PC N5 PC N6 PC N7 PC N8 Bottom phase-change cell array V bottom = 0V Slide 72

73 Characterization of Propagation Delay A B C Vdd PCRAM LUT (DUT) LUT A Vdd Replica LUTs LUT programmed to a NAND3 Equalize LUT loading A LUT A drives PCRAM + buffer out1 PCRAM LUT drives LUT B + buffer out2 Propagation delay = t out2 t out1 out1 LUT B out2 t out1 t out2 t out1 t out2 t Slide 73

74 Output voltage (V) Pull-up Propagation Delay Measured pull-up delay ps Time (ns) out1 out2 Slide 74

75 Output voltage (V) Pull-down Propagation Delay Time (ns) Measured pull-down delay ps out1 out Slide 75

76 Conclusion Feasibility of using phase-change vias to reconfigure RF circuits demonstrated Need PC material with different characteristics compared to NVM RF VCO vehicle uses CMU PC process, foundry CMOS process and CMU 3-D integration flow Encouraging phase noise performance Preliminary cyclability tests conducted Other kinds of PC-via based circuits demonstrated Foundry CMOS+PC process Non-memory circuits demonstrated Slide 76

77 Backup Slide 77

78 Solder Bumping Cu Sn Plated Sn on 5 μm tall Cu stud Reflowed Solder Balls Slide 78

79 ρ (Ω-m) ρ (Ω-m) Material Comparison Ge x Sb 1-x Ge 50 Te W 15sccm 300W 15sccm 500W 15sccm Temperature ( C) Simone Raoux et al., Phase transitions in Ge-Sb phase change materials, JAP, 105, (2009) Temperature ( C) S. K. Bahl and K. L. Chopra, Amorphous vs Crystalline GeTe films, JAP 41, 2196 (1970) Ge 15 Sb 85 OFF ON GeTe OFF ON ρ (Ω-m) ρ (Ω-m) x10-6 Slide 79

80 SEM Cross-section of a Single PC Switch PC via Regular via PC via 1 µm PC (GeTe+TiW) PC (GeTe+TiW) M 2 (Cu) SiO 2 M 2 (Cu) SiO 2 M 2 (Cu) M 1 (Cu) Slide 80

81 CMOS Zoom In (after bonding and removal) CMOS inductors tin transfer from bonding process Slide 81

82 Bonded CMOS and PC Chips PC Chip (made at CMU) CMOS chip flipped and bonded This chip was not functional CMOS chip cracked on on side Slide 82

83 Clk (V) Clk (V) Out+ (V) Out+ (V) Transient Output Waveform Time (ms) Regenerate a 1 Reset Regenerate a Time (ms) Time (ms) Time (ms) Determines an output of 0 Determines an output of 1 Run 20 cycles and record outputs Regenerate a 1 Designate a 1 if 1 s > 0 s; designate a 0 otherwise Reset Regenerate a 0 Slide 83

84 Count Monte Carlo Simulation of Comparator Offset Voltage (Vos) The calibrated V OS,A < 89.4%, V OS,B < 75.4% of samples from 1000 sampling points Slide 84