Crossbar architecture for Non-Volatile Memories. Andrea Redaelli

Transcription

1 Crossbar architecture for Non-Volatile Memories Andrea Redaelli

2 Outline Why 3D approaches (literature review)? The crossbar concept The self-selected resistive cross bar array The diode selected array: the PCM example Other biasing schemes System issues Possible applications for cross-bar The cross-bar architecture (e. g., NiO storage) Conclusions Page 2

3 Outline Why 3D approaches (literature review)? The crossbar concept The self-selected resistive cross bar array The diode selected array: the PCM example Other biasing schemes System issues Possible applications for cross-bar The cross-bar architecture (e. g., NiO storage) Conclusions Page 3

4 Market trends $ $ $ $ $ $ $ $ EEPROM NOR NAND DRAM $ Non volatile Memory market is fast increasing market with large expected revenues. Scaling of conventional approaches are featuring fundamental limitations Page 4

5 Why 3D stacking? 3D stacking allows cost reduction without cell geometrical scaling Page 5

6 Crossbar early works: the OTP Simple scheme employing an anti-fuse as storage element. A diode required to select the storage element. S. Molleretal, Princeton Univ., Nature 2003 M. Johnson et al., Matrix Semicon., IEEE J. of Solid-State Circuits, 2003 S.B. Herner, Matrix Semicon., IEEE Electr. Dev. Lett., 2004 Polysilicon diodes process temperatures: 540 C-750 C Page 6

7 Crossbar for Oxide-Based RRAM I on ~ A/cm 2 I on /I off ~10 3 η=2 M-J Lee etal, Samsung, IEDM 2007 M-J Lee etal, Samsung, Adv. Funct. Mat Page 7

8 Latest results: Crossbar with PCM Y. Sasago et al., Hitachi, Symposium on VLSI Technology, 2009 Selection through a polysilicon diode PCM till created after diode fabrication Good diode driving current capability K. DerChanget al., Intel-Numonyx, IEDM, 2009 Selection through a threshold chalcogenide-based not rectifying element: OTS Sensing biasing above the OTS threshold but below the OUM one Programming above the OTS+OUM thresholds Page 8

9 Outline Why 3D approaches (literature review)? The crossbar concept The self-selected resistive cross bar array The diode selected array: the PCM example Other biasing schemes Feasibility issues Possible applications for cross-bar The cross-bar architecture (e. g., NiO storage) Conclusions Page 9

10 The memory array Memory cell Main array: storage Circuitry: read and write/erase operation Read current to the sense amplifier trough the column Page 10

11 Cross-point array (CPA) Top electrode Bottom electrode Selecting and storage layers Each cell is located between two metal lines. Very small cell size 4F 2 for layer If the right material is found only 2 mask steps are required, resulting in a very simple process. Usual processes employ more masks (3/4) Page 11

12 Cross section view Stacked memory layers 2 metals for each layer Cu Metals Top Storage Cu Metals Bottom W contacts Dielectrics Cu Metals for Circuitry Dielectric material cover the CMOS 2/3 metal levels to manage circuitry W contact to connect silicon with metals and circuitry metals with array metal CMOS on STD silicon Cells are fully integrated in the BEOL No silicon contamination issues Page 12

13 Array architecture N layers 1D/1R scheme Diode Storage element V 1 V d d V 0 V 1 V rows columns To ensure a reasonable yield, the maximum number of critical masks should be minimized (r P =r SLN ). Interconnection complexity exponentially rises with number of stacked layers (loss of array efficiency). Two stacked layers are considered feasible. Three-four layers are considered challenging Page 13

14 Advantages of the crossbar scheme Minimum device area can be achieved: 4F 2 Very simple process flow with reduced mask number No issues for silicon contamination Maximum array efficiency can be achieved: η=a array / (A array U A circuitry )=1 More memory device can be stacked in a 3D array, further reducing the effective cell size: 4/nF 2 Page 14

15 Outline Why 3D approaches (literature review)? The crossbar concept The self-selected resistive cross bar array The diode selected array: the PCM example Other biasing schemes System issues Possible applications for cross-bar The cross-bar architecture (e. g., NiO storage) Conclusions Page 15

16 Resistive cross-point V/2 readout scheme -V/2 V/2 GND GND The ideal following condition should be verified: (N-1) x I(V/2) << I(V) 0 V 0 V 0 V -V/2 0 V 0 V 0 V N rows Strongly non-linear characteristic needed!!! The practical condition is: (N-1) x I(V/2) < 0.1I(V) 0 V 0 V V/2 0 V0 V M columns Trade off between sensing and technology Page 16

17 Resistive cross-point programming scheme 0V 0V Vp/2 0V 0V 0 V 0 V 0 V -Vp/2 0 V 0 V 0 V N rows RESET threshold -Vp 0V SET threshold -Vp/2 Vp/2 Vp M columns Program/erase must be a threshold mechanism Page 17

18 Ideal Crossbar array Ion Ioff=0 I Vread/2 Vread Program region Vth1 Vth0 Iprog 0 V 0 V 0 V -Vp/2 0 V 0 V 0 V N rows Vp/2 Vp Assumptions: 1) Symmetric characteristic 0 V Vp/2 0 V0 V M columns 2) Vp 0 1 and 1 0 almost equal (bipolar switching) Sensed current Isense=I(V)+(N-1)I(V/2)=Ion+(N-1)x0 if 1 =Ioff+(N-1)x0 if 0 Program Vprog=Vp & Vdisturb=±Vp/2 V Page 18

19 Read crossbar array: an example I (µa) Sense current of n x n crossbar 360nA 30nA 30nA 270nA 240nA 210nA 180nA 150nA 120nA 90nA 60nA 30nA Ioff!= 0 I(on) I(of) x100 ON 50x50 ON 100x100 OFF 50x50 OFF 0nA 0.0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V 1.4V x10 ON 10x10 OFF E. Lortscher, J. W. Ciszek, J. Tour, H. Riel: Reversible and Controllable Switching of a Single-Molecule Junction, Small 2, No. 8-9, 973 (2006) (Volts) Simulation from Prof. Paolo Lugli, TUM, EU funded VERSATILE Project V Sensed current Isense=I(V)+(N-1)I(V/2)=Ion(V)+(N-1)/2xIon(V/2) if 1 =Ioff(V)+(N-1)/2xIon(V/2) if 0 Absolute window: W=Ion(V)-Ioff(V) but design margins not acceptable Page 19 19

20 Solution: the selecting element The storage element itself displays strongly non linear characteristics suitable to selection purpose nowadays no working storage materials 1D/1R scheme must be adopted. A selecting element is required: A rectifying element as a diode (A) A symmetric element (B) (A) (B) Current Current Voltage Voltage Page 20

21 1T/1R Proposed Alternatives Chalcogenide GST and other phase-change alloys AgGeSe, AgGeS, WO 3 and SiO 2 solid electrolyte Binary oxide Nb 2 O 5, Al 2 O 3, Ta 2 O 5, TiO 2, ZrO x, Cu x O and NiO M. Kozicki, EPCOS 2006 Oxides with perovskite structure SrZrO 3, doped- SrTiO 3, Pb(Zr x Ti 1-x )O 3 and Pr 0.7 Ca 0.3 MnO 3 Conductive organics Bengala Rose, AlQ 3 Ag, Cu-TCNQ A. Chen et al., IEDM Tech. Dig Page 21

22 Emerging memories swithing Memory Type Typical Material Electrode Materials Programming Voltage Emerging memories must be compliant with a rectifying or symmetric decoding scheme Resistive RAM (RRAM) Colossal Magneto- Resistive (CMR) material as Pr 0.7 Ca 0.3 MnO 3 (PCMO) Pt Same or opposite polarity Oxide Resistive RAM (OxRRAM) Transition Metal Oxides (NiO) Noble metals (as Pt) Same or opposite polarity Programmable Metallization Cell (PMC) Ag 33 Ge 20 Se 47, WO 3 Ag or Cu/Ni, Cu/W Opposite polarity Phase Change Memory (PCM) Ge 2 Sb 2 Te 5 TiN or TaN Same or opposite polarity Organic CuTCNQ, Bengala Rose Cu/Al Opposite polarity Page 22

23 Outline Why 3D approaches (literature review)? The crossbar concept The self-selected resistive cross bar array The diode selected array: the PCM example Other biasing schemes System issues Possible applications for cross-bar The cross-bar architecture (e. g., NiO storage) Conclusions Page 23

24 Resistive/PCM selection approaches MOSFET BJT/diode Diode BEOL Process Complexity No mask overhead for the selector Dedicated steps for the BJT integration Simpler process Cell Size Larger (~20-30F 2 ) Smaller (~5-8F 2 ) Smaller (~4F 2 /n) Memory Array Organization Conventional Innovative Breakthrough Application Embedded memory Stand alone, high density Stand alone, very high density Schematic Cell Structure Crosssection GND BL WL BL WL n+ p-substrate n+ STI p+ n+ n-well p-substrate Page 24

25 PCM Array Layout and Section Cell is 104nm x 104nm: µm 2 52nm x 52nm BJT selectors base contact shared by 4 Emitters effective cell area is µm 2 G. Servalli, IEDM 2009 Page 25

26 BJT selector array Dual crossed STI for BJT array definition 270nm STI for wordlines (BJT bases) 140nm STI for BJT emitters and base contact region thin CoSi 2 over BJT emitters junctions Page 26

27 BJT selector array Dual crossed STI for BJT array definition 270nm STI for wordlines (BJT bases) 140nm STI for BJT emitters and base contact region thin CoSi 2 over BJT emitters junctions p-implant n-implant emitters base emitters Bases (WLs) Common collector Page 27

28 x-wl equivalent electric circuit emitters base M2 WL M1 BL1 M1 BL2 M1 BL3 M1 BL4 n-array Page 28 p-collector common and grounded

29 x-bl equivalent electric circuit M2 WL1 M2 WL2 M2 WL3 M2 WL4 M2 WL5 M2 WL6 M2 WL7 M2 WL8 emitters Bases (WLs) M1 BL Common collector AA STI AA STI AA STI AA STI AA STI AA STI AA STI AA Page 29

30 PNP-BJT Transistor Emitter - BJT is not a field controlled transistor but is mainly current controlled. As a results, some current flowing from the base to ground could exist. Base - Properly biasing the base contact through the word line, the BJT can be used as a switching selector Collector -The transistor gain is an important parameter to define WL voltage drop contributing to read and program performance Page 30

31 Selection through PNP-BJT Storage Emitter BL - Collector is always grounded while the emitter and base are used for selection purposes. Base (WL) Collector - The emitter is connected to the BL through the PCM cell, the base is connected to the WL through the base contacts -We use the BJT almost as a diode but the BJT gain reduces voltage drops. Page 31

32 Array stand-by: the leaker row Leaker: 0V +Vdd +Vdd +Vdd +Vdd When the array is switched ON, ready for programming operation, all the BJTs of the matrix are reverse biased at high voltage, +Vdd with all the BLs let floating from decoders To manage the BLs voltage a row at the array edge (the leaker row) is 0 V The BLs voltage stabilizes at an intermediate voltage between 0 and +Vdd. What voltage? Page 32 FL FL FL FL FL V BL I EB (+V BL )=(N-1)xI EB (- Vdd-V BL ) V BL V TH of the emitter-base junction During stand-by there is consumption

33 Program biasing scheme: selected cell +Vdd 0V +Vdd +Vdd +Vdd When the array is programmed the leaker is switched off (WL leak. Vdd) When the array is ready for programming, the selected WL is grounded and works as a leaker (there is a consumption). The selected BL is thus about Vdd to program the cell. During stand-by and program, the array leakage could be severe, thus it must be minimized. How many junctions are leaking? Stand-by: Ileak=(N)x(N-1)I EB (VBL-Vdd) V BL V BL V BL V pulse <Vdd+V TH V BL Program: Ileak=(N-1)x(N-1)I EB (VBL-Vdd)+ +(N-1)xI EB (Vpulse-Vdd) Page 33

34 Selected device during programming Storage Emitter Base (WL = 0 V) BL V pulse - Programmed WL is biased to ground - BL of the selected cell is carried at Vpulse(I(Prog)) about 4 V - EB junction is polarized in direct biasing - Collector is grounded - In the BJT (diode) flows the direct current at I(V EB ))=I(Prog) V EB about 2 V Collector = 0 V Page 34

35 Standby/program biasing unselected cell BL V BL V TH +Vdd Storage 0V Emitter +Vdd +Vdd Base (WL +Vdd) V pulse V BL V BL V BL V BL +Vdd Two leakage: Collector 0 V I BE high contribution due to BTB tunneling I BC small contribution due to Impact ionization Page 35

36 Standby/program biasing unselected row/column +Vdd 0V +Vdd +Vdd Unselected cells along the selected columns and rows are biased at small voltages: - Row I(VBL) working as the leaker - Column I(Vpulse-Vdd) +Vdd V BL V BL VpulseV BL V BL Page 36

37 Standby/program biasing unselected row/column Unselected cells belonging from selected column Unselected cells belonging from selected row works as leaker Storage BL Vpulse Storage BL V BL Emitter Emitter Base (WL = Vdd) Base (WL = 0 V) Collector = 0 V Collector = 0 V Page 37

38 BJT selector characteristics Active current as large as 2V Emitter leakage lower than 1pA / even at high temperature p C 85 C Reverse current [A] 1p 100f 10f 30 C 85 C VBE [V] 1f VBE [V] Page 38

39 Isolation issues Each active area (local WL) must be electrically isolated from the other ones. Emitter P Emitter P STI Base WL N at 0V STI Base WL N at 4V STI BL cut npn-bjt par. Collector P at 0 V Each BE junction (belonging from different BLs) must be isolated from the adjacent ones Base n+ Base n Collector p Emitter P at 0 V Emitter P at 4 V Rot. STI Rot. STI Rot. STI WL cut pnp-bjt par. Page 39

40 Trench isolation Emitter P Base WL N at 0V Emitter P Base WL N at 4V BL cut npn-bjt par. Collector P at 0 V To manage WL to WL isolation we can play Moving up the BC junction (raised emitter or epitaxy) Increasing the trench deep (difficult for technology) Increasing the collector doping (but this increases the BC leakage..) Page 40

41 Shallow STI isolation Base n+ Emitter P at 0 V Emitter P at 4 V Rot. STI Rot. STI Rot. STI Base n Collector p WL cut pnp-bjt par. To manage BL to BL isolation we can play Taking the base-emitter junction as shallow as possible Increasing the rotated trench deep (Not easy for junction position) Increasing the base doping (but this increases the BE leakage..) Page 41

42 Outline Why 3D approaches (literature review)? The crossbar concept The self-selected resistive cross bar array The diode selected array: the PCM example Other biasing schemes System issues Possible applications for cross-bar The cross-bar architecture (e. g., NiO storage) Conclusions Page 42

43 Array contingency For the crossbar architecture a biasing scheme must be developed, considering Leakage during reading operation: when a cell must be read, the overall leakage of unselected cells along the same selected column must be at least one order of magnitude lower than the sensed current When the array is in the programming condition, the overall leakage of the array must be lower than programming current. If not, the array throughput is severely depressed. Different biasing schemes can be employed depending on the properties of the chosen storage element and the selecting device. Two extreme cases can be however identified: The standard rectifying scheme V/2 biasing scheme Page 43

44 Cross-point standard rectifying biasing Vread Vread Vread The following condition must hold for reading: (N-1) x I(V=0) << 0.1x I(Vread) Vread 0 V Vread Vread Vread N rows Always verified 0 V 0 V 0 V 0 V 0 V M columns Page 44

45 Cross-point standard rectifying biasing Vp Vp Vp The following condition must hold for reading: (N-1) x I(V=0) << 0.1x I(Vread) Vp 0 V Vp Vp N rows Always verified 0 V 0 V 0 V 0 V 0 V Vp The following condition must hold for programming: (N 2-2N+1) x I(-(Vp)) << I(Vp) M columns Rectifying characteristics needed!!! Page 45

46 Cross-point V/2 biasing Vread Vread/2 Vread/2 Vread/2 0 V Vread/2 Vread/2 Vread/2 N rows The following condition must hold for reading: (N-1) x I(+Vread/2) << 0.1xI(Vread)) Strongly non-linear characteristic needed!!! Vread/2 Vread/2 Vread/2 Vread/2 Vread/2 M columns Page 46

47 Cross-point V/2 biasing Vp Vp/2 Vp/2 Vp/2 0 V Vp/2 N rows The following condition must hold for reading: (N-1) x I(+Vread/2) << 0.1xI(Vread) Strongly non-linear characteristic needed!!! Vp/2 Vp/2 Vp/2 Vp/2 Vp/2 Vp/2 Vp/2 The following condition must hold for programming: (N 2-2N+1) x I(0) << I(Vp) M columns (N-1) x I(+Vp/2) << 0.1x I(Vp) During the programming in N-1 cells along the selected column and in N-1 cells along the selected rows flow a current equal to I(+Vp/2) that can cause a program disturb Page 47

48 Biasing scheme following the storage requirements V 0.66V 0.66V 0.66V 0 V 0.66V N rows The following condition must hold for reading: (N-1) x I(+0.33Vread) << I(Vread) The leakage is depressed from I(+0.5Vread) to I(+0.33Vread) 0.33V 0.33V 0.33V 0.33V 0.33V M columns 0.66V 0.66V The following condition must hold for programming: (N 2-2N+1) x I(-0.33Vp) << I(Vp) (N-1) x I(+0.33Vp) << 0.1x I(Vp) By playing on the bias voltage is possible to better match the storage element characteristics. A compromise between read and program is always to be found Page 48

49 Simplified equivalent circuit n x V Non-accessed OFF Accessed junction Non-accessed ON unaccessed = V / 2 word dd GND curent density (A/cm 2 ) V sens V Non-accessed OFF GND read = bit Vdd 2 n x Non-accessed ON Best 10 4 result of Versatile diode : Ag / ZnO I 10-1 on /I off ratio ~ voltage (V) - No issue during reading V Vp read = V / 2 word dd - Leakage issue during program Non-accessed OFF V Vp unaccessed bit = + Vdd 2 2 n Non-accessed ON Current [A] x V 0 V 0 V Read bit Read word Unaccessed bit Unaccessed word Vp 0 V 0 V Diode from EU VERSATILE Project Sel Sel Array size Vp Vp Vp 0 V Vp Vp Vp 4 10 Page 49

50 Outline Why 3D approaches (literature review)? The crossbar concept The self-selected resistive cross bar array The diode selected array: the PCM example Other biasing schemes System issues Possible applications for cross-bar The cross-bar architecture (e. g., NiO storage) Conclusions Page 50

51 Possible applications Multi-layer stacked memories could be interesting for High density applications (NAND-replacement): rewritable, high system embeddability, easy portability, low power consumption Consumable applications: one time programmable, high system embeddability, easy portability, low power consumption The high density/mass storage application market is continuously increasing due to the increase of multi-media portable systems Page 51

52 Specification for NAND replacement application Biasing scheme Vmax Only diode Vread Max current density [A/cm 2 ] I(Vdd)/ I (-Vdd) Tile: 1k x1k I (V) /I(V/2) Temperature Range Standard rectifying Scheme V/2 scheme Direct V Reverse 5-7 V Direct V Reverse Do not care V V 10 7 A/cm A/cm A/cm A/cm Do not care Do not care 10 4 From -40 C To 55 C Specification for the junction in the case on NAND replacement application. The storage element used for extracting the junction specification is the PCM. Page 52

53 Consumable applications Can consumable device also play a role in portable system fast growing market in future? Consumable Digital Media Tgt mkt: Use mdl: Channel: Avg. price: pc optional & non-pc mainstream store on card forever mass merchant, food & drug low absolute out of-pocket (3-5X cheaper) Videogame software storing Matrix semiconductor Consumable memory cards Page 53

54 Specification for consumable application Biasing scheme Vmax on diode Vread Max current density [A/cm2] I(Vdd)/ I (-Vdd) I (Vdd)/ I (Vdd/2) Temperature Range Standard rectifying Scheme V/2 scheme Direct +2 V Reverse -3.5 V Direct +2 V Reverse Do not care 1.5 V 1.5 V 10 3 A/cm A/cm A/cm A/cm Do not care Do not care 10 4 From -40 C To 55 C The storage element actually chosen as an anti-fuse is the NiO developed in the EMMA project that can be programmed with 1.5 V and 1000 A/cm2.. Alternatively Alumina was also considered. Latest result from Versatile and Emma project fulfill with these specifications! Page 54

55 ZnO results 10-1 Metal Binary oxide Metal Ti/Au ZnO Ag Storage element Schottky Diode current (A) Switch from ON to OFF state Switch from OFF to ON state EU funded Versatile and Emma projects voltage (V) Each cross point = selector + storage element Storage element : binary oxide (EMMA project) 4 steps of UV lithography Page 55

56 Application scenario Application scenario for stacked memory: NAND-replacement application if its cost is comparable to the cost of ML-NAND technology (this implies at least 2 stacked levels with a 1D1R scheme and it looks feasible) Consumable application if its cost is at least 5 times lower than the NAND one (this implies a large number of levels, e. g. 5. High risk due to high number of critical masks that can impact the yield) Page 56

57 Outline Why 3D approaches (literature review)? The crossbar concept The self-selected resistive cross bar array The diode selected array: the PCM example Other biasing schemes System issues Possible applications for cross-bar The cross-bar architecture (e. g., NiO storage) Conclusions Page 57

58 Design flow Single layer view: Programming current of memory element, I prog I prog must be delivered by decoders W of MOS overall dec. area tile size I prog defines the maximum direct voltage required taking into account the voltage drop on the selector and parasitics (WLs BLs additional drops) Reverse voltage to deselect rows V unsel should be closed to maximum direct voltage Assuming a rectifying or V/2 scheme, the leakage determine the overall array consumption System view: Tile size at least equal to decoder size Partitioning of tiles can help in managing the overall leakage Page 58

59 Selecting element performances DIODE Parameter Max density current before breakdown (direct ) Max Ion (+2V) / Ioff ratio (-2V) Threshold voltage ( 45 nm tech node) Max direct 45nm tech node Back end (best results) < 8-10 MA / cm 2 < 10 8 ~ 1-2 V < 300 ua Front end (typical) > 30 MA / cm 2 >10 11 ~ V > 600 ua Best result for leakage: EU Versatile project Best 10 4 result of Versatile diode : Ag / ZnO I 10-1 on /I off ratio ~ curent density (A/cm 2 ) voltage (V) Best result for direct current Page 59

60 NiO-based RRAM as storage Parameter Tech node (F) NiO forming voltage NiO reset current NiO reset voltage NiO set voltage NiO set/reset time n-mos driving current capability [1/ W] p-mos driving current capability [1/ W] Write throughput Mean value 45 nm < 4V 250 ua 2.5 V 3 V < 100 ns 500uA /um 200uA /um 1-10 [MB/s] Page 60

61 Array 45nm Silicon Area Programming current Array area Decoders area n Array sizing The cell programming current drives the decoders size The minimum tile size is dictated by space required to allocate decoders (array efficiency > 90%) Tile size define the parasitics, thus the required voltages and consumption. 4Mbit array seems a good starting point (to be verified): Array area = um 2 Decoder area = um 2 Page 61

62 Programming path voltages (parasitics) Process parameters: F = 45 nm (technology node) Cell size: 4F 2 = um2 Cu / bit 0.5 ohm/bit Cu / bit 0.5 ohm/bit C CELL ~ 0.05fF (negligible) Cu damascene process available today Programming path Storage (NiO ) Back end diode WL resistance (1kOhm) BL resistance (1kOhm) Maximum required voltage Voltage drop [V] (worst case) ~ A CMOS oxide Page 62

63 Rectifying scheme Vp Vunsel Vunsel Vunsel 0 V Vunsel N rows Vp = 5V Vunsel = 4.5V V (leaker) = 1V (~Vth diode) I DIODE (Vp)= 250uA Vleak Vleak Vleak Vleak Vunsel Vunsel Vleak Total array leakage: N columns I DIODE (Vleak-Vunsel) x (N-1) 2 << I PROG (<I PROG / 10) I DIODE (- 3.5V) < 6pA /bit I(Vp)/I(Vleak-Vunsel) > 4x10 7 Courtesy of Tortorelli, EU funded EMMA Project Page 63

64 V/3, 2/3V polarization scheme Vp Vp = 5V Vunsel = 3.3 V V BL = 1.7V I DIODE (Vp)= 250uA Pro and Cons: V BL V BL V BL N columns Leakage: I DIODO (V BL -Vunsel) x (N-1) 2 < I PROG /10 I DIODO (-1.7 V) < 6 pa /bit Disturb: I (Vp-Vunsel)< I disturb I (+1.7 V) Sensing: I (0.33xVread)x (N-1) < 0.1xI(Vread) I (0.33xVread) < 0.5 na Further consumption: I (+1.7V) x N < 0.1 x Iprog I (+1.7V) <20 na/bit Ratio: I(Vp)/I(-1.7 V)=4x10 7 ~ I(Vp)/I(-3.5 V)=2.5x10 5 V BL V BL Vunsel Vunsel Vunsel 0 V Vunsel Vunsel Vunsel N rows Page 64

65 Polarization schemes comparison Rectifying V/3, 2/3V Break down Reverse leakage (< 6pA/bit) Threshold voltage < ~ 1 na /bit No matter < - 1.7V ~ 3 pa/bit > 1.7 Direct current 250 2V 250 2V I(Vp)/I(-3.5 V) Direct slope (ideal : 60mV/dec) 4x10 7 > 60 mv / dec 2.5x10 5 ~ 60mV / dec Leakage issue: exacerbated by scaling because of periphery defects V TH > 1.8V needed other kind of switch selector!! Page 65

66 Conclusions The 3D approach is an effective way to reduce cost per bit of a NVM Self selected crossbar array are today not available. No resistive memory satisfy the requested non-linearity IV constraints. Strong efforts to find a suitable selector able to drive the current requested by the storage element till maintaining good leakage performances A careful optimization of array design is mandatory to exploit the diode and storage element characteristics The NAND replacement application (data storage) still remain the driving force of this activity Page 66