Prof. Paolo Colantonio a.a

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1 Prof. Paolo olantonio a.a

2 ipolar transistors are one of the main building blocks in electronic systems They are used in both analogue and digital circuits They incorporate two pn junctions and are sometimes known as bipolar junction transistors or JTs Here will refer to them simply as bipolar transistors onstruction Two polarities: npn pnp Prof. Paolo olantonio 2 23

3 While control in a FET is due to an electric field, control in a bipolar transistor is generally considered to be due to an electric current urrent into one terminal determines the current between two others ipolar transistors are 3 terminal devices collector (c) base (b) emitter (e) The base is the control input Diagram illustrates the notation used for labelling voltages and currents Prof. Paolo olantonio 3 23

4 Realization by growth The device is growth by strengthening a semiconductor. During the operation different doping materials (acceptor or donor) are added to realize the p orn regions. Realization by alloy On the two faces of a semiconductor (e.g. n Ge) are placed two globe of doping material (e.g. Indium) which melt in the semiconductor when the temperature is increased. During the cooling the regions where the Indium was melt becomes p type Planar realization In the semiconductor substrate, by using photolithographic windows, a doping material is diffused to realize the base and the emitter. The external contacts are realized by metal deposition Prof. Paolo olantonio 4 23

5 Relationship between the collector and the base currents in a bipolar transistor characteristic is approximately linear magnitude of collector current is generally many times that of the base current the device provides current gain We will consider npn transistors pnp devices are similar but with different polarities of voltage and currents When using npn transistors collector is normally more positive than the emitter V E might be a few volts device resembles two back to back diodes but has very different characteristics with the base open circuitnegligible currentflowsfromthe collector to the emitter Prof. Paolo olantonio 5 23

6 onsider what happens when a positive voltage is applied to the base (with respect to the emitter) This forward biases the base emitter junction The base region is lightly doped and very thin ecause it is lightly doped, the current produced is mainly electrons flowing from the emitter to the base ecause the base region is thin, while the base collector is reverse biased, most of the electrons entering the base get swept across the base collector junction into the collector This produces a collector current that is much larger than the base current this gives current amplification Prof. Paolo olantonio 6 23

7 Assuming the current and voltage references as reported in the figure, the current in the collector can be expressed as: I I I 0 E I E v E I I - v E v - - eing the large signal current amplification factor I I0 I E I 0 the reverse bias current of the ollector ase junction In general, assuming the base emitter junction forward biased, the collector current can be expressed as: I IE IO 1e V V T Prof. Paolo olantonio 7 23

8 I I I 0 E y using the Kirchhoff current law, it is possible to write: I I IE 0 I E v E I I - v E v - - ombining the two relationships, it is possible to relate the output current I to the controlling current I : eing I I I I I E0 I I 1 I 1 0 E0 0 I 1 I I E0 The reverse saturation current when the base is open (I =0) The large signal current amplification gain Prof. Paolo olantonio 8 23

9 Thus the behaviour can be described by the current gain, (h fe ) or by the transconductance, g m of the device (accounting for the diode behavior of the baseemitter junction) I I h I E0 fe Prof. Paolo olantonio 9 23

10 The circuit shows a simple amplifier R is used to bias the transistor by injecting an appropriate base current is a coupling capacitor and is used to couple the A signal while preventing external circuits from affecting the bias This is an A coupled amplifier Prof. Paolo olantonio 10 23

11 Transistors can be used in a number of configurations Most common is as shown Emitter terminal is common to input and output circuits This is a common emitter (E) configuration We will look at the characteristics of the device in this configuration Prof. Paolo olantonio 11 23

12 The input takes the form of a forward biased pn junction The input characteristics are therefore similar to those of a semiconductor diode I[ A] V [V] E V [V] E Prof. Paolo olantonio 12 23

13 The output characteristics can be divided in three regions Region near to the origin is the saturation region, which is normally avoided in linear circuits Slope of lines in the active region represents the output resistance Saturation region I[mA] Active region I E0 I =700 A 600A 500A 400A 300A 200 A 100A 0 reakdown region V [V] E Prof. Paolo olantonio 13 23

14 an be described by either the current gain or by the transconductance D current gain h FE or dc is given by A current gain h fe is given by h dc fe h I I FE V E I I const 1 0 I I I I I I I Assuming h FE h h I I h h FE fe 0 fe FE I I 0 0 I I I I I I I 0 I I h h fe FE h fe 1 h FE FE I0 I I h 1 I Prof. Paolo olantonio 14 23

15 +V I c [ma] R L I V E V R L 20 r sat 200μA 160μA 120μA 80μA r sat nω V E E I E 10 40μA 20μA V RL I VE V 0.5 V ce [v] In saturation both emitter and collector junctions are forward biased Increasing the bias current, the collector current is practically unaffected I sat, V R L, 0.2V Prof. Paolo olantonio V E sat

16 +V I c [ma] R L I V R L 200μA 160μA 120μA V E 20 80μA V E E I E 10 40μA 20μA V RL I VE V 0.5 V ce [v] In the active region emitter base junction is forward biased collector base junction is reverse biased I I h FE VE V RL I Prof. Paolo olantonio 16 23

17 The interdicted region is defined as the region for which I E =0 I I I I 0 E 0 Saturation region +V I[mA] Active region V 1 R 1 V E R L I E = I E0 I =700 A 600A 500A 400A 300A 200 A 100A 0 reakdown region V [V] E In order to have I E =0, it is required a small positive voltage V E (0.1V for Ge, 0 for Si) Prof. Paolo olantonio 17 23

18 The phototransistor is quite similar to the photodiode I Radiation I n J IL> V E n J E E V E Usually it is used in E configuration with open base (I =0) 1 I I I O The incident radiation increase the saturation reverse current I O +I L There is an advantage with respect to the photodiode, due to the multiplying factor (1+>>1) If the base is not open 1 I I I I O L Prof. Paolo olantonio 18 23

19 The analysis of a circuit containing a JT typically requires to study two mixed regime, due to the presence of both D and A signals Assuming a linear behavior (i.e. small signal), we can adopt the superposition principle It is convenient to look at its D (or quiescent) behaviour separately from its A (or small signal) behaviour D Analysis Only D sources (I or V) are considered It is adopted to determine the quiescent (device) bias point R L V i A Analysis Only A sources (I or V) are considered It is adopted to determine the variation of the electrical parameters (I and V) in the neighborhood of the operating point (i.e. Taylor approximation) i v I R 1 + v E - v E Prof. Paolo olantonio 19 23

20 Applying the Kirchhoff voltage law at the input and output mesh V vi ir ve R L i V i RL ve i R I i R V v V v V I I E E I i R V v L E E v I + v E - v E Thus separating the D from the A components, it follows D A V I R V I E V I R V L E v i R v i b be 0 icr L vce Prof. Paolo olantonio 20 23

21 onsider the following circuit R V R 2 1 and 2 are two D blocking capacitance R L is the loading impedance I 1 I npn R L E I E V i D analysis The capacitances are considered OPEN circuits A analysis The capacitances are considered SHORT circuits Prof. Paolo olantonio 21 23

22 V Applying the Kirchhoff voltage law at the input mesh R V R I VE R I Applying the Kirchhoff voltage law at the output mesh I npn V R I VE E I E I[mA] Static load line V / R I[ A] V / R I Q I Q Q I Q V EQ V V [V] E 0 V EQ V V [V] E Prof. Paolo olantonio 22 23

23 The D block capacitance are assumed short circuit The D bias V DD is not varying thus it is equivalent (A) as a virtual GND I I npn v R // R i ce L c V i R E I E R R L v be v i I[mA] Dynamic load line Static load line V / R I[ A] i b V / R i c R// R L I Q t I Q Q t V EQ V V [V] E 0 V EQ V V [V] E v be v ce t t Prof. Paolo olantonio 23 23

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