Mayank Chakraverty and Harish M Kittur. VIT University, Vellore, India,

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1 International Journal of Micro and Nano Systems, 2(1), 2011, pp. 1-6 FIRST PRINCIPLE SIMULATIONS OF FE/MGO/FE MAGNETIC TUNNEL JUNCTIONS FOR APPLICATIONS IN MAGNETORESISTIVE RANDOM ACCESS MEMORY BASED CELL PHONE ARCHITECTURES Mayank Chakraverty and Harish M Kittur VIT University, Vellore, India, nanomayank@yahoo.com, kittur@vit.ac.in Abstract: Fe/MgO/Fe magnetic tunnel junctions (MTJs) have been reported to have very high tunnel magnetoresistance (TMR) ratios. In this work, we present the results of First Principle simulations of Fe/ MgO/Fe MTJs with LSDA as the exchange correlation. The I-V characteristics in the antiparallel magnetization state exhibit strong features. The bias dependence of the TMR ratio shows nearly 100% TMR ratios for bias voltages up to 1.5 Volts. The MgO thickness dependence of the tunnel resistance shows the expected exponential increase in the tunnel resistance. The write energy per bit and power consumption have been computed for a bias voltage of 0.5 Volts. The Fe/MgO/Fe MTJs are the most widely used MTJs, integrated with NMOS transistors, in the form of MTJ based Magnetoresistive Random Access Memory (MRAM) which is an advanced memory technology operating at the nano scale. MRAMs are spintronic devices. Keywords: First Principle, LSDA, Fe/MgO/Fe, MTJ, TMR I. INTRODUCTION A. Magnetic Tunnel Junction (MTJ) An MTJ is basically comprised of two thin films of ferromagnetic (FM) materials like Fe, Ni or Co, with a very thin layer of insulator (MgO, Al 2 O 3, HfO 2 etc.) sandwiched in between. The insulating layer is so thin that electrons can tunnel through the barrier if a bias voltage is applied between the two metal electrodes. In MTJs, the tunneling current depends on the relative orientation of magnetizations of the two ferromagnetic layers, which can be changed by an applied magnetic field. The resistance offered to the flow of current through the ferromagnetic layers on account of the relative orientation of magnetizations of the two magnetic layers is called Tunnel Magnetoresistance (TMR). In TMR based MTJs, the magnetization of one of the ferromagnetic layer is fixed by using an anti ferromagnetic layer beneath the FM layer for which the magnetization is to be fixed. The magnetization of the other FM layer is free to flip depending upon the layer s switching threshold, hence called free layer [1]. In this paper, Fe/MgO/Fe MTJ has been selected for simulation on account of several factors like highly crystalline structure of Fe, remarkable adhesion of Fe and MgO thin films which is not common among other MTJs. Fe/MgO/Fe MTJs are also reported to have very high TMR ratios [2, 3]. B. Use of MTJs in MRAMs An array of FM/Insulator/FM tunnel junctions can be integrated with conventional Si based electronics technology to obtain the functionality of Random Access Memories (RAMs). Such RAMs based on TMR junctions are called Magnetoresistive RAMs (MRAMs) and have great potential applications because of the non volatility of the magnetizations of the two FM layers. Besides, the tunnel current does not change the relative magnetization of the two FM layers which means that the readout from such MRAMs is non destructive. Figure 1: Schematic of an MTJ in Parallel and Anti Parallel State Depicting the Logic States [4]

2 2 International Journal of Micro and Nano Systems The MTJs exhibit very good data retention property. If the magnetizations of the two FM layers are parallel, a low resistance path is said to exist through the MTJ thereby writing bit 0 and when the magnetizations of the two FM layers are anti parallel, a high resistance path is said to exist and correspondingly, bit 1 is said to have been written, as depicted in Figure 1. Though MTJs can store binary data, it has to be integrated with a sensing device to accomplish the reading of the stored binary data. This gives rise to an MTJ based Magnetoresistive Random Access Memory (MRAM) cell which consists of an NMOS field effect transistor with the TMR device on top of it. The orientation of magnetization of the FM layers takes place in different ways based upon the type of MRAM cell being investigated. However, the magnetization of the bottom FM layer in an MTJ is pinned in all types of MRAMs. Therefore, the magnetization of only the top FM layer needs to be flipped in either direction to accomplish the write operation. In MFW (Magnetic Field Write) MRAM cells, the magnetization of the free layer gets flipped as a result of the magnetic field generated when a current is passed through the bit line and the write word line aligned at right angles to each other, thereby storing data. Whereas, in case of Spin Injection MRAM cells, the current is made to pass through the MTJ directly causing spin polarized transport based upon the reversal of magnetization in the free layer. When compared to MFW MRAM cells, Spin Injection MRAM cells have been proved to consume least power during write operation, they are far more scalable than other RAM technologies, they have reduced memory cell area and simpler memory cell structure, there is no limitation on the number of write cycles and they offer extremely small read/write /erase times [6]. MRAMs have the potential for very wide applications in the field of communication devices, especially cell phones and other handhelds. This Figure 2: Schematic of an MTJ based MRAM Cell [5] paper exploits the potential of Fe/MgO/Fe MTJ in terms of size, power consumption, write energy etc. to be used in MRAMs for mobile devices like cell phones. A memory array consists of not only a single cell but an array of cells connected to bit lines and digit lines. The MRAM cell of Figure 2 can be implemented in the form of a memory array as shown in figure 3. Such an array is called a crosspoint array as the bit lines and digit lines cross each other at right angles and the point at which the lines cross forms a single MRAM cell with a TMR device at each cross point. Each TMR device has a sensing transistor connected to it to accomplish the read operation. To make a high-density memory, the MRAM cell shown in Figure 2 is arranged in a matrix with each write line spanning hundreds or thousands of bits, as shown in Figure 3. Figure 3: Cross Point Architecture with an MTJ at each Cross Point of Bit Line and Word Line [7] II. NEED FOR MTJ BASED MRAMS IN CELL PHONE ARCHITECTURES The memory technologies used for permanent data storage in cell phones today are the flash memories which are essentially EEPROM. It is also called floating gate memory [8]. Each cell of a flash memory consists of a N-MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The Figure 4 shows the structure of NAND flash cell. The black lines represent current paths with or without wires. Data is written into such cells either by Fowler- Nordheim (FN) Tunneling or by Hot Carrier Injection where as erasure is done by FN Tunneling only. Though flash memories save data when power is off, saving data is slow and uses a lot of power. Although flash and MRAM are very similar in power requirements while reading, flash is rewritten using a large pulse of voltage (about 10V) that is stored up over time in a charge pump, which is both power-hungry and time consuming.

3 First Principle Simulations of Fe/MgO/Fe Magnetic Tunnel Junctions for Applications in Magnetoresistive... 3 Figure 5: Fe/MgO/Fe MTJ with Left and Right Electrodes Figure 4: Flash Memory Cell [9] Additionally, the current pulse physically degrades the flash cells, which means flash can only be written to some fixed number of times before it must be replaced. Therefore, the need for a memory technology is felt that can effectively overcome the short comings encountered in flash memory technology. MRAM stands as a powerful contender for replacing flash memories in cell phones. In addition to overcoming the limitations of flash memories, MRAMs offer something close to the speed of SRAM, with a density approaching that of single-transistor DRAM and the ability to store information when power is removed, like flash memory or EEPROM. Memories based on MRAM have been seen to be in a race to develop a universal memory that could replace SRAM, DRAM and flash in many applications. between the first and second surface layer is ú and the distance from the surface layer to the oxygen layer of the central region is 2.2 Å. In order to simulate the structure, a bias voltage starting from 0.2V to 2.4V through 0.6V, 1V, 1.5V, 2V and 2.2V have been applied to the right electrode. The calculator used for the simulation is ATK-DFT (Device) with electron temperature of 300K and exchange correlation as LSDA (Local Spin Density Approximation) because the current flow is essentially due to spin polarized transport through the MTJ. The simulations are performed separately for parallel and antiparallel magnetizations of the two FM layers and the I-V curves obtained in the two cases are shown in Figure 6. In Figure 6(a), the I-V plot does not exhibit any strong feature as such and the plot is more or less a linear one where the tunnel current is directly proportional to the bias voltage applied. As it is clear from the Figure 6(b), the tunnel current is extremely low (almost approaching 0 nano Amperes) in the bias voltage III. I-V CHARACTERISTICS OF FE/MGO/FE MTJ The Fe/MgO/Fe MTJ is the most widely used MTJ exhibiting a very high value of TMR, though Ni/ Al 2 O 3 /Ni MTJs are also quite promising with regards to the value of TMR they exhibit. In this paper, we have built and simulated a Fe/MgO/Fe MTJ through first principle band structure calculations. The configuration is a BCC crystal oriented along the (100) direction. For reducing the complexity of simulation and keeping the time constraint in mind, we have built a set up of 48 atoms that constitute the Fe/MgO/Fe MTJ, where there are 24 Fe atoms, 12 Mg atoms and 12 oxygen atoms. The device configuration along with the left and right electrodes is shown in Figure 3. In the MTJ shown above, the electrodes have a lattice constant of Å, the insulating barrier has a layer separation of Å with a total of 6 atomic layers, the number of layers in the (100) direction in each electrode is 2 with a total of 4 layers making up the two electrodes, lattice distance Figure 6: I-V Curves for (a) Parallel and (b) Antiparallel Magnetizations of Fe/MgO/Fe MTJ

4 4 International Journal of Micro and Nano Systems range of -1 Volts to 1 Volts. This indicates an extremely high tunnel resistance in the specified bias voltage range. It can be seen in Figure 6(b) that in the bias voltage range of 1 Volts Volts, the tunnel current makes a negative excursion. This needs to be explained or clarified. The Figure 7 shows the plot of di/dv-v (tunnel conductance bias voltage) for the simulated Fe/MgO/Fe MTJ in the parallel and anti parallel magnetization states respectively. In Figure 7 (a), the value of tunnel conductance is high in the bias voltage range of -1 Volts to 1 Volts. This behavior can be explained on the basis of availability of empty electronic states in the right electrode of the MTJ that causes the tunneling of electrons from the left to the right electrode thereby leading to a high tunnel conductance in the voltage range of -1 Volts to 1 Volts. In the Figure 7(b), the value of tunnel conductance revolves around 0 ns in the bias voltage range of -1 Volts to 1 Volts. This can either be due to the unavailability of electronic states in the right electrode or even due to the availability of only filled electronic states in the right electrode of the structure. As a result, the tunneling rate of electrons across the insulating barrier goes down and a very high tunnel resistance is exhibited in the specified voltage range. A very interesting feature observed in the tunnel current-bias voltage plot as well as in the tunnel conductance-bias voltage plot obtained in the anti parallel magnetization state is the occurrence of negative resistance regions. The negative resistance is not seen in the plots obtained for parallel magnetization state. This property of exhibiting negative resistance by Fe/MgO/Fe MTJs, especially in the anti parallel magnetization state, can prove it to be a powerful contender for microwave generation and related applications. From the above simulations, the power consumption and the work done/ energy dissipated in storing a bit or reading a stored bit can be estimated. For a bias voltage of 0.5 Volts, the tunnel current through the MTJ is nano Amps in the parallel magnetization state while it is nano Amps in the anti parallel magnetization state. Correspondingly, the power consumption in the parallel state is Watts and the write energy per bit is femto Joules, which is far lesser than the write energy witnessed in flash memories [10], [11]. In the anti parallel magnetization state, the power consumption per cell has been estimated to be pico Watts and the write energy per bit is Joules. These values clearly exhibit the potential advantage of MTJ based MRAMs in terms of power consumption in cell phones as against to flash memories. IV. TMR STUDIES OF FE/MGO/FE MTJ The I-V characteristics of Figure 6 gives the values of tunneling current in nano Amperes for each of the input voltages applied. Using these data, the resistance at each point can be computed and hence the TMR can be computed for each input voltage applied using equation 1.Tunnel magnetoresistance (TMR) is the change in the tunnel resistance with the change in the relative magnetizations of two ferromagnetic (FM) films separated by a thin insulating barrier layer. The tunnel conductance is a maximum when the two ferromagnetic layers are magnetized parallel to each other and a minimum when the magnetizations of the two layers are antiparallel to each other. In order to quantify the percentage change in the junction resistance, one defines a tunnel magnetoresistance ratio TMR in terms of the junction resistances in the parallel and the anti-parallel magnetized states R P and R AP respectively, where Figure 7: di/dv-v Curves for (a) Parallel and (b) Anti Parallel Magnetization States R RAP RP TMR = 100% = 100% (1) R R AP AP

5 First Principle Simulations of Fe/MgO/Fe Magnetic Tunnel Junctions for Applications in Magnetoresistive... 5 Using (1), the TMR is computed for each of the input voltages applied and they have been plotted against the bias voltages as shown in Figure 8. It can be observed from the plot that considerably high TMR values have been reported with the highest value going up to % for bias voltage of 0.2 Volts. The tunnel magnetoresistance ratio can also be computed alternatively using the equation (2) R RAP RP TMR = 100% = 100% (2) R R P in which the difference between the anti parallel and parallel resistances for different bias voltages is divided by the parallel resistance unlike equation (1). Using this equation, the TMR ratios for different bias voltages have been computed and they have been plotted against the bias voltages as shown in Figure 9. AP As it is clear from the figure 9, the TMR ratios are extremely high when computed using equation (2). V. BEHAVIOR OF MAGNETORESISTANCE VALUES FOR DIFFERENT INSULATOR THICKNESSES In this paper, we have built a Fe/MgO/Fe MTJ and for a fixed bias voltage of 0.5 Volts, we have obtained the resistance values in both parallel and anti parallel states respectively, by varying the thickness of the insulating layer of MgO from 4 atomic layers to 10 atomic layers, and we have plotted the resistance in the two states against the insulator thicknesses to obtain curves as shown in Figure 10. The simulations have been carried out at electron temperature of 300K with LSDA as the exchange correlation in order to enable spin (a) (a) Figure 8: TMR v/s Bias Voltage for Fe/MgO/Fe MTJ using (1) (b) (b) Figure 9: TMR v/s Bias Voltage for Fe/MgO/Fe MTJ using (2) Figure 10: Plot of (a) Parallel & (b) Anti Parallel Resistance v/s Insulator Thickness in Fe/MgO/Fe MTJ

6 6 International Journal of Micro and Nano Systems polarized transport through the MTJ. As expected, the resistances in the parallel and anti parallel states increase exponentially as the thickness of the insulating barrier is gradually increased. That is, the rate of tunneling of electrons through the barrier from one electrode of the MTJ to the other comes down as the thickness of the insulator increases. VI. CONCLUSION This work confirms the large, nearly 100% TMR ratios in Fe/MgO/Fe MTJs predicted and reported by others before. The bias dependence of the I-V curves in the antiparallel state shows strong features. To our knowledge, such a strong bias dependence of the tunnel current in the anti parallel magnetization state has not been reported earlier. The write energy per bit has been found to be very less than that for both NOR and NAND flash memories. A plot of the TMR% versus the bias voltage reveals nearly 100% TMR ratios for bias voltages up to 1.5 Volts. Our simulations show that for a bias voltage of 2 Volts the TMR ratio becomes negative, meaning the R AP is less than R P. This anomalous TMR has not been reported earlier and needs to be further investigated. The oxide barrier thickness dependence of the tunnel current, both in the parallel and anti parallel magnetized state, shows the exponential increase in the tunnel resistance. We conclude, previous reports and our studies confirm the high TMR ratios of Fe/MgO/ Fe MTJs which can ideally be integrated with NMOS transistors to form MTJ based MRAM cells and these MTJ based MRAM cells in the form of memory array architecture can be used to replace flash memories that are being used in cell phones. VII. FUTURE WORK The future work involves designing a block diagram of MRAM based cell phone architecture, designing and simulating a circuit for MTJ based MRAM cell followed by an MRAM based memory array architecture and simulating the R/W circuitry of the array architecture to obtain the performance metrics and their comparison with those of flash memories thereby validating the replacement of flash memories in cell phone architectures with MTJ based MRAM cells. REFERENCES [1] Mark Johnson, Magnetoelectronics, 2001, Academic Press. [2] S. S. P. Parkin, C. Kaiser, A. Panchula, P. M. Rice, B. Hughes, M. Samant and S. H. Yang, Nat. Mater. 3, 862, (2004). [3] H. Ohmori, T. Hatori and S. Nakagawa, J. Appl. Phys. 103, 07A911, (2008). [4] Roberto Mantovan, Spin Polarized Advanced Materials for MagneticMemories, [5] Natali T. Del Conte, News from PC Magazine: Magnetic Memory Chips Hit the Market, [6] Motoyuki Oishi, Spin Injection MRAM Main Focus at MMM, Nikkei Electronics Asia March 2008 Analysis. [7] I.L. Prejbeanu, M. Kerekes, R.C. Sousa, H. Sibuet, O. Redon, B. Dieny, J.P. Nozieres, Thermally assisted MRAM, Submitted to: J. Phys. Condens. Matter, 2001, pp [8] R. Dean Adams, High Performance Memory Testing : Design Principles, Fault Modeling and Self- Test, 2003, Kluwer Academic Publishers, Boston/ Dordrecht / London. [9] Robert Hallock, The hows and whys of Solid State Disks (SSDs), September 2008, tech.icrontic.com/articles/how_ssds_work/ [10] Emerging Research Devices (ERD), International Technology Roadmap for Semiconductors 2009, Ed. [Online]. Available: [11] R. F. Freitas and W. W. Wilcke, Storage-class memory: The next storage system technology, IBM J. Res. Develop., Vol. 52, No. 4 5, pp , [12] Roberto Bez, Agostino Pirovano Non-volatile memory technologies: emerging concepts and new materials Materials Science in Semiconductor Processing 7, (2004), [13] S. Tehrani, B. Engel, J. M. Slaughter, E. Chen, M. DeHerrera, M. Durlam, P. Naji, R. Whig, J. Janesky, and J. Calder, Recent Developments in Magnetic Tunnel Junction MRAM, IEEE Transactions on Magnetics, Vol. 36, No. 5, 2000, pp [14] M. Durlam, P. Naji, M. DeHerrera, S. Tehrani, G. Kerszykowski, and K.Kyler, Nonvolatile RAM based on magnetic tunnel junction elements, in IEEE ISSCC Dig. of Tech. Papers, Feb. 2000, Vol. 43, p. 128.