Simulation of digital and analog/mixed signal circuits employing Tunnel-FETs
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1 Simulation of digital and analog/mixed signal circuits employing Tunnel-FETs P.Palestri, S.Strangio, F.Settino, F.Crupi*, D.Esseni, M.Lanuzza*, L.Selmi IUNET-University of Udine, * IUNET-University of Calabria Energy Efficient Tunnel FET Switches and Circuits imec 1
2 Aim of this presentation So far very few reports of fabricated circuits with TFETs (inverters, simple gates, half-sram, current mirrors). Often not with the best performing TFETs. Often w/o complementary technology. Experimental TFETs still suffer from SS degradation (traps) Our aim: to evaluate the performance of TFET circuits down to very low Vdd considering a virtual complementary TFET technology. Benchmarking against 10nm silicon FinFETs 2
3 OUTLINE Template devices and methodology Digital building blocks Analog/Mixed-signal building blocks Conclusions 3
4 III-V heterojunction complementary TFET virtual platform Template devices PTM for 10nm silicon finfets Baravelli et al., IEEE TED, v.61, n.2, p.473 (2014) Same footprint if TFETs are vertical 7+2.3*2= 11.6 nm 14 TFET 7+2.3*2= 11.6 nm 10 nm node 8+1.2*2= 10.4 nm Area occupation= nm 2 Area occupation= nm 2 4
5 ABS[Drain current] (A) Drain current (A) ABS[Drain current] (A) Drain current (A) DC charateristics 10u 1u 100n 10n 1n 100p 10p (a) P-type pff(-0.3v) pff(-0.1v) ptf(-0.3v) ptf(-0.1v) 1p V GS (V) 10u 1u 100n 10n 1n 100p 10p Ioff=2pA (b) N-type nff(0.3v) nff(0.1v) ntf(0.3v) ntf(0.1v) 1p V GS (V) TFETs: unipolar conduction threshold in Vds lower output conductance TFETs: more current than finfets at low voltages (SS<60mV/dec) ptfet current is ntfet/4 same I OFF same static power per area 100u 10u 1u 100n 10n 1n 100p 10p 1p 100f 10f 1f (a) P-type V GS = 0.1V V pff ptf V DS (V) 100u 10u 1u 100n 10n 1n 100p 10p 1p 100f 10f 1f (b) N-type V GS = 0.1V...0.4V nff ntf V DS (V) 5
6 Gate capacitance (af) Gate capacitance (af) C-V curves (a) P-type (b) N-type pff(0) ptf(0) pff(-0.3) ptf(-0.3) nff(0) ntf(0) nff(0.3) capacitance of ptfets higher ntf(0.3) than ntfets, due to higher DoS not so large differences between finfets and TFETs Vds dependence in TFETs V GS (V) V GS (V) a parasitic capacitance of 30aF present in the finfet model has been added to the TFETs too. 6
7 Drain Current (A) Drain Current ( A) 7nm Simulation methodology (a) NTFET (b) PTFET ptfet G ntfet S D D i G G i D D I DS i gd i gs Look-Up Tables: I DS (V DS,V GS ) C gd (V DS,V GS ) C gs (V DS,V GS ) Baravelli et al., IEEE TED, v.61, n.2, p.473 (2014) full-quantum NEGF simulations from IUNET-Bologna calibrated TCAD templates (a) V DS =0.4V Tn (TCAD) Tp (TCAD) Tn (F.Q.) Tp (F.Q.) V GS (V) Final Workshop 10 November (c) 2017 Energy Efficient 20Tunnel FET Switches and Circuits10 Tp G S TFET symbols (a) (b) see legend in (a) V GS =0.4V V DS (V) Tn (d) i S S i Gate = i gd + i gs i Drain = I DS i gd i Source = (I DS + i gs ) TFET Verilog-A model (b) look-up-tables in Verilog-A Cadence 7
8 OUTLINE Template devices and methodology Digital building blocks Analog/Mixed-signal building blocks Conclusions 8
9 V OUT Inv. Noise Margins Inverters: static characteristics (a) FinFET TFET (b) NML=VIL VOL, NMH=VOH VIH V IN higher gain for TFETs thanks to lower output conductance asymmetry between n- and p-tfet requires 5 NWs in parallel for the pull-up to improve static margins lower speed; better to stay 1:1 had have slightly reduced margins p- and n-finfets are symmetric NML-FinFET NMH-FinFET NML-TFET NMH-TFET 1/1 2/1 3/1 4/1 5/1 #P-type / #N-type 9
10 FO4 delays (s) Inverters: delay TFET-FO4 FinFET-FO4 L=>H Delay H=>L Delay L=>H Delay H=>L Delay V DD inverters with fan-out =4 1NW for pull-up 1NW for pull-down TFETs: asymmetry between L H and H L transitions due to different on-current of pull-up and pull-down TFETs faster than finfets for Vdd below approx. 400mV no layout parasitics, see presentation by IMEC 10
11 Propagation delay (s) Full-adders: delay standard, static CMOS, 28T full-adder FinFET TFET 10n 1n V DD TFET implementation faster than finfet implementation for Vdd lower than approx. 400mV 11
12 E Total (aj/cyc) E Total (aj/cyc) E Dynamic (aj/cyc) E Static (aj/cyc) E Total (aj/cyc) 32 bit ripple adder (a) Dynamic Energy FinFET TFET V DD TFETs vs finfets: (b) Static Energy V DD similar dynamic energy Full-adders: energy FinFET TFET lower static energy of TFETs at low Vdd TFETs advantageous at low Vdd and low switching activity (a) Switching activity = 100% FinFET V DD FinFET (b) Switching activity = 10% TFET V DD FinFET (c) Switching activity = 1% TFET V DD TFET 12
13 Static Noise Margins Static Noise Margins 6T static RAM cell (1) outward-faced cell Vdd=300mV (a) FinFETs (b) TFETs WRITE #PU= WRITE BL =V DD BL =0.5xV DD #PU= READ #PU= Number of ATs (#AT) 25 0 #PU= Number of ATs (#AT) TFETs with BL pre-charged at Vdd the cell cannot be read pre-charge at Vdd/2 and outward-faced configuration allow for reasonable static noise margins for a 6T cell 13
14 Write delay (s) Read delay (s) 6T static RAM cell (2) (a) Write FinFET TFET (b) Read FinFET TFET PD=1 PU=1 AT=1 (finfets), AT=3 (TFETs) BL parasitic capacitance =20 ff V DD V DD BL pre-charge at Vdd/2 TEFTs faster than finfets for Vdd below 400mV 14
15 Fabricated half-sram (Juelich+Udine) Schematic BL and WL for AT inward I-V of the devices (Si TFET nanowires) BL and WL for AT outward Layout inverter with independent gates to mimic WF adjustment WF alignment needed for n- and p-tfets in the inverter due to variability, access transitor differs from the ntfet in the inverter [V.Luong et al, ESSDERC 2017, p.42 15
16 Fabricated half-sram (Juelich+Udine) different high and low voltages for each TFET TFET devices V low V high (M1) n-tfet, V g,n = 0.5V 1.3V (M2) p-tfet, V in = V g,p = 0V 0.8V (M3) n-tfet, WL = 1V 1.8V measured noise margins BLs at V DD /2 needed 16
17 Energy Delay Product (Js) Energy Delay Product (Js) Energy D Energy D Level shifters V DDL (c) Lanuzza FinFET TFET Mixed V DDL (c) (d) Kim FinFET TFET Mixed V DDH =750mV topology from [M. Lanuzza, et al, IEEE T-CAS II, v. 64, p. 61, 2017] V DDL V DDL hybrid TFET/finFET topology advantageous for high V DDH /V DDL ratio TFETs for the low Vdd part, finfets for the high Vdd part 17
18 OUTLINE Template devices and methodology Digital building blocks Analog/Mixed-signal building blocks Conclusions 18
19 g m /I D (S/A) r o ( ) Small-signal performance (n-type) f T (Hz) A V = g m r o (a) 1 1p 10p 100p 1n 10n 100n 1u 10u 10 Drain current (A) (c) nfinfet ntfet nfinfet ntfet 1 1p 10p 100p 1n 10n 100n 1u 10u Drain current (A) 1T 100G 10G 1G 100M 10M 1M (b) 100k 1p 10p 100p 1n 10n 100n 1u 10u 1T 100G 10G 1G 100M Drain current (A) (d) nfinfet ntfet 10M nfinfet ntfet 1M 1p 10p 100p 1n 10n 100n 1u Drain current (A) TFETs vs finfets: higher efficiency g m /I D at low current higher gain at mellow currents due to higher output resistance slightly higher f T at low-currents V DS = 0.3V 19
20 g m /I D (S/A) r o ( ) Small-signal performance (p-type) 1000 (a) pfinfet ptfet 1T 100G (b) pfinfet ptfet G 1G A V = g m r o f T (Hz) p 10p 100p 1n 10n 100n 1u 10u 10 ABS[Drain current] (A) (c) pfinfet ptfet 1 1p 10p 100p 1n 10n 100n 1u 10u ABS[Drain current] (A) 100M 10M 1M 100k 1p 10p 100p 1n 10n 100n 1u 10u 1T 100G 10G 1G 100M 10M ABS[Drain current] (A) (d) pfinfet ptfet 1M 1p 10p 100p 1n 10n 100n 1u ABS[Drain current] (A) similar trends as for n-type devices lower on-current results in lower peak f T V DS = 0.3V 20
![Operation amplifier TFET design FinFET design Simple Simple Telescopic cascode Folded cascode DC gain [db] 33 16 36 34 FOMGBW* [MHz pf/µa] 6.3 2.2 2.3 1.2 IDD [na] 7.9 22.7 21.7 41.](/docs-images/88/116061999/images/21-0.jpg "7 * V DD = 500 mv, GBW = 50 MHz, C L = 1fF minimum size designs simple topology with TFETs has same performance as folded cascode with finfets at lower power simple telescopic cascode folded")
21 Operation amplifier TFET design FinFET design Simple Simple Telescopic cascode Folded cascode DC gain [db] FOMGBW* [MHz pf/µa] IDD [na] * V DD = 500 mv, GBW = 50 MHz, C L = 1fF minimum size designs simple topology with TFETs has same performance as folded cascode with finfets at lower power simple telescopic cascode folded cascode 21
22 Energy per op. (aj/op) Comparators V DD values ranging from 100 mv to 600 mv (step 10 mv) FinFET (conventional) TFET (conventional) FinFET (double tail) TFET (double tail) conventional double-tail Delay (s) range where TFET comparators are more energy efficient than finfet ones no advantages in going to double-tail architecture 22
23 OUTLINE Template devices and methodology Digital building blocks Analog/Mixed-signal building blocks Conclusions 23
24 Conclusions (1) many digital building blocks show advantages of TFETs over finfets for Vdd below approx. 400mV promising analog performance due to higher g m /I d and higher R out of TFETs analysis based on idealized devices with no layout parasitics due to the lower Ion, it is mandatory to have SS<60mV/dec to have advantages of TFETs over MOSFETs the pros (i.e. low SS and high R OUT ) and cons (i.e. ambipolarity, unidirectionality, p- versus n-type asymmetry, large C GD ) of TFETs with respect to MOSFETs can be balanced at best by adopting new circuit topologies; while research on TFETs focuses mostly on switches for digital circuits, TFETs exhibit potential interesting advantages also for analog / mixed-signal applications; 24
25 Conclusions (2) the introduction of TFET in mainstream CMOS technologies will likely be limited to electronic systems operating at extremely reduced voltage (lower than 400 mv) preferentially by adopting an hybrid TFET/MOSFET implementation, which takes advantage of both transistor options. At such small voltages (time dependent) variability may end up being the most stringent requirement dictating the application window of such technology 25
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