DESIGN AND SIMULATION OF A TEMPERATURE-INSENSITIVE RAIL-TO-RAIL COMPARATOR FOR ANALOG-TO-DIGITAL CONVERTER APPLICATION. A Thesis.

Transcription

1 DESIGN AND SIMULATION OF A TEMPERATURE-INSENSITIVE RAIL-TO-RAIL COMPARATOR FOR ANALOG-TO-DIGITAL CONVERTER APPLICATION A Thesis Presented to The Graduate Faculty of The University of Akron In Partial Fulfillment of the Requirements for the Degree Master of Science Matthew D. Kollarits August, 21

2 DESIGN AND SIMULATION OF A TEMPERATURE-INSENSITIVE RAIL-TO-RAIL COMPARATOR FOR ANALOG-TO-DIGITAL CONVERTER APPLICATION Matthew D. Kollarits Thesis Approved: Accepted: Advisor Dr. Robert Veillette Co-Advisor Dr. Joan Carletta Committee Member Dr. Kye-Shin Lee Department Chair Dr. Alex De Abreu-Garcia Dean of the College Dr. George K. Haritos Dean of the Graduate School Dr. George R. Newkome Date ii

3 ABSTRACT A comparator with rail-to-rail input voltage range is presented. The rail-to-rail operation is achieved using two folded-cascode differential amplifiers operating in parallel as an input stage. The output of the appropriate amplifier is connected to the comparator output through a transmission-gate logic stage. Temperature-insensitivity is achieved by designing the input-stage amplifiers for zero-temperature-coefficient (ZTC) operation. The proposed comparator was simulated using.5µm silicon-on-insulator CMOS (SOI-CMOS) models. The circuit provides propagation delay less than 146.9ns. Over the V to 3.3V rail-to-rail common-mode input voltage range, the maximum inputoffset voltage is less than 3µV at 27 C and less than 1.91mV over the temperature range of 27 C to 125 C. The comparator is shown to be suitable for a successive-approximation-register analog-to-digital converter (SAR-ADC) application by a series of validation simulations. An 8-bit SAR-ADC incorporating the comparator was tested to determine its integral non-linearity (INL) and differential non-linearity (DNL). The SAR-ADC exhibited a worst-case INL of.6lsb and a worst-case DNL of.2lsb over the temperature range 27 C to 125 C. The SAR-ADC is capable of completing one conversion every 15µs, which is adequate for sampling at a rate of 65 Kilo-samples per second (KSPS). iii

4 DEDICATION I would like to dedicate this thesis to my parents, Dr. Frank J. Kollarits and Dr. Carol R. Kollarits. This thesis would not have been possible without their support, encouragement, and love. iv

5 ACKNOWLEDGEMENTS I would like to acknowledge my thesis advisory committee, Dr. Robert Veillette, Dr. Joan Carletta, Dr. Firas Hassan and Dr. Kye-Shin Lee, for their technical input and support throughout the conception, realization and culmination of this thesis project. I would like to thank Mr. Mike Ward for opening the door to this opportunity and encouraging me to pursue this thesis project. I wish to also express my most sincere gratitude to the Electrical Engineering Department of the University of Akron for supporting my studies through a research assistantship. v

6 TABLE OF CONTENTS Page LIST OF TABLES... viii LIST OF FIGURES... ix CHAPTER I. INTRODUCTION Motivation Contribution and Goal Thesis Organization...4 II. BACKGROUND ZTC and SOI-CMOS Background Comparator Characteristics Proposed Comparator Design Background Differential Amplifiers for Comparator Input Stages Rail-to-Rail Common-Mode Input Voltage Range Comparator Input Stages...11 III. DESIGN Comparator Topology Folded-Cascode Differential Amplifier Folded-Cascode Differential Amplifier Drain Currents Wilson Current Mirror Design...2 vi

7 3.2.3 NMOS Biasing Current Source Design NMOS Cascode Design P-tail Current Source Design Differential Amplifier Input Design Bias Generation Circuit Parallel-Folded-Cascode Amplifier Input Stage Transmission-Gate Logic Stage...28 IV. VALDATION Performance Specifications Input-Offset Voltage Minimum Output Voltage Range Propagation Delay Input Capacitance Simulation and Validation Conclusions...47 V. APPLICATION SAR-ADC Topology SAR-ADC Operation INL and DNL Simulations Sample-and-Hold Input Device...61 VI. CONCLUSIONS AND FUTURE WORK...77 BIBLIOGRAPHY...8 vii

8 LIST OF TABLES Table Page 3.1 Folded-Cascode Differential Amplifier Channel Dimensions, Terminal Voltages and Drain Currents a) P-tail Configuration b) N-tail Configuration Transmission-Gate Logic Stage Channel Dimensions Variation of V TN and V TP Over Process and Temperature Required Comparator Performance for the SAR-ADC Propagation Delay (27 C) Propagation Delay (125 C) Proposed Comparator Performance Validation Conclusions...53 viii

9 LIST OF FIGURES Figure Page 2.1 Zero-Temperature-Coefficient Concept [13] Differential Input, Single-Ended Output Voltage Comparator Symbol Ideal Comparator Transfer Characteristic Comparator Transfer Characteristic with Finite Differential Voltage Gain Comparator Transfer Characteristic with Finite Differential Voltage Gain and Input-Offset Voltage Five-Transistor Differential Amplifier Cascode Differential Amplifier Folded-Cascode Differential Amplifier Complementary-Folded-Cascode Rail-to-Rail Differential Amplifier Input Stage [22] Proposed Comparator Block-Level Topology Folded-Cascode Differential Amplifier a) P-tail Configuration b) N-tail Configuration Folded-Cascode Differential Amplifier Design Flow Effect of Drain-to-Source Voltage on Gate Bias Voltage for ZTC Operation a) Initial V DS Simulation b) V DS = V OV Simulation Bias Generation Circuit Folded-Cascode Differential Amplifier Drain Current Versus Common-Mode Input Voltage a) P-tail Configuration b) N-tail Configuration Transmission-Gate Logic Stage Modes of Operation Concept...35 ix

10 3.8 Transmission-Gate Logic Stage Transmission-Gate Logic Stage Modes of Operation Comparator Differential Input Voltage Characteristic Showing Input-Offset Voltage a) 27 C b) 125 C HIGH Output Voltage (27 C) HIGH Output Voltage (125 C) LOW Output Voltage (27 C) LOW Output Voltage (125 C) Rising Edge Step Response at 2.75V Common-Mode Input Voltage (27 C) Falling Edge Step Response at.75v Common-Mode Input Voltage (27 C) Input Capacitance Test Circuit Input Capacitance Simulation Experiment Results at 1.65V (27 C) SAR-ADC Topology SAR-ADC Example Timing Diagram Integral and Differential Non-Linearity Concepts a) Output Transfer Characteristic b) INL Representation c) DNL Representation Integral Non-Linearity a).5lsb Input Step from.75v to 2.75V b).1lsb Input Step from.75v to.789v c).1lsb Input Step from 2.71V to 2.75V (27 C) Integral Non-Linearity a).5lsb Input Step from.75v to 2.75V b).1lsb Input Step from.75v to.789v c).1lsb Input Step from 1.921V to 1.96V d).1lsb Input Step from 2.71V to 2.75V (125 C) Differential Non-Linearity a).1lsb Input Step from code to 5 b).1lsb Input Step from code 251 to 255 (27 C) Differential Non-Linearity a).1lsb Input Step from code to 5 b).1lsb Input Step from code 15 to 155 c).1lsb Input Step from code 251 to 255 (125 C)...72 x

11 5.8 Sample-and-Hold Input Device Charge Feedthrough SAR-ADC with Sample-and-Hold Input Device Charge Feedthrough Example Integral Non-Linearity with Sample-and-Hold Input Device a).5lsb Input Step from.75v to 2.75V b).1lsb Input Step from.75v to.789v c).1lsb Input Step from 1.187V to 1.226V d).1lsb Input Step from 1.84V to 1.843V e).1lsb Input Step from 2.335V to 2.375V f).1lsb Input Step from 2.71V to 2.75V (27 C) Integral Non-Linearity with Sample-and-Hold Input Device a).5lsb Input Step from.75v to 2.75V b).1lsb Input Step from.75v to.789v c).1lsb Input Step from.789v to.828v d).1lsb Input Step from 1.593V to 1.632V e).1lsb Input Step from 2.593V to 2.625V f).1lsb Input Step from 2.71V to 2.75V (125 C) Differential Non-Linearity with Sample-and-Hold Input Device a).1lsb Input Step from code to 5 b).1lsb Input Step from code 56 to 61 c).1lsb Input Step from code 135 to 14 d).1lsb Input Step from code 23 to 28 e).1lsb Input Step from code 251 to 255 (27 C) Differential Non-Linearity with Sample-and-Hold Input Device a).1lsb Input Step from code to 5 b).1lsb Input Step from code 5 to 1 c).1lsb Input Step from code 18 to 113 d).1lsb Input Step from code 235 to 24 e).1lsb Input Step from code 251 to 255 (125 C)...76 xi

12 CHAPTER I INTRODUCTION 1.1 Motivation A comparator is an integral part of a successive-approximation-register analog-to-digital converter (SAR-ADC) [1-4]. In an SAR-ADC the input-offset voltage of the comparator limits accuracy. The propagation delay time of the comparator limits the speed of the SAR-ADC. The comparator common-mode input voltage range can limit the SAR-ADC full-scale analog input voltage range. For these reasons the design of the comparator is crucial to the quality of the SAR-ADC. A comparator with rail-to-rail operation, meaning one for which the common-mode input voltage range extends to both the upper and lower supply voltage levels, is beneficial in an SAR-ADC. A comparator with a rail-to-rail input voltage range allows for the largest practical ADC full-scale input voltage range; thus, rail-to-rail operation is common and especially important in low-voltage applications and designs. If all other characteristics remain constant, a larger input voltage range implies better accuracy relative to full-scale variations. Temperature-insensitive operation is highly desirable in a comparator to be used in an SAR-ADC. A circuit designed for a wide temperature range has practical 1

13 applications in aerospace, automotive, nuclear energy, and other industries. Sensor circuits in all of these applications experience wide temperature fluctuations that would render circuits not designed for temperature-insensitive operation inaccurate and unreliable. 1.2 Contribution and Goal The contribution of this thesis is the design of a temperature-insensitive rail-to-rail comparator to be implemented in an SAR-ADC. To accommodate a rail-to-rail input voltage range the input stage of the proposed comparator is configured with two separate differential amplifiers in parallel. Each of the input-stage differential amplifiers is designed using a folded-cascode (FC) topology, one with a P-tail configuration and the other with an N-tail configuration. The P-tail FC differential amplifier has a common-mode input voltage range that extends to the lower supply rail and the N-tail FC differential amplifier has a common-mode input voltage range that extends to the upper supply rail [5, 6]. The combination of these two FC differential amplifiers, referred to as the parallel-folded-cascode (PFC) amplifier input stage, produces two in-phase candidate output voltages. To select between the two candidate output voltages a transmission-gate logic (TGL) stage is used. The TGL stage selects and passes the candidate output voltages of the PFC amplifier input stage depending on the non-inverting input voltage level of the comparator. The output of the TGL stage is buffered to digital logic levels. The proposed 2

14 comparator design, and in particular the use of a transmission-gate logic stage, is original to this thesis and has not been reported in literature. Temperature-insensitive operation of the input-stage FC differential amplifiers is achieved by biasing the gates of the tail current source transistors, cascode transistors and biasing current source transistors for zero-temperature-coefficient (ZTC) operation. At the gate bias voltage for ZTC operation of a transistor, the effects of temperature on electron mobility and threshold voltage cancel one another and the saturation drain current remains relatively constant over temperature [7-13]. The proposed comparator has been designed in.5µm SOI-CMOS and verified for temperature-insensitive operation by simulation in the Cadence Virtuoso circuit simulator over a temperature range of 27 C to 125 C. The input-offset voltage of the comparator is no greater than 3µV at 27 C over the V to 3.3V rail-to-rail input voltage range. Over the rail-to-rail input voltage range and the temperature range 27 C to 125 C the input-offset voltage of the comparator is no greater than 1.91mV. This level of accuracy is suitable to achieve an error of less than 1LSB in a 1-bit SAR-ADC with a V to 3.3V full-scale input voltage range. The worst-case propagation delay of the comparator over the temperature range is approximately 146.9ns. The effective input capacitance is no greater than.436pf. An 8-bit SAR-ADC utilizing the proposed comparator is simulated assuming a 3.3V unipolar power supply. The analog input voltage range corresponding to the full digital (binary) output range of the SAR-ADC is.75v to 2.75V. The full-scale input range of the SAR-ADC is limited by the design of the digital-to-analog converter (DAC) used; thus, the simulations demonstrate the accuracy of the comparator but not its 3

15 rail-to-rail operation. The SAR-ADC operates over the temperature range 27 C to 125 C and is capable of performing a conversion every 15µs, which is adequate for a sampling rate of 65 Kilo-samples per second (KSPS). The 8-bit SAR-ADC design exhibits worst-case integral non-linearity (INL) between.5lsb and.6lsb and worst-case differential non-linearity (DNL) between LSB and.2lsb when the input is supplied by an ideal constant voltage source. When the input is supplied by a sample-and-hold (SH) input device, worst-case INL degrades to between 1LSB and 1.1LSB and worst-case DNL degrades to between.5lsb and.6lsb due to charge feedthrough during each clock cycle of the conversion period. 1.3 Thesis Organization Chapter 2 presents background information related to the proposed comparator. Metrics for evaluating the performance characteristics of comparators are presented. The ZTC bias point is explained, and input-stage amplifiers for comparators are presented. Chapter 3 presents the temperature-insensitive rail-to-rail comparator design. Transistor-level designs of the blocks of the proposed comparator are discussed. Chapter 4 presents simulations which validate the comparator design for an 8-bit SAR-ADC. The simulations determine input-offset voltage, output voltage range, and propagation delay and input capacitance over the temperature range. These simulations confirm the comparator is suitable for a 1-bit SAR-ADC with a rail-to-rail input voltage range. 4

16 Chapter 5 presents the 8-bit SAR-ADC in which the comparator is used. Timing issues are addressed as they pertain to the SAR and the DAC. The INL and DNL of the SAR-ADC are presented over the temperature range. The effects of a sample-and-hold input device on the INL and DNL are presented. Chapter 6 presents conclusions and future work. 5

17 CHAPTER II BACKGROUND This chapter presents the background necessary for the design of the proposed comparator. For temperature considerations the benefits of SOI-CMOS and the gate bias voltage for ZTC operation are explained. The parameters for evaluating the performance characteristics of the comparator in this thesis are defined. Input-stage amplifiers are presented, with special attention to those that operate with rail-to-rail input voltages. 2.1 ZTC and SOI-CMOS Background It is a well established fact that there exists a gate bias voltage for zerotemperature-coefficient (ZTC) operation for both n-channel and p-channel transistor devices operating in saturation [7, 11-13]. ZTC operation provides a nearly constant drain current in bulk-cmos for temperatures up to 2 o C-25 o C [7, 8] and in the case of SOI-CMOS up to 32 o C [9, 1]. The gate bias voltage for ZTC operation can be obtained in simulation by plotting the drain current versus the gate-to-source voltage at several temperatures, assuming a constant drain-to-source voltage. An example set of plots is presented in Figure 2.1 which is sourced from [13]. 6

18 Some CMOS processes such as SOI-CMOS are inherently better suited for high temperature designs [7-1].Conversely, some processes like bulk-cmos are inferior. A bulk-cmos operational amplifier (op-amp), for example, exhibits an increase in the leakage current to the substrate with increasing temperature which can result in loss of operation. In SOI-CMOS there is no path for leakage current to the substrate; the only path for leakage current to follow in an op-amp is through the branches of the amplifier. Therefore, a circuit implemented in SOI-CMOS operates over a wider temperature range, with smaller changes in the bias points due only to changing thresholds and electron mobility. The superior behavior of SOI-CMOS technology at high temperature makes it highly suitable for extreme temperature applications, especially those in excess of 2 o C. 2.2 Comparator Characteristics A differential input, single-ended output voltage comparator, referred to here simply as a comparator, is a circuit that compares the instantaneous value of two input voltages and produces a digital logic level output. The digital logic level output is dependent on which of the two input voltages is larger. The symbol for a comparator (Figure 2.2) is very similar to that of an operational amplifier (op-amp). The transfer characteristic of an ideal comparator is presented in Figure 2.3. If the voltage at the non-inverting input is below that at the inverting input, the output voltage is saturated LOW (V OL ). Conversely, when the non-inverting input voltage is above that of the inverting input, the output voltage is saturated HIGH (V OH ). For an ideal comparator, the transition in the center of Figure 2.3, where the differential input voltage (V V ) 7

19 equals V, is exactly vertical, corresponding to an infinite differential voltage gain at that point [6]. The transfer characteristic of a comparator with finite differential voltage gain at the transition is presented in Figure 2.4. For this non-ideal characteristic, the output does not reach saturation until the differential input voltage (V V ) is above V IH or below V IL [6]. The values of V IL and V IH are determined by the points on the comparator transfer characteristic where the gain of the comparator, the slope of the curve, is unity. These values are considered the minimum differential input voltages to produce a saturated output voltage. The transfer characteristic of a comparator with finite differential voltage gain and an input-offset voltage (V OS ) is presented in Figure 2.5. For this non-ideal characteristic, the output crosses the threshold represented by the horizontal axis for a differential input voltage (V V ) equal to V OS [6]. In this case, V IL and V IH are determined with respect to the value of V OS. The most significant performance characteristics for a comparator are the following [6, 14]: Response Time - the time interval between the edge of an input step function and the time when the output begins to change. This characteristic depends on the input differential voltage step size. Rise/Fall Time - in the response of the output voltage to a step input, the elapsed time from the initial change in the output voltage to an output voltage change of a given percentage, usually 5%, of the full swing of the output voltage. Propagation Delay Time - the sum of response time and rise/fall time. 8

20 Common-Mode Input Voltage Range - range of input voltages for which proper operation is exhibited. Output Voltage Range - the range of possible output voltages, i.e., V OL to V OH. Input-Offset Voltage - the differential input voltage that produces an output voltage in the middle of the output voltage range. Differential Voltage Gain - ratio of incremental output voltage to incremental differential input voltage in the transition region. 2.3 Proposed Comparator Design Background This section presents background information related to the design of the proposed comparator. Topics include input-stage amplifiers for comparators, and rail-to-rail input-stage amplifiers for comparators Differential Amplifiers for Comparator Input Stages In general, there are four types of comparator architectures that are commonly used and referred to in the literature; they include single-ended auto-zeroing, differential, regenerative and fully-differential architectures [5, 6]. In this thesis a differential architecture is considered because the SAR-ADC application requires a differential comparator. A differential comparator requires at least one differential amplifier as its input stage. 9

21 The simplest example of a differential amplifier is the five-transistor version presented in Figure 2.6. However, for most applications the gain of the five-transistor differential amplifier is not sufficient. This shortcoming may be overcome by introducing additional gain stages in cascade. Unfortunately, cascading differential amplifier stages leads to a cascading of offset voltages, resulting in low accuracy [6]. The cascode differential amplifier presented in Figure 2.7 has larger voltage gain than that of the five-transistor differential amplifier [5]. The cascode differential amplifier configuration contains a common-gate transistor pair and two cascode current mirrors to increase the output resistance. The most important disadvantage of this circuit is the common-mode input voltage range, which does not reach either supply rail voltage level (V DD or V SS ). The folded-cascode (FC) differential amplifier presented in Figure 2.8 consists of a PMOS common-source and an NMOS common-gate stage. The differential voltage gain of the FC differential amplifier is approximately the same as that of the cascode amplifier. The advantage is that the common-mode input voltage range of the FC differential amplifier extends to one of the supply rail voltages. The input range of the P- tail configuration, presented in Figure 2.8, can extend to V SS ; the input range of an N-tail configuration of the circuit can extend to V DD. Variations of the FC differential amplifier can reduce the power consumption and increase gain. The recycling-folded-cascode (RFC) differential amplifier uses the existing transistors from the FC topology to recycle or reuse the load currents to reduce power consumption [15, 16]. Gain-boosted-folded-cascode (GBFC) differential amplifiers are presented in [17-2]. The gain-boosting operation is costly in terms of power and requires 1

22 a large transistor count and area. However, applications like switched capacitor filters that require extremely fast settling times, less than 1ns, will utilize GBFC differential amplifiers despite the disadvantages. In this thesis, standard FC differential amplifiers are used in the input stage of the comparator Rail-to-Rail Common-Mode Input Voltage Range Comparator Input Stages The most common method for designing a comparator with a rail-to-rail commonmode input voltage range is to use N-tail and P-tail amplifier input stages in a complementary fashion [21, 22]. The predominant rail-to-rail input-stage amplifier is the complementary-folded-cascode (CFC) differential amplifier. Figure 2.9 presents an example of a CFC differential amplifier from [22]. Two FC differential amplifiers, one N-tail and one P-tail, are combined by removing the current mirror loads and connecting the drain terminals of the NMOS cascode and the PMOS cascode from the two configurations. This circuit has a rail-to-rail common-mode input voltage range; however, it is sensitive to temperature variations as the tail currents must be precisely matched. Several variations of the CFC differential amplifier have been presented in [21-27]. Some of the designs presented in these articles are internally biased, meaning the gate voltage of some or all of the biased transistors are obtained from some node inside the amplifier. In the case of Figure 2.9, the NMOS cascode, NMOS biasing current source, PMOS cascode and PMOS biasing current source are internally biased. External biasing is necessary for 11

23 I D (ua) operation at ZTC bias points; therefore, only externally biased amplifier architectures are considered in this thesis. The proposed comparator in this thesis uses a differential amplifier input stage, referred to as the parallel-folded-cascode (PFC) amplifier input stage. The input stage consists of two separate FC differential amplifiers. To achieve a rail-to-rail input voltage range, one differential amplifier is designed in a P-tail configuration and one in an N-tail configuration. The non-inverting and inverting inputs of the comparator are connected to both input-stage FC differential amplifiers in parallel. The input-stage FC differential amplifiers thus produce two in-phase output voltages, referred to as the comparator candidate output voltages. The two input-stage FC differential amplifiers operate independently which makes their bias designs simpler and less sensitive than those of complementary configurations. The selection between the comparator candidate output voltages is done by a transmission-gate logic stage. The overall design of the comparator is presented in the next chapter C 75C 125C 1 ZTC V GS (V) Figure 2.1 Zero-Temperature-Coefficient Concept [13] 12

24 V + V V OUT Figure 2.2 Differential Input, Single-Ended Output Voltage Comparator Symbol V OUT V OH (V + - V - ) V OL Figure 2.3 Ideal Comparator Transfer Characteristic 13

25 V OUT V OH V IL V IH (V + - V - ) V OL Figure 2.4 Comparator Transfer Characteristic with Finite Differential Voltage Gain V OUT V OH V OS V IL V IH (V + - V - ) V OL Figure 2.5 Comapartor Transfer Characteristic with Finite Differential Voltage Gain and Input-Offset Voltage 14

26 V DD V BIAS V - V + V OUT V SS Figure 2.6 Five-Transistor Differential Amplifier V DD V BIAS1 V - V + V BIAS2 V OUT V SS Figure 2.7 Cascode Differential Amplifier 15

27 V DD V BIAS1 V- V+ V OUT V BIAS2 VBIAS3 V SS Figure 2.8 Folded-Cascode Differential Amplifier V DD V BIAS-P-tail V+ V- V OUT V BIAS-N-tail V SS Figure 2.9 Complementary-Folded-Cascode Rail-to-Rail Differential Amplifier Input Stage [22] 16

28 CHAPTER III DESIGN This chapter presents the design of the proposed comparator. The complete block-level comparator topology is presented, followed by the transistor-level design details for the parallel-folded-cascode (PFC) amplifier input stage and the transmission-gate logic (TGL) stage. 3.1 Comparator Topology The proposed comparator block-level topology is presented in Figure 3.1. From left to right, the blocks of the proposed comparator are the parallel-folded-cascode (PFC) amplifier input stage, the transmission-gate logic (TGL) stage and the buffer. The comparator inputs (V and V ) are connected to both of the input-stage differential amplifiers in parallel. The PFC amplifier input stage thus produces two in-phase output voltages (V PO and V NO ). These two output voltages are the candidate comparator output voltages supplied to the TGL stage. The TGL stage uses the non-inverting input voltage (V ) to control the transmission gates and so determines which of the candidate comparator output voltages are passed to the output of the TGL stage (V PRE-BUFF ). This output is then supplied to a buffer which drives the comparator output voltage (V OUT ) to a 17

29 digital logic level under no-load conditions. The output of the comparator reaches digital logic levels for any differential input voltage greater than the input-offset voltage of the comparator. 3.2 Folded-Cascode Differential Amplifier The PFC amplifier input stage of the proposed comparator uses two FC differential amplifiers, one of P-tail configuration and one of N-tail configuration. The two FC differential amplifiers, presented in Figure 3.2, are completely separate from one another. Each FC differential amplifier operates independently and is biased independently. The final transistor channel dimensions, operational bias-point terminal voltages and operational bias-point drain currents of the P-tail and N-tail FC differential amplifiers are listed in Table 3.1 a) and Table 3.1 b). The following design discussion pertains to the P-tail FC differential amplifier (m1 to m11) shown in Figure 3.2 a). The design of the N-tail FC differential amplifier (m12 to m22) shown in Figure 3.2 b) is similar, and is therefore not discussed. Figure 3.3 presents the design flow used to design the P-tail configuration of the FC differential amplifier. The design flow consists of six steps to select, calculate and derive the drain currents, channel dimensions and gate bias voltages for ZTC operation of the complete FC differential amplifier. Over the next few sections the process to arrive at these values is presented. 18

30 3.2.1 Folded-Cascode Differential Amplifier Drain Currents This section presents Step 1 from Figure 3.3, the selection of the drain currents for all the transistors (m1 to m11). The tail current (I D-m1 ) determines the total current in the differential amplifier input transistors (m2 and m3).the tail current is selected to be I D-m1 =8µA arbitrarily. However, there are tradeoffs made by the selection of the tail current. Larger tail currents provide increased differential voltage gain at the expense of increased power consumption. It is advantageous to design for small currents in the Wilson current mirror transistors (m4 to m7) and the NMOS cascode transistors (m8 and m9) to minimize the total power consumption and channel dimensions. Using small currents in the Wilson current mirror transistors and NMOS cascode transistors is also beneficial for the differential voltage gain of the FC differential amplifier; when this is done, a small change in the currents in the differential amplifier input transistors (m2 and m3), due to a differential input voltage, translates to a very large percentage change in the small Wilson current mirror and NMOS cascode currents ( I D-m4 to I D-m9 ). The drain currents of the Wilson current mirror transistors and the NMOS cascode transistors are arbitrarily selected to be I D-m4 = = I D-m9 =¼ I D-m1 =2µA. (3.1) By simple current summation 19

31 I D-m1 = I D-m11 =½ I D-m1 +2µA=6µA; (3.2) this value determines the design of the NMOS biasing current source transistors (m1 and m11) Wilson Current Mirror Design This section presents Step 2 from Figure 3.3, the design of the Wilson current mirror transistors. At this point the output voltage is selected to be V PO =V D-m6,m7 =½V DD =1.65V. (3.3) The drain-to-source voltage of the Wilson current mirror transistors (m4 to m7) is selected to be V DS-m4 to m7 =¼V DD =.825V, (3.4) so that m4 to m7 can be designed as matched transistors. The value of V DS-m4 to m7 is considered fixed so the channel dimensions can be determined. The channel dimensions of the Wilson current mirror transistors are selected such that m4 to m7 produce the current selected in Step 1. The channel length (L) is selected to be 2µm; this medium length was found to provide adequate incremental output resistance, and therefore adequate differential voltage gain in the FC differential 2

32 amplifiers. A longer channel length could have been selected, for higher gain, at the expense of increased area. The channel width (W) is selected to be 28.4µm, which ensures that m4 to m7 produce the desired 2µA NMOS Biasing Current Source Design This section presents Step 3 from Figure 3.3, the design of the NMOS biasing current sources. The design of the NMOS biasing current source transistors (m1 and m11) determines the minimum output voltage that can be achieved by the FC differential amplifier. The minimum output voltage is calculated by first assuming the NMOS cascode transistors (m8 and m9) are biased in such a way that the NMOS biasing current source transistors (m1 and m11) are operating at the edge of the saturation region and therefore the drain-to-source voltage of m1 and m11 is [5] V DS-m1, m11 = V OV-m1,m11 = V GS-m1,m11 V T, (3.5) where V T is the threshold voltage. The minimum output voltage is achieved when m9 is also operating at the edge of saturation with V DS-m9 = V OV-m9, so that V PO (min)=v SS V DS-m11 V DS-m9 =V SS V OV-m11 V OV-m9. (3.6) If the drain-to-source voltage of m1 and m11 is larger than V OV-m11, a higher minimum output voltage will result, reducing the output voltage range. To obtain the largest output 21

33 voltage range the FC differential amplifier can produce, the drain-to-source voltage of the NMOS biasing current source transistors must satisfy (3.6). The following paragraphs show how to ensure that V DS-m1, m11 = V OV-m1,m11 while m1 and m11 are biased for ZTC operation. Simulations show that the gate bias voltage for ZTC operation ( V G-ZTC ) changes with drain-to-source voltage. The proper channel dimensions, gate bias voltage and drain-to-source voltage for ZTC operation of m1 and m11 are determined by a process of trial and error. Initially the channel dimensions for m1 and m11 are selected. The channel length (L) of each transistor (m1 and m11) is selected to be 5µm; this gives each transistor a high incremental output resistance, which helps make m1 and m11 constant current sources. The channel width (W) is arbitrarily selected to begin the following iterative process. Next, the drain-to-source voltage is assumed to be V DS-m1, m11 =¼V DD =.825V. (3.7) Given the initial values of W and V DS-m1, m11, and the fixed value of L, a simulation is done to determine the gate bias voltage for ZTC operation. Figure 3.4 a) shows the resulting I D versus V GS characteristics that reveal this initial gate bias voltage for ZTC operation. In this case the gate bias voltage for ZTC operation is V G-ZTC =1.55V. This gate bias voltage is used to determine the drain-to-source voltage required for m1 and m11 to operate at the edge of saturation. This voltage is calculated as 22

34 V OV-m1, m11 = V GS V T = V G-ZTC V T =1.55V.655V=.4V, (3.8) where the threshold voltage (V T ) of a PMOS transistor is.655v. The new drain-to-source voltage is set to 5% (2mV) higher than the edge-of-saturation voltage, to ensure that m1 and m11 are operating in the saturation region. Therefore, the new drain-to-source voltage is calculated as V DS-m1, m11 =1.5 V OV-m1,m11 =1.5.4V=.42V. (3.9) At this point the I D versus V GS characteristics are replotted to find the new gate bias voltage for ZTC operation assuming the new value of V DS-m1, m11 =.42V. The result is shown in Figure 3.4 b). The simulation results indicate the gate bias voltage for ZTC operation has shifted downward by 3mV, from 1.55V to 1.25V. Calculating a new V OV-m1, m11 and V DS-m1, m11 for a second time and replotting I D versus V GS yields a minimal change in the gate bias voltage for ZTC operation; therefore, the process ends. If the drain current at the gate bias voltage for ZTC operation corresponds to the drain current selected in Step 1, the process is complete and the gate bias voltage for ZTC operation has been determined; if not, the channel dimensions are adjusted, increasing W to increase current or decreasing W to decrease current, and the process is repeated. At the end of the iterative process, the gate bias voltage of the NMOS biasing current source transistors is found to be V G-m1, m11 =1.25V, and the channel dimensions of m1 and m11 are found to be W=57.5µm and L=5µm for ZTC operation. 23

35 3.2.4 NMOS Cascode Design This section presents Step 4 from Figure 3.3, the design of the NMOS cascode transistors. The drain-to-source voltage of the NMOS cascode transistors has been determined by the previous two design steps and is calculated as V DS-m8, m9 = V D-m6, m7 V D-m1, m11 =1.65V.42V=1.23V. (3.1) This value of V DS is considered fixed. The proper channel dimensions and gate bias voltage for ZTC operation of m8 and m9 are determined by a process of trial and error. At this point some initial channel dimensions are selected. The channel length (L) of each transistor (m8 and m9) is selected to be.8µm; this length was found to provide adequate incremental output resistance, and therefore adequate differential voltage gain in the FC differential amplifiers. A longer channel length could have been selected, for higher gain, at the expense of increased area. The channel width (W) is arbitrarily selected to begin the following iterative process. Given the initial value of W, and the fixed values of L and V DS-m8, m9, a simulation is done to determine the gate bias voltage for ZTC operation. If the drain current at this gate bias voltage corresponds to the drain current selected in Step 1, the process is complete and ZTC operation has been achieved; if not, the channel dimensions are adjusted, increasing W to increase current or decreasing W to decrease current, and the process is repeated. At the end of the iterative process the gate bias voltage of the 24

36 NMOS cascode transistors is found to be V G-m8, m9 =1.536V and the channel dimensions of m8 and m9 are found to be W=1.7µm and L=.8µm for ZTC operation P-Tail Current Source Design This section presents Step 5 from Figure 3.3, the design of the tail current source transistor m1. The drain-to-source voltage of the tail current source is selected to be V DS-m1 =¼V DD =.825V. (3.11) The proper channel dimensions and gate bias voltage for ZTC operation are determined by a process of trial and error. At this point some initial channel dimensions are selected. The channel length (L) of m1 is selected to be 5µm; a long length gives m1 a high incremental output resistance, which helps make m1 a constant current source. The channel width (W) is arbitrarily selected to begin the following iterative process. Given the initial value of W, and the fixed values of L and V DS-m1, a simulation is done to determine the gate bias voltage for ZTC operation. If the drain current at the gate bias voltage for ZTC operation corresponds to the drain current selected in Step 1, the process is complete and ZTC operation has been achieved; if not, the channel dimensions are adjusted, increasing W to increase current or decreasing W to decrease current, and the process is repeated. At the end of the iterative process the gate bias voltage of the tail current source transistor is found to be V G-m1 =2.391V and the channel dimensions are found to be W=17µm and L=5µm for ZTC operation. 25

37 3.2.6 Differential Amplifier Input Design This section presents Step 6 from Figure 3.3, the design of the differential amplifier input transistors. For this part of the design, the amplifier input voltages are assumed to be in the middle of the supply voltage range. Thus, the gate voltages of the differential amplifier input transistors m2 and m3 are V G-m2, m3 = ½V DD =1.65V and are considered to be fixed. The drain-to-source voltage of m2 and m3 has been determined by the previous design steps, Step 3 and Step 5, and is calculated as V DS-m2, m3 = V DD V DS-m1 V D-m1, m11 =3.3V.825V.42V=2.55V. (3.12) Assuming V DS-m2, m3 is fixed for the given input voltage V G-m2, m3, the channel dimensions of m2 and m3 are selected such that m2 and m3 provide the current selected in Step 1. The channel length (L) of each transistor (m2 and m3) is selected to be 2µm; this medium length was found to provide adequate incremental output resistance, and therefore adequate differential voltage gain in the FC differential amplifiers. A longer channel length could have been selected, for higher gain, at the expense of increased input capacitance. The channel width (W) is selected to be 51.7µm, which ensures that m2 and m3 produce the desired 4µA. 26

38 3.2.7 Bias Generation Circuit The six bias voltages required in the design of the two FC differential amplifiers were obtained from six bias generation circuits. Figure 3.5 shows an example of a bias circuit; it is built using a single PMOS and two NMOS transistors in series, each in a diode-connected configuration. The channel dimensions of the transistors are selected such that the output voltage of the bias circuit (V BIAS ) is the gate bias voltage necessary for ZTC operation. Over the temperature range 27 C to 125 C, the output voltages of the bias circuits vary by no more than 16µV from the designed values, which is sufficient to maintain ZTC operation. 3.3 Parallel-Folded-Cascode Amplifier Input Stage At this point in the design process the P-tail and N-tail FC differential amplifiers for the PFC amplifier input stage have been designed. An important consideration for the design of the PFC amplifier input stage is the range of common-mode input voltages for which the P-tail and N-tail FC differential amplifiers operate properly. Figure 3.6 a) and 3.6 b) show the currents through the tail current source transistors (m1 and m12), the cascode transistors m9 and m19, and the biasing current source transistors m11 and m21 as a function of common-mode input voltage. These figures indicate the common-mode input voltage range for which each FC differential amplifier operates. Each FC differential amplifier operates best for the input voltage range over which the tail current is near the designed value of 8µA. The FC differential amplifiers continue to operate 27

39 when the tail current is as low as 6µA, but with reduced differential voltage gain. The P-tail FC differential amplifier is operational for common-mode input voltages of 2.3V and lower. Conversely, the N-tail FC differential amplifier is operational for common-mode input voltages of 1.V and higher. In the common-mode input voltage ranges where the tail currents are near 8µA, the cascode transistor drain currents and biasing current source drain currents are also near their designed values. Combining the input voltage ranges of these two circuits in one input stage yields a rail-to-rail input voltage range for the comparator. The output of the PFC amplifier input stage consists of two candidate comparator output voltages. Depending on the noninverting input voltage level, the transmission-gate logic (TGL) stage selects one or both of the candidate comparator output voltages. In the next section, the TGL stage is presented. 3.4 Transmission-Gate Logic Stage The TGL stage has three modes of operation, referred to as the P-tail only, mutual operation, and N-tail only modes, depending on the non-inverting input to the comparator. Figure 3.7 illustrates the relationship between the non-inverting input voltage and the corresponding modes of operation. When the non-inverting input voltage is below a particular threshold V TN, only the P-tail FC differential amplifier output is passed to the output of the comparator. When the non-inverting input is above a higher threshold V TP, only the N-tail FC differential amplifier output is passed. When the non-inverting input is between the two thresholds, both FC differential amplifier outputs are passed. 28

40 Figure 3.8 shows the circuit diagram of the transmission-gate logic (TGL) stage, which consists of two transmission gates whose control lines are driven by a set of inverters and buffers. The non-inverting input voltage is used to control the two transmission gates. The operation of a generic SAR-ADC can help to understand this design choice. As the SAR-ADC conversion process progresses, the inverting input voltage level (the DAC output) moves around, while the non-inverting input is fixed. This makes the non-inverting input a better choice as the control signal. The threshold voltages V TN and V TP are designed to ensure the TGL stage passes at least one signal. This is done by choosing the thresholds to be V TN =½V DD dv and V TP =½V DD dv where dv> is large enough to remove the possibility of both transmission gates being turned off, as could happen if process or other variations caused V TN >V TP in implementation. The nominal values of V TN and V TP are 1.375V and 1.925V, respectively, which corresponds to dv.275v. This leaves a margin of 55mV between the two thresholds. The thresholds must also ensure that the transmission gate connected to the output of the P-tail FC differential amplifier is turned off for common-mode input voltage levels higher than 2.3V and that the transmission gate connected to the output of the N-tail FC differential amplifier is turned off for common-mode input voltage levels lower than 1.V. The choices of V TN =1.375V and V TP =1.925V ensure this condition when the comparator is used as part of an SAR-ADC. As a result, the TGL stage never passes a candidate comparator output voltage from a non-operational FC differential amplifier. For example, for any value of V < V TP, the values taken by V during the SAR-ADC conversion process will never exceed never exceed ¾V DD =2.475V; so, the 29

41 common-mode input voltage will never be greater than 2.2V. A similar analysis can be made with V TN ; thus, the comparator has a rail-to-rail input range and the output of the comparator is always resultant from at least one operational FC differential amplifier. The transistors m23 to m38 within the buffers and inverters presented in Figure 3.8 are sized to obtain the desired thresholds. The resulting channel dimensions are listed in Table 3.2. The threshold voltage levels are observed via simulation by sweeping the non-inverting input voltage from GND to V DD and plotting the transfer characteristics for the buffers and inverters. These transfer characteristics are shown in Figure 3.9. Two vertical lines in the figure are used to represent V TN and V TP. The simulation results show that V TN and V TP are 1.369V and 1.912V, respectively, which are the points where the buffer and inverter transfer characteristics intersect. The threshold voltage V TN corresponds to the point where V NO-Buffer and V NO-Inverter intersect and the threshold voltage V TP corresponds to the point where V PO-Buffer and V PO-Inverter intersect. The variation of V TN and V TP due to process variation and temperature effects was determined by simulating a non-inverting input voltage sweep at the process corners using a 3-σ model for process variations. The resulting variations in V TP and V TN are listed in Table 3.3 and the worst-case scenarios where V TN and V TP are closest to each other or to the supply rail voltage levels are shaded. Over 3-σ process variation the TGL works correctly; at no point does V TN become greater than V TP and turn off both transmission gates. Furthermore, at no point does V TP become larger than 2.3V and at no point does V TN become smaller than 1.V. 3

42 In the next chapter the comparator is simulated and validated for the 8-bit SAR-ADC. Simulations are done to confirm the input-offset voltage, output voltage range, and propagation delay. Parallel-Folded-Cascode Amplifier Input Stage V + + P-tail V PO - Transmission Gate Logic Stage VPRE-BUFF V OUT + V NO V - - N-tail Figure 3.1 Proposed Comparator Block-Level Topology Table 3.1 Folded-Cascode Differential Amplifier Channel Dimensions, Terminal Voltages and Drain Currents a) P-Tail Configuration Component Transistor W (µm) 31 L (µm) V DS (V) V GS (V) PMOS Tail Current Source m PMOS Diff. Amp. Input m2,m PMOS Wilson Current Mirror m4 to m Diode 2 NMOS Cascode m8,m NMOS Biasing Current Source m1,m Component b) N-Tail Configuration Transistor W (µm) L (µm) V DS (V) V GS (V) NMOS Tail Current Source m NMOS Diff. Amp. Input m13,m NMOS Wilson Current Mirror m15 to m18 V G (V) V G (V) I D (µa) I D (µa) Diode 16 PMOS Cascode m19,m PMOS Biasing Current Source m21,m

43 V DD V G-m1 m1 m4 m5 V- m2 m3 V+ m6 m7 V PO m8 m9 V G-m8,m9 V G-m1,m11 m1 m11 GND a) V DD m22 m21 V G-m19,m2 V G-m21,m22 m2 m19 V- V+ m14 m13 m18 m17 V G-m12 m12 m16 m15 GND b) Figure 3.2 Folded-Cascode Differential Amplifier a) P-tail Configuration b) N-tail Configuration 32

44 START Step 1. Select Drain Currents Step 2. Design Wilson Current Mirror Step 3. Design NMOS Biasing Current Source Step 4. Design NMOS Cascode Step 5. Design Tail Current Source Step 6. Design Differential Amplifier Input FINISH Step 1. Select ALL Drain Currents FINISH Step 2. Select VD-m6,m7=VPO=1/2VDD Select VDS-m4 to m7=1/4vdd Select W and L such that m4 to m7 produce selected drain current from Step 1. FINISH Step 3. Select L of m1, m11 Select W of m1, m11 Assume VDS-m1,m11=1/4VDD Plot ID vs VGS to find VG-ZTC Calculate VDS-m1,m11=1.5 VOV using initial VG-ZTC Plot ID vs VGS to find VG-ZTC Use new VDS-m1, m11 Does ID-ZTC=ID-m1,m11 from Step 1? YES ZTC operation has been achieved! FINISH NO Step 4. Step 5. Calculate Select VDS-m8,m9 VDS-m1=1/4VDD Select L of m8,m9 Select L of m1 Select W of m8,m9 Select W of m1 Plot ID vs VGS to find VG-ZTC Plot ID vs VGS to find VG-ZTC Does ID-ZTC=ID-m8,m9 from Step 1? Does ID-ZTC=ID-m1 NO NO from Step 1? ZTC operation has been achieved! YES YES ZTC operation has been achieved! FINISH FINISH Step 6. Select VG-m2,m3=V+=V-=1/2VDD Calculate VDS-m2,m3 Select W and L such that m2 and m3 produce selected drain current from Step 1. FINISH Figure 3.3 Folded-Cascode Differential Amplifier Design Flow 33

45 I D ( A) I D ( A) C 75C 125C Device: m1 and m11 V DS-m1,m11 =.825V W=57.5 m L=5 m Drain Current at ZTC Operation Gate Bias 5 (73 A) Voltage at ZTC Operation (1.55V) V GS (V) a) C 75C 125C Device: m1 and m11 V DS-m1,m11 =.42V W=57.5 m L=5 m Gate Bias 5 Drain Current at ZTC Operation Voltage at (6 A) ZTC Operation (1.25V) V GS (V) b) Figure 3.4 Effect of Drain-to-Source Voltage on Gate Bias Voltage for ZTC Operation a) Initial V DS Simulation b) V DS = V OV Simulation V DD V BIAS GND Figure 3.5 Bias Generation Circuit 34