STATISTICAL MODELING FOR COMPUTER-AIDED DESIGN OF MOS VLSI CIRCUITS

Transcription

1 STATISTICAL MODELING FOR COMPUTER-AIDED DESIGN OF MOS VLSI CIRCUITS

2 THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE ANALOG CIRCUITS AND SIGNAL PROCESSING Consulting Editor Related titles: Mohammed Ismail Ohio State University ANALOG CMOS FILTERS FOR VERY HIGH FREQUENCIES, Bram Nauta ISBN: ANALOG VISI NEURAL NETWORKS, Yoshiyasu Takefuji ISBN: INTRODUCTION TO THE DESIGN OF TRANSCONDUCTOR-CAPACITOR FILTERS, Jaime Kardontchik ISBN: VISI DESIGN OF NEURAL NETWORKS, Ulrich Ramacher, Ulrich Ruckert ISBN: LOW-NOISE WIDE-BAND AMPliFIERS IN BIPOlAR AND CMOS TECHNOLOGIES, Z. Y. Chang, Willy Sansen ISBN: ANALOG INTEGRATED CIRCUITS FOR COMMUNICATIONS: Principles, Simulation and Design, Donald o. Pederson, Kartikeya Mayaram ISBN: X SYMBOliC ANALYSIS FOR AUTOMATED DESIGN OF ANALOG INTEGRATED CIRCUITS, Georges Gielen, Willy Sansen ISBN: AN INTRODUCTION TO ANALOG VISI DESIGN AUTOMATION, Mohammed Ismail, Jose Franca ISBN: STEADY-STATE METHODS FOR SIMULATING ANALOG AND MICROWAVE CIRCUITS, Kenneth S. Kundert, Jacob White,Alberto Sangiovanni-Vincentelli ISBN: MIXED-MODE SIMULATION: Algorithms and Implementation, Reseve A. Saleh, A. Richard Newton ISBN: ANALOG VISI IMPLEMENTATION OF NEURAL NETWORKS, Carver A. Mead, Mohammed Ismail ISBN: SELECTIVE linear-phase SWITCHED-CAPACITOR AND DIGITAL FILTERS, Hussein Baher ISBN:

3 STATISTICAL MODELING FOR COMPUTER-AlDED DESIGN OF MOS VLSI CIRCillTS by Christollher Michael National Semiconductor Mohammed Ismail Ohio State University " ~. SPRINGER SCIENCE+BUSINESS MEDIA, LLC

4 Library of Congress Cataloging tn Publication Data Michael, Christopher. Statistical modeling for computer-aided design of MOS VLSI circuits / by Christopher Michael, Mohammed Ismail. p. cm. -- (The Kluwer international series in engineering and computer science. Analog circuits and signal processing) Includes bibliographical references and index. ISBN ISBN (ebook) DOI / Metal oxide semiconductors--design and construction -Statistical methods--data processing. 2. Metal oxide semiconductors--mathematical models. 3. Integrated circuits--very large scale integration--desin and construction--data processing. 4. Integrated circuits--very large scale integration--mathematical models. 5. Computer-aided design. I. Ismail, Mohammed. II. Title. III. Series. TK M44M ' 5--dc CIP Copyright 1993 Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 1993 Softcover reprint ofthe hardcover Ist edition 1993 AII rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, record ing, or otherwise, without the prior written permission of the publisher, Springer Science+ Business Media, LLC. Printed on acid-free pa per.

5 CONTENTS LIST OF FIGURES LIST OF TABLES PREFACE CHAPTER i x xiii xv PAGE 1. Introduction Research Focus Significance of Research 3 2. Survey of Statistical Modeling and Simulation Techniques Statistical Parameter Modeling Parameter Variance Models for MOS Device Mismatch Critique of Statistical MOS Models Statistical Simulation Device-Oriented Statistical Simulation Process-Oriented Statistical Simulation Critique of Statistical Simulation Tools Statistical MOS Model Modeling Obstacles Parameter Mismatch Variance Model Local Parameter Variations Global Parameter Variations Final Parameter Mismatch Variance Model Distance Dependence of Parameter Variance The Coordinate Method a-space Analysis Comparison of asa and Coordinate Method Parameter Correlations: Principal Component Analysis PCA Calculation Procedure PCA Calculation Program Properties of PCA 36

6 vi Statistical Modeling for CAD of MOS VLSI Circuits 3.5 Model Integration: Statistical Parameter Model Model Calculation Procedure 3.6 Model Calculation Example Statistics for Model Calculations Model Calculation Procedure Model Calculation Results 4. Experimental Process Characterization for MOS Statistical Model 4.1 TheBSIMModel 4.2 BSIM Parameter Extraction Test Environment Extraction Accuracy and Repeatability 4.3 Test Chip Description Test Structures Measurement of Fitting Constants N-Channel Test Chip P-Channel Test Chip 4.4 Process Characterization Data Characterization of Full CMOS Process Intra-Die Model Data Inter-Die Model Data 5. CAD Implementation of the SMOS Model 5.1 APLAC - An Object-Oriented Circuit Simulator Description of APLAC 5.2 Simulation Framework 5.3 Model Calculation Programs.(MCPs) SPICE Implementation of SMOS APLAC Implementation of SMOS 5.4 Measurement and Simulation of Test Circuits Measurement of Circuit Output Variance Simulation of Circuit Output Variance (;. Statistical CAD of Analog MOS Circuits. 6.1 Basic Analog Sub-Circuits Mismatch in General Transistor Pair The Current Mirror The Differential Pair 6.2 Operational Amplifier Statistical Simulation of an Op-Amp Statistical Optimization of an Op-Amp Applications of the SMOS Model to Digital Integrated Circuits Introduction CMOS Inverter 124

7 Contents vii Noise Margin Inverter Delay Time 7.3 Dynamic Sense Amplifier Qualitative Overview of Sense Amplifier Analytical Solution. 8. Conclusion and Future Work 8.1 Potential Uses for the SMOS Model APPENDIX PAGE A B MCP - SPICE Implementation of SMOS APLAC Input Files BIBLIOGRAPHY 179 INDEX 189

8 LIST OF FIGURES FIGURES PAGE 1. Separation of device variability into five levels: process, lot, wafer, die, and intra-die 6 2. Nonnalized densities for inter- and intra-die parameter standard deviations 7 3. Device geometry and placement for derivation of parameter variance due to local parameter variations. Origin is at the center of Ml Sample contour map for polysilicon line-width Device geometry and placement for derivation of parameter variance due to global parameter variations. Origin is at the center of M Density of parameter mismatch for global parameter variations. Examples of.6p for different directions of parameter increase are shown Examples of a-space for a three transistor circuit Fortran program containing IMSL subroutines which perform Principal Component Analysis Output of Principal Component Analysis program Scatter plot of flat-band voltage (VFB) and substrate factor (Kl) for W/L=3/2 ~/~ devices Model Calculation framework Circuit layout for model calculation example. The layout includes device areas and separation distances. The numbers in parentheses correspond to the coordinates of the MOSFET centroid in Jlm Primary BSIM parameters Parameter extraction system hardware 54

9 x Statistical Modeling for CAD of MOS VLSI Circuits 15. Example of extracted and actual 10-V 0 curves for a W /L=25/1.5 J.lm/J.Ull (a) n-channel MOSFET and (b) p-channel MOSFET Rotated transistor pairs Four-transistor column with available mismatch data Test structure consisting of two orthogonal four-transistor columns. Arrows indicate direction of drain Mismatch in flat-band voltage in W/L=20/4 J.Ull/J.Ull devices at three different separation distances Current mirror circuit contained in the n-channel test chip Contents of one transistor group on the n-channel test chip Physical layout of the n-channel test chip Contents of one transistor group on the p-channel test chip Physical layout of the p-channel test chip Correlation matrix for n-channel MOSFETs using the BSIM model Correlation matrix for p-channel MOSFETs using the BSIM model Area dependence of parameter mismatch for two BSIM model parameters, (a) flat-band voltage and (b) saturation region mobility, for n-channel MOSFETs. Dots are measured values and the line is a fit to the data. 28. Area dependence of parameter mismatch for two BSIM model parameters, (a) flat-band voltage and (b) saturation region mobility, for p-channel MOSFETs. Dots are measured values and the line is a fit to the data Separation distance dependence of parameter mismatch for two BSIM parameters, (a) flat-band voltage and (b) saturation region mobility, for three sizes ofn-channel MOSFETs. Dots are measured values and the line is a fit to the data Inter-die parameter correlation matrix for n-well MOSIS process using the BSIM model Simulation flow chart Block diagram of the model calculation program, SPICE implementation 90 n

10 List of Figures xi 33. Sample input file to the SPICE implementation of the model calculation program BSIM model me for n-channel MOSFETs in the 2 Ilm n-well MOSIS process BSIM model me for p-channel MOSFETs in the 2 jlm n-well MOSIS process Sample output me of SPICE implementation of the model calculation program Block diagram of the model calculation program. APLAC implementation Sample APLAC input me for current mirror circuit including "SMOS" object Mismatch in mirrored current for W /L = 20/4 jlm/jlm devices at three different device separation distances. Reference current is 50 1lA General matched transistor pair showing parameter and bias mismatches The current mirror Simulated device area and separation distance dependence of current mirror circuit All simulations performed at ISS=50 IlA and W/L= Simulated bias dependence of current mirror circuit All simulations performed for device areas of 80 Ilm2 and at minimum separation distances The differential pair with resistive load The differential pair with current mirror load Simulated device area and separation distance dependence of differential pair circuit Simulated bias dependence of differential pair circuit Operational Amplifier Circuit Probability density functions for a sample circuit performance criterion Flow chart for statistical circuit optimization 119

11 xii Statistical Modeling for CAD of MOS VLSI Circuits 51. Standard CMOS Inverter DC Transfer Characteristic of CMOS Inverter Step Response of a CMOS Inverter CMOS Inverter Transient Response using BSIM Model NMOS Dynamic Sense Amplifier Sense Amplifier Latch Optimum Latching Wavefonn and Piecewise Linear Approximation Sense Amplifier Latch with Levell MOS Model Standard Deviation of Amplifier Sensitivity 153

12 LIST OF TABLES TABLE PAGE 1. Statistical fitting constants for model calculation example Correlation matrix for model calculation example Calculated "A" matrix values for model calculation example using a-space Analysis Parameter means and correlations of calculated model decks Intta-die parameter variances of calculated model decks Repeatability of extracted parameters for a W 1L=20/l J.lIllIJ..I.Ol device Fitting constants of mean and variance models for n-channel transistors in a 2 J..I.Ol n-well process. Units column refers to J.IO terms. Other fitting constants have units described by the final row Fitting constants of mean and variance models for p"channel transistors in a 2 J..I.Ol n-well process. Units column refers to J.IO terms. Other fitting constants have units described by the final row PCA Coefficients from inter-die correlation matrix Inter-die parameter means and standard deviations for W/L = 3/l J..I.Ol/J..l.Ol oovices Measured and simulated current mismatch of current mirror circuit for three ttansistor sizes at three different separation distances under three different biases. Measured data found from n-channel test chip Op-amp Characteristics before and after nominal optimization Transistor dimensions before and after nominal circuit optimization. the numbers in parentheses refer to transistor numbers provided through Figure

13 xiv Statistical Modeling for CAD of MOS VLSI Circuits 14. Simulated op-amp characteristics at different device areas: (a) DC gain, gain-bandwidth, and slew rate (b) gain margin, phase margin, and offset voltage. All aspect ratios are held constant at values provided in the "after optimization" column of Table Op-amp statistical optimization results. Optimized values for device area coefficients, device aspect ratios, and circuit performance criteria for four different offset voltage tolerances Simulated Noise Margin Variances: Interdie Case Simulated Noise Margin Variances: Intradie Case Simulated Delay Time Variances: Interdie Case 144

14 PREFACE As MOS devices are scaled to meet increasingly demanding circuit specifications, process variations have a greater effect on the reliability of circuit performance. For this reason, statistical techniques are required in order to design integrated circuits with maximum yield. This book describes a statistical circuit simulation and optimization environment for VLSI circuit designers. The first step toward accomplishing statistical circuit design and optimization is the development of an accurate CAD tool capable of performing statistical simulation. This tool must be based on a statistical model which comprehends the effect of device and circuit characteristics, such as device size, bias, and circuit layout, which are under the control of the circuit designer on the variability of circuit performance. The distinctive feature of the CAD tool described in this book is its ability to accurately model and simulate the effect of both intra- and inter-die process variability on analog/digital circuits, accounting for the effects of the aforementioned device and circuit characteristics. Previous books in this area have focused either on MOSFET modeling, ignoring the effect of process variability, or on modeling the process variability itself. Chapter 3 describes a general, parameter-level statistical model, called SMOS (Statistical MOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device area, bias, and circuit layout. Chapter 4 details a procedure to tune the statistical model to a given fabrication process. Test structures, designed to allow easy determination of fitting constants for both the area and separation distance mismatch components, are presented along with measurement procedures. This chapter also examines experimental issues, such as repeatable parameter extraction, in the measurement of device mismatch from these test structures. A complete set of intra- and inter-die data, required to perform model calculations with the SMOS model, is included for one MOSIS process. Chapter 5 examines the implementation of the SMOS model in two existing circuit simulators, SPICE and APLAC. In these CAD environments, the statistical model provides the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Experimental and simulation results for a current mirror are compared to verify both the statistical modeling algorithms and the SMOS implementations.

15 xvi Statistical Modeling for CAD of MOS VLSI Circuits Chapter 6 is devoted to the statistical analysis, simulation, and optimization of analog MOS integrated circuits. Two basic analog sub-circuits, the current mirror and the source-coupled pair, are analyzed and simulated to determine the effects of device area, layout, and bias on circuit performance. A basic, Miller-compensated operational amplifier is then optimized to meet nominal as well as yield specifications. Chapter 7, written by Christopher J. Abel, examines the effect of parameter variations on digital integrated circuits. The effect of process variations on the noise margins and delay time of a CMOS inverter are both calculated and simulated using the SMOS model. Then, a sense amplifier is examined to determine its sensitivity to parameter mismatch.

16 STATISTICAL MODELING FOR COMPUTER-AIDED DESIGN OF MOS VLSI CIRCUITS