INTEGRATED CIRCUIT DEFECT-SENSITIVITY: THEORY AND COMPUTATIONAL MODELS

Transcription

1 INTEGRATED CIRCUIT DEFECT-SENSITIVITY: THEORY AND COMPUTATIONAL MODELS

2 THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE MICROELECTRONICS MANUFACTURING Consulting Editor Arjun N. Saxena Rensselaer Polytechnic Institute

3 INTEGRATED CIRCUIT DEFECT-SENSITIVITY: THEORY AND COMPUTATIONAL MODELS by Jose Pineda de Gyvez Texas A&M University SPRINGER SCIENCE+BUSINESS MEDIA, LLC

4 Ubrary of Congress Cataloglng-ln-Publication Data Pineda de Gyvez, Jose. lntegrated circuit defect-sensitivity : theory and computational models 1 by Jose Pineda de Gyvez. p. cm. -- (fhe Kluwer international series in engineering and computer science; 208. Microelectronics manufacturing) Includes bibliographical references (p. ) and index. ISBN ISBN (ebook) DOI / Integrated circuits--very large scale integration--design and construction--data processing. 2. Integrated circuits--very large scale integration--defects--mathematical models. 3. Computer-aided design. 1. Title. II. Series: Kluwer international series in engineering and computer science ; SECS 208. III. Series: Kluwer international series in engineering and computer science. Microelectronics manufacturing. TK7874.P dc CIP Copyright 1993 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 1993 Softcover reprint ofthe hardcover 1st edition 1993 Ali rights reserved. No part ofthis publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, record ing, or otherwise, without the prior written permission of the publisher, Springer Science +Business Media, LLC Printed on acid-free paper.

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6 Table of Contents Foreword... Preface Introduction Approaches to Yield Modeling xix xxiii Defect Semantics and Yield Modeling Microelectronics Technology Modeling of Process Induced Defects and Faults Statistical Characterization of Spot Defects Brief Overview of Historical Yield Models Computational Models for Defect-Sensitivity Taxonomy of Defect-Sensitivity Models Theoretical Foundation of Critical Areas Susceptible Sites Critical Regions and Critical Areas Geometrical Proof of the Construction of Critical Regions Single Defect Multiple Layer (SDML) Model Critical Regions for Protrusion Defects

7 Table of Contents viii 4.2 Critical Regions for Isolated Spot Defects Critical Regions for Intrusion Defects A CAD System for SDML Critical Areas A "Spot-Defect" Language Layout Partitioning Extraction of Multi-Layer Susceptible Sites Defect Mechanisms Intrusion Defects Isolated-Spot Defects Protrusion Defects Construction of Multi-Layer Critical Regions Computation of Multi-Layer Critical Areas Notes on Implementation Examples Fault Analysis and Multiple Layer Critical Areas Failure Analysis and Yield Projection of 6T-RAM Cells Fault Weighting Analysis and Weighting of Defect Induced Faults Single Defect Single Layer (SDSL) Model Theory of Critical Regions for SDSL Models Single-Layer Susceptible Sites Critical Regions for Bridges Critical Regions for Cuts Computation of Critical Areas for SDSL Models Extraction of SDSL Susceptible Sites Computation of SDS Critical Areas Complexity Analysis Examples IC Yield Prediction and Single Layer Critical Areas Sensitivity Analysis... III

8 IC Defect Sensitivity 7.9 Yield Arlalysis Single vs. Multiple Layer Critical Areas Uncovered Situations of the SDSL Model Case Study Comparative Results Summary and Discussion References Appendix 1 Sources of Defect Mechanisms Appendix 2 End Effects of Critical Regions Appendix 3 NMOS Technology File Index

9 List of Figures Figure 1. 1 Features in Yield Models... 5 Figure 2.1 A Silicon Layer Structure Figure 2.2 Defect Mechanisms. (a) Intrusion. (b) Protrusion. (c) Isolated Figure 2.3 A "typical" defect size distribution (a) analytical (b) data Figure 2.4 Probability density function for different defect densities Figure 2.5 An area of interest in a wafer Figure 2.6 Defect densities are averaged for a batch of wafers for independent concentric regions Figure 2.7 Layout defect-sensitivity, layout probability of failure, and manufacturing defect size distribution Figure 3.1 Taxonomy of Failure Primitives Figure 3.2 Taxonomy of Defect-Sensitivity Models Figure 3.3 Example of susceptible sites Figure 3.4 (a) Three connected point sets. (b) Corresponding susceptible sites Figure 3.5 Application of the geometrical failure criterion. (a) Three islands equally spaced and with the same width (b) Two bridges with and without the usage of the failure criterion w Figure 3.6 Creation of critical regions from susceptible sites. The corner critical region is created for a defect size of 3 units, the lateral critical region for a defect size of 3.5 units Figure 3.7 Theorem 3.l. (a) Three connected point sets. (b) Critical region Figure 3.8 Theorem 3.3. (a) Three connected point sets and corresponding susceptible sites Ei. (b) Critical regions from the three susceptible sites. (c) Critica] region from susceptible site E I. (d) Critical region from susceptible site E2. (e) Critical region from susceptible site E

10 xii IC Defect Sensitivity Figure 3.9 Theorem 3.5. (a) Three connected point sets with three corner susceptible sites. (b) Corresponding critical regions Figure 3.10 Theorem 3.6. (a) Three connected point sets with three lateral susceptible sites. (b) Corresponding critical regions. 46 Figure 4.1 Three mutually non-intersecting islands Figure 4.2 A multilayer situation is depicted in which three patterns belonging to three different layers are characterized by two distinct islands. (a) a c ~ by Rl(ro) I ~ b. c ~ by R{J.I.) I ~ and. c c Lk by R2(ro) ILk. (b) Some susceptible sites Figure 4.3 Multilayer critical regions for protrusion defects Figure 4.4 Multilayer critical regions for isolated spot defects Figure 4.5 System framework for the computation of critical areas 57 Figure 4.6Syntax of the Spot-Defect Language Figure 4.7 Forming multilayer susceptible sites. (a) Three different masks. (b) Susceptible site for mask A (c) Susceptible site for masks A and B. (d) Susceptible site for masks A and C (e) Susceptible site for masks A. B. and C Figure 4.8 Critical Regions after node and fault splitting Figure 4.9 Static Line Array. (a) Data structure. (b) Insert operation (c) Split-<ielete operation Figure 4.10 Transistor Matrix layout for an NMOS technology Figure 4.11 Critical regions for protrusions and isolated spots of poly Figure 4.12 Protrusion defects of diffusion Figure 4.13 Critical regions for missing thick oxide Figure 4.14 Critical regions for intrusion defects of diffusion Figure T Static RAM. (a) Schematic diagram (b) Layout Figure 5.2 Critical regions for polysilicon defects of 10J.t. (a) Intrusions (b) Protrusions and isolated Figure 5.3 Defect-Sensitivity of the 6-T RAM. (a) Protrusion and isolated defects. (b) Intrusion defects Figure 5.4 Defect-SenSitivity per fault and node. (a) One defect effecting more than one node. (b) More than one defect effecting only one node

11 List of Figures xiii Figure 5.5 Likelihood offailure of the 6-T RAM per layer. (a) Intrusion defects. (b) Protrusion and isolated defects Figure 5.6 I-Bit Adder (a) Layout (b) Schematic diagram Figure 5.7 Critical Areas for a bridge between nodes 8 and C Figure 5.8 Weight Spectrum for the full adder Figure 6. 1 (a) 1\vo active patterns identifying two wiring trees. (b) Susceptible sites for bridges and cuts Figure 6.2 The critical regions for both bridges and cuts are found by shrinking the susceptible sites Figure 6.3 Creation of susceptible sites. BEGIN line segments are at positions P2 and P4; END line segments are at positions PI and P Figure 6.4 Creation of critical regions Figure 6.5 Computation of the area of the union of a set of rectangles Figure 6.6 An active region area with "complex" pattern shapes Figure 6.7 Single-layer susceptible sites for bridges. (a) Vertical sites. (b) Horizontal sites. (c) Corner sites Figure 6.8 Critical regions for bridges Figure 7.1 (a) PIA. (b) TM. (c) SID Figure 7.2 Layout Sensitivity vs. defect size in JlIl1 (BRIDGES) Figure 7.3 Layout Sensitivity vs. defect size in JlIl1 (CUTS) Figure 7.4 Critical Regions for bridges in the metal-2 mask (a) TM 7JlIl1 (b) SID 9JlIl Figure 7.5 Critical regions for cuts (a) TM 7JlIl1 (b) PIA 7JlIl Figure 7.6 Defect Size distribution Figure 7.7 Layout likelihood of failure. (Bridges) Figure 7.8 Layout likelihood of failure (Cuts) Figure 7.9 Yield vs. defect density (BRIDGES) Figure 7.10 Yield vs. defect density (curs) Figure 7.11 Layout yield for metal-1(2l, poly. and active area masks for protrusion and intrusion defects Figure 8.1 Enhancement Transistor. (a) The gate is fully broken. (b) The gate is partially broken Figure 8.2 Creation of a parasitic transistor Figure 8.3 Poly-metal via. (a) Metal wire broken (b) Metal wire partially broken.. 128

12 xiv Ie Defect Sensitivity Figure 8.4 Involuntary via Figure 8.5 Depletion transistor affected by a spot ofmisstng material in its implant layer Figure A 1 End effects of critical regions for protrusion defects. (a) defect size bigger than the space between the patterns. (b) defect size smaller than the space between the patterns

13 List of Tables Table 2.1 Fault Modeling Abstraction Levels Table 2.2 Probability distribution function of defect densities (compounders) and their associated yield models 23 Table 5.1 Yield Projections for a 4K and 40K bit SRAM Table 6. 1 Time Complexity Analysis Table 7. 1 Layout data III Table 8.1 Logic Benchmarks Table 8.2 Sensitivity Analysis - Intrusion Defects Table 8.3 Sensitivity Analysis - Protrusion Defects Table 8.4 Yield Estimation

14 List of Algorithms Algorithm 3.1 Geometrical Construction of Critical Regions.. 40 Algorithm 4.1 Extraction of Susceptible Sites Algorithm 4.2 Creation of Multi-layer Critical Regions Algorithm 4.3 Computation of Multi-layer Critical Areas Algorithm 6.1 Creation of Susceptible Sites for Bridges Algorithm 6.2 Creation of Critical Regions

15 Foreword The history of this book begins way back in At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology- and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders. The market, however, developed its own dynamics. The large ASIC volumes still have not come about and it is more than doubtful that they will ever arrive. Instead specialized companies concentrate on very high performance memories and microprocessors. Prototypes and low volume applications of more specific character tend to be covered by special purpose standard processors, gate arrays and field programmable devices. And while the technology becomes more and more demanding, more and more physical phenomena require the attention of the designer. Standard design rules have at all times been

16 Foreword xx out of consideration for memory designers for reasons of density and yield. But the designers of new high perfonnance processors (like the ALPHA-chip) or sea of gates master patterns are increasingly driven by the same kinds of demands. Yield is a more sensitive parameter than ever. Industry started to obseive the local stochastic phenomena in silicon layer structures under the microscope. The results were considered so significant that at certain sites techniques were developed to measure the statistics of those so called "spot defects" by means of test layout patterns that could be evaluated by standard high volume test and measuring equipment. The new tendencies also affected the attitudes toward testing. The stuck-at fault model had seived as a standard for many years up to the point that questioning it was an indication of a lack of professionality. Yet today some industrial leaders admit that the available defect statistics and some more recent research results suggest that fault coverage predictions based on the stuck-at hypothesis could be many percent off and thus prove to be insufficiently reliable for the new generation of Silicon technologies. New types of fault models like bridging faults or delay faults enter the discussion and fault simulators for these types of faults are in increasing demand. But in order to obtain reliable results measured statistics have to be translated into yield estimates and ranked fault lists. This is what this book is all about. To make a long story short: our proposal experienced a reanimation only three years after its turn down. As a consequence one day in the Fall of 1986 an extremely jet-lagged young man from Puebla. Mexico. knocked at the door of my home and introduced himself as the new PhD student that had to work on defect modeling. His name was Jose Pineda de Gyvez. In the years to follow this very talented and active person developed a whole line of research activities in the laboratories of Eindhoven University. The work found recognition in Philips LaboratOries next door as well as in many other places all over the world. He made that my group could contribute to the ESPRIT EVEREST project of the Commission of the European Communities.

17 xxi Ie Defect Sensitivity In his book Jose Pineda describes dominantly original work from his own research which is fundamental and unique and will undoubtedly set a new pace in this field. Designers have to understand the concepts in order to stay competitive on the long run. Students should pay attention to this material. because there is still a lot of work to do. At various schools defect analysis already enters the first and second level design courses. As happened in the past so many times design technology again seems to add another fundamentally new chapter to its encyclopedia. I wish the book the attention it deselves. Jochen A. G. Jess Eindhoven. The Netherlands August

18 Preface This monograph is an introduction to the field of spot defect modeling in Integrated Circuits and its applications to fault and yield prediction. The contents has a compromise between CAD and analytical formulae, as these two topics are combined to effectively obtain more accurate results. Broadly speaking, the CAD contrtbution presents algortthms for the extraction of "crttical areas" from complex layouts, while the analytical part is concerned with the application of yield formulae and fault weighting techniques. As it will be seen, the applications of critical areas exist not only in yield prediction but also in areas such as layout verification, defect tolerant routers, manufacturing fault modeling, fault weighting and ranking, etc. The monograph is meant as a reference text for practitioners in the areas of defect tolerant VLSI design, manufacturing-based testing, yield estimation, and CAD for manufacturabu1ty. The text provides foundations on detailed computational models which are of interest to CAD practitioners, and also highlights methods by which the IC defect-sensitivity is used in typical situations for yield and fault prediction. To be more explicit, chapters 4 and 6 present deterministic algortthms for the extraction of critical areas, and chapters 5 and 7 present case-studies of layout analyses for fault and yield prediction, taking into account the environmental conditions of the manufacturing line. Chapter 2 covers the physical characterization of defects such as defect size distribution and defect density as well as a brtef overview of yield modeling and its relation to crttical areas. This chapter starts by

19 xxiv Ie Defect Sensitivity introducing formal definitions for technology. defect. and fault semantics to unite terminology and concepts worked out through the book. Instead ot: developing only mathematical models for yield analysis. the work develops rigorously a theory on critical areas related to both design layout and to variabilities in the manufacturing process. This theory. presented in chapter 3. is developed in a context of computational geometry and topology set theory to have a mathematical basis in developing the algorithms for layout verification presented in chapters 4 and 6. Although the material is quite abstract it "touches ground" with the experiments presented in subsequent chapters. Finally. I would like to mention that the work discussed in this book has been influenced greatly by the support of the Design Automation Group in the Technological University of Eindhoven. The Netherlands. I would also like to acknowledge the financial support of the Foundation for Fundamental Research on Matter. The Netherlands. Lastly. the algorithms described in the book were implemented in several software packages under UNIX and X environments. These packages are available for public domain and can be requested directly from the author.