CMOS LOGIC CIRCUIT DESIGN

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1 CMOS LOGIC CIRCUIT DESIGN

2 CMOS LOGIC CIRCUIT DESIGN John P. Uyemura Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

3 ebook ISBN: Print ISBN: Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print 2001 Kluwer Academic Publishers Dordrecht All rights reserved No part of this ebook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's ebookstore at:

4 Dedication This book is dedicated to Christine and Valerie for all of the joy and happiness that they bring into my life

5 Preface This book is based on the earlier Kluwer title Circuit Design for CMOS/VLSI which was published in At that time, CMOS was just entering the mainstream as a technique for high-speed, high-density logic circuits. Although the technology had been invented in the 1960 s, it was still necessary to include Section 1.1 entitled Why CMOS? to justify a book on the subject. Since that time, CMOS has matured and taken its place as the primary technology for VLSI and ULSI digital circuits. It therefore seemed appropriate to update the book and generate a second edition. Background of the Book After loading the old files and studying the content of the earlier book, it became clear to me that the field is much more stable and well-defined than it was in the early 1990 s. True, technological advances continue to make CMOS better and better, but the general foundations of modern digital circuit design have not changed much in the past few years. New logic circuit techniques appearing in the literature are based on well-established ideas, indicating that CMOS has matured. As a result of this observation, the great majority of the old files were abandoned and replaced with expanded discussions and new topics, and the book was reorganized to the form described below. There are sections that didn t change much. For example, Chapter 1 (which introduces MOSFETs) includes more derivations and pedagogical material, but the theme is about the same. But, many items are significantly different. For example, the earlier book contained about 60 pages on dynamic logic circuits. The present volume has almost three times the number of pages dedicated to this important area. In addition, the book has been written with more of a textbook flavor and includes problem sets. Contents Chapter 1 introduces the MOS system and uses the gradual-channel approximation to derive the square-law equations and basic FET models. This sets the notation for the rest of the book. Bulkcharge models are also discussed, and the last part of the chapter introduces topics from smalldevice theory, such as scaling and hot electrons.

6 viii Chapter 2 is an overview of silicon fabrication and topics relevant to a CMOS process flow. Basic ideas in lithography and pattern transfer are covered, as are items such as design rules, FET sizing, isolation, and latch-up. This chapter can be skipped in a first reading, but it is important to understanding some problems that are specific to layout and fabrication issues. It is not meant to replace a dedicated course in the subject. Circuit design starts in Chapter 3, which is a detailed analysis of the static CMOS inverter. The study is used to set the stage for all of the remaining chapters by defining important DC quantities, transient times, and introducing CMOS circuit analysis techniques. Chapter 4 concentrates on a detailed study of the electrical characteristics of FETs when used as voltage-controlled electronic switches. In particular, the treatment is structured to emphasize the strong and weak points of nfets and pfets, and how both are used to create logic networks. This feeds into Chapter 5, which is devoted entirely to static logic gates. This includes fully complementary designs in addition to variants such as pseudo-nmos circuits and novel XOR/XNOR networks. Chapter 6 on transmission gate logic completes this part of the book. Dynamic circuit concepts are introduced in Chapter 7. This chapter includes topics such as charge sharing and charge leakage in various types of CMOS circuit arrangements. RC modelling is introduced, and the Elmore formulas for the time constant of an RC ladder is derived. Clocks are introduced and used in various types of clocked static and dynamic circuits. Dynamic logic families are presented in Chapter 8. The discussion includes detailed treatments of precharge/evaluate ripple logic, domino logic cascades, self-resetting logic gates, single-phase circuits and others. I have tried to present the material in an order that demonstrates how the techniques were developed to solve specific problems. Chapter 9 deals with differential dual-rail logic families such as CVSL and CPL with short overviews of related design styles. The material in Chapter 10 is concerned with selected topics in chip design, such as interconnect modelling and delays, crosstalk, BSD-protected input circuits, and the effects of transmission lines on output drivers. The level of the presentation in this chapter is reasonably high, but the topics are complex enough so that the discussions only graze the surface. It would take another volume (at least) to do justice to these problems. As such, the chapter was included to serve as an introduction for other courses or readings. Use as a Text There is more than enough material in the book for a 1-semester or 2-quarter sequence at the senior undergraduate or the first-year graduate level. The text itself is structured around a first-year graduate course entitled Digital MOS Integrated Circuits that is taught at Georgia Tech every year. The course culminates with each student completing an individual design project. My objectives in developing the course material are two-fold. First, I want the students to be able to read relevant articles in the IEEE Journal of Solid-State Circuits with a reasonable level of comprehension by the end of the course. The second objective is more pragmatic. I attempt to structure the content and depth of the presentation to the point where the students can answer all of the questions posed in their job interviews and plant visits, and secure positions as chip designers after graduation. Moreover, I try to merge basics with current design techniques so that they can function in their positions with only a minimum amount of start-up time. Problem sets have been provided at the end of every chapter (except Chapter 2). The questions are based on the material emphasized in the chapter, and most of them are calculational in nature. Process parameters have been provided, but these can easily be replaced by different sets that might be of special interest. Most of the problems have appeared on my homeworks or exams; others are questions that I wrote, but never got around to using for one reason or another. I have tried to include a reasonable number of problems without getting excessive. Students that can follow the level of detail used in the book should not have many problems applying the material. SPICE simulations add a lot to understanding, and should be performed whenever possible.

ix Apologies No effort was made to include a detailed list of references in the final version of the book. I initially set out to compile a comprehensive bibliography.

7 ix Apologies No effort was made to include a detailed list of references in the final version of the book. I initially set out to compile a comprehensive bibliography. However, after several graduate students performed on-line literature searches that yielded results far more complete than my list, I decided to include only a minimal set here. The references that were chosen are books and a few papers whose contents are directly referenced in the writing. The task is thus left to the interested reader. I have tried very hard to eliminate the errors in the book, but realize that many will slip through. After completing six readings of the final manuscript, I think that I caught most of the major errors and hope that the remaining ones are relatively minor in nature. I apologize in advance for those I missed. Acknowledgments Many thanks are due to Carl Harris of Kluwer who has shown amazing patience in waiting for this project to be completed. He never seemed to lose hope, even when I was quite ill (and crabby) for several months and unable to do much. Of course, those who know Carl will agree with me that he is a true gentlemen with exceptional qualities. And a real nice guy. Dr. Roger P. Webb, Chair of the School of Electrical & Computer Engineering at Georgia Tech, has always supported my efforts in writing, and has my never ending thanks. Dr. William (Bill) Sayle, Vice-Chair for ECE Undergraduate Affairs, has also helped me more times than I can count during the many years we have known each other. I am grateful to my colleagues that have taken the time to discuss technical items with me. On the current project, this includes Dr. Glenn S. Smith, Dr. Andrew F. Peterson, and Dr. David R. Hertling in particular. I am grateful to the reviewers that took the time to weed through early versions of the manuscript that were full of typos, missing figures, and incomplete sections to give me their comments. Feedback from the many students and former students that have suffered through the course have helped shape the contents and presentation. Finally, I would like to thank my wife Melba and my daughters Valerie and Christine that have put up with dad sitting in front of the computer for hours and hours and hours. Their love has kept me going through this project and life in general! John P. Uyemura Smyrna, Georgia

8 Table of Contents Preface Table of Contents vii xi Chapter 1 Physics and Modelling of MOSFETs Basic MOSFET Characteristics The MOS Threshold Voltage Body Bias Current-Voltage Characteristics Square-Law Model Bulk-Charge Model The Role of Simple Device Models p-channel MOSFETs MOSFET Modelling Drain-Source Resistance MOSFET Capacitances Junction Leakage Currents Applications to Circuit Design Geometric Scaling Theory Full-Voltage Scaling Constant-Voltage Scaling Second-Order Scaling Effects Applications of Scaling Theory Small-Device Effects Threshold Voltage Modifications Mobility Variations 50 Hot Electrons Small Device Model MOSFET Modelling in SPICE Basic MOSFET Model 56

9 xii 1.9 Problems References 59 Chapter 2 Fabrication and Layout of CMOS Integrated Circuits Overview of Integrated Circuit Processing Oxides 61 Polysilicon 63 Doping and Ion Implantation 64 Metal Layers Photolithography The Self-Aligned MOSFET The LDD MOSFET Isolation and Wells LOCOS Improved LOCOS Process Trench Isolation The CMOS Process Flow Silicide Structures 83 Other Bulk Technologies Mask Design and Layout MOSFET Dimensions 88 Design Rules 90 Types of Design Rules 90 General Comments 94 Latch-Up Latch up Prevention Defects and Yield Considerations Other Failure Modes Chapter Summary References

10 xiii Chapter 3 The CMOS Inverter: Analysis and Design Basic Circuit and DC Operation DC Characteristics Noise Margins Layout Considerations Inverter Switching Characteristics Switching Intervals High-to-Low Time Low-to-High Time Maximum Switching Frequency Transient Effects on the VTC RC Modelling Propagation Delay Use of the Step-Input Waveform Output Capacitance Inverter Design DC Design 134 Transient Design 137 Power Dissipation Driving Large Capacitive Loads Problems References Chapter 4 Switching Properties of MOSFETs nfet Pass Transistors Logic 1 Input Logic 0 Input Switching Times Interpretation of the Results Layout 161 pmos Transmission Characteristics Logic 0 Input

11 xiv Logic 1 Input Switching Times 165 The Inverter Revisited Series-Connected MOSFETs nfet Chains pfet Chains FETs Driving Other FETs Transient Modelling The MOSFET RC Model 171 Voltage Decay On an RC Ladder 173 MOSFET Switch Logic Multiplexor Networks 186 Problems Chapter 5 Static Logic Gates Complex Logic Functions CMOS NAND Gate DC Characteristics Transient Characteristics Design N-Input NAND CMOS NOR Gate DC Transfer Characteristic Transient Times Design N-Input NOR Comparison of NAND and NOR Gates Layout Complex Logic Gates Examples of Complex Logic Gates 217 Logic Design Techniques 219 FET Sizing and Transient Design Exclusive OR and Equivalence Gates Mirror Circuits 226 Adder Circuits 230 SR and D-type Latch 232 The CMOS SRAM Cell 234

12 5.8.1 Receiver Latch Schmitt Trigger Circuits Tri-State Output Circuits Pseudo-nMOS Logic Gates Complex Logic in Pseudo-nMOS Simplified XNOR Gate 251 Compact XOR and Equivalence Gates 253 Problems 256 xv Chapter 6 Transmission Gate Logic Circuits Basic Structure The TG as a Tri-State Controller Electrical Analysis Logic 1 Transfer 263 Logic 0 Transfer RC Modelling TG Resistance Estimate Equivalent Resistance TG Capacitances Layout Considerations TG-Based Switch Logic Gates Basic Multiplexors 272 OR Gate 273 XOR and Equivalence 274 Transmission-gate Adders 276 TG Registers The D-type Flip-Flop nfet-based Storage Circuits Transmission Gates in Modern Design Problems

13 xvi Chapter 7 Dynamic Logic Circuit Concepts Charge Leakage Junction Reverse Leakage Currents Charge Leakage Analysis Subthreshold Leakage pfet Leakage Characteristics Junction Leakage in TGs Charge Sharing RC Equivalent The Dynamic RAM Cell Cell Design and Array Architecture 314 DRAM Overhead Circuits Bootstrapping and Charge Pumps Physics of Bootstrapping Bootstrapped AND Circuit Clocks and Synchronization Shift Register 327 TGs as Control Elements 330 Extension to General Clocked Systems 330 Clocked-CMOS Clock Generation Circuits Summary Comments Problems Chapter 8 CMOS Dynamic Logic Families Basic Philosophy Precharge/Evaluate Logic NAND3 Analysis Dynamic nmos Gate Examples nmos-nmos Cascades Dynamic pmos Logic nmos-pmos Alternating Cascades

14 8.3 Domino Logic Gate Characteristics Domino Cascades Charge Sharing and Charge Leakage Problems Sizing of MOSFET Chains High-Speed Cascades Multiple-Output Domino Logic Charge Sharing and Charge Leakage 395 Carry Look-Ahead (CLA) Adder Self-Resetting Logic NORA Logic NORA Series-Parallel Multiplier Single-Phase Logic 8.8 An Overview of Dynamic Logic Families 8.9 Problems 8.10 References xvii Chapter 9 CMOS Differential Logic Families Dual Rail Logic Cascode Voltage Switch Logic (CVSL) The pfet Latch CVSL Buffer/Inverter nfet Switching Network Design Switching Speeds Logic Chains in CVSL Dynamic CVSL Variations on CVSL Logic Sample-Set Differential Logic (SSDL) ECDL DCSL Complementary Pass-Transistor Logic (CPL) Input Arrays Input Arrays 459 CPL Full-Adder Dual Pass-Transistor Logic (DPL) 462

15 xviii Summary of Differential Design Styles Single/Dual Rail Conversion Circuits Single-to-Dual Rail Conversion Dual-to-Single Rail Conversion A Basic Current Source 472 Problems References Chapter 10 Issues in Chip Design On-Chip Interconnects Line Parasitics 477 Modelling of the Interconnect Line Clock Distribution Coupling Capacitors and Crosstalk Input and Output Circuits Input Protection Networks 498 Output Circuits Transmission Lines Ideal Transmission Line Analysis Reflections and Matching Problems 10.5 References Index 525

16 CMOS LOGIC CIRCUIT DESIGN

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation