VALLIAMMAI ENGINEERING COLLEGE

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VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK VI SEMESTER EC6601 VLSI Design Regulation 2013

1 VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK VI SEMESTER EC6601 VLSI Design Regulation 2013 Academic Year Prepared by Dr. Usha Bhanu. N, Associate Professor/ECE Mr. S. Senthilmurugan, Assistant Professor/ECE Mr. C.Saravanakumar, Assistant Professor/ECE Page 1 of 12

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203.

2 VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT : EC6601 VLSI Design SEMESTER/YEAR : VI / III UNIT I MOS TRANSISTOR PRINCIPLE NMOS and PMOS transistors, Process parameters for MOS and CMOS, Electrical properties of CMOS circuits and device modelling, Scaling principles and fundamental limits, CMOS inverter scaling, propagation delays, Stick diagram, Layout diagrams. Q. No Questions PART - A BT Level Competence 1. What is the need for demarcation line? 2. Compare NMOS and PMOS transistor. 3. Define propagation delay of CMOS inverter. 4. Mention the different types of scaling technique. 5. Why NMOS transistor is selected as pull down transistor? 6. Describe the lambda based design rules used for layout. 7. What is stick diagram? Sketch the stick diagram for 2 input NAND gate. 8. Explain the hot carrier effect. 9. Draw the DC transfer characteristics of CMOS inverter. 10. Name the different operating modes of transistor? 11. Classify SPICE models for MOS transistor. 12. What are the steps involved in IC fabrication? 13. Discuss the limitations of the constant voltage scaling. 14. Define body effect and write the threshold equation including the body 15. Design a 3 input NAND gate. 16. List out second order effects of MOS transistor Determine whether an NMOS transistor with a threshold voltage of 0.7v is operating in the saturation region if GSV=2v and DSV=3v. Summarize the equation for describing the channel length modulation effect in NMOS transistor. Why the tunneling current is higher for NMOS transistors than PMOS transistors with silica gate? Consider the NMOS transistor in 180nm process with a nominal threshold voltage of 0.4v and doping level of 8x10 17 cm -3. Propose the body voltage. Page 2 of 12

3 PART - B 1. Illustrate with necessary diagrams Electrical properties of MOS transistor in detail. (13) 2. Describe the CMOS inverter and Derive the DC characteristics. (13) 3. Narrate in detail about ideal I-V characteristics and non-ideal I-V characteristics of NMOS and PMOS devices. (13) 4. i) Derive the drain current of MOS device in different operating regions. (8) ii) With neat diagram formulate the n-well and channel formation in CMOS process. (5) 5. Mention in detail about second order effects in MOS transistor. (13) 6. Summarize the following: i) CMOS process enhancements (8) ii) Layout design rules. (5) 7. i) Examine the equation for threshold voltage of a MOS transistor in terms of flat band voltage using necessary explanations and derivations. (8) ii) State the step by step derivation of threshold voltage equation of NMOS transistor with and without body effect. (5) 8. i) An NMOS transistor has the following parameters: gate oxide thickness=10nm, relative permittivity of gate oxide =3.9, electron mobility=520cm 2 /v-sec, threshold voltage=0.7v, permittivity of free space=8.85x10-14 F/cm and W/L=8. Estimate the drain current when V GS= 2v and V DS =1.2v and also compute the gate oxide capacitance per unit area. Note that W and L refer to the width and length of the channel respectively. (8) ii) Evaluate the principle of SOI technology with neat diagram and list out its advantages and disadvantages. (5) 9. i) An NMOS transistor has a nominal threshold voltage of 0.16v. Inspect the shift in threshold voltage caused by body effect using the following data. The NMOS transistor is operating at a temperature of 300 o K with the following parameters: gate oxide thickness t ox =0.2x10-6 cm, relative permittivity of gate oxide ε ox =3.9, relative permittivity of silicon ε si =11.7, substrate bias voltage =2.5v, intrinsic electron concentration N i =1.5 x cm 3, impurity concentration in substrate N A =3 x cm 3. Given Boltzman s constant =1.38x10-23 J/ o K, electron charge =1.6x10-19 coulomb and permittivity of free space =8.85x10-14 F/cm. (8) ii) Examine a brief note on CMOS fabrication steps with necessary diagram. (5) Page 3 of 12

4 10. i) Draw the stick diagram and layout diagram using the function Y ( A B C). D of CMOS compound gate. (8) ii) Label the necessary stick diagram and layout for the design of NAD and NOR gates. (5) 11. i) Analyze the different steps involved in n-well CMOS fabrication process with neat diagrams. (8) ii) Explain the noise margin for a CMOS inverter. (5) 12. i) Construct the design rules for a CMOS inverter, in detail with a neat layout. (8) ii) Apply the mathematical equations that can be used to model the drain current and diffusion capacitance of MOS transistors. (5) 13. i) Express the Scaling Principles and its fundamental limits. (8) ii) Recall the principles of constant field and lateral scaling. Write the effects of the above scaling methods on device characteristics (5) 14. i) Define and derive the trans conductance of NMOS transistor. (8) ii) Write down the equations of the small signal model of an NMOS transistor. (5) PART C 1. With necessary illustrations explain the layout design rules and draw the layout diagram for four input NAND and NOR gate. (15) 2. Explain in detail about the need of scaling, scaling principles and effect of scaling on MOSFET device parameters. (15) 3. Derive an expression for Vin of a CMOS inverter to achieve the condition Vin=Vout. What should be the relation for βn=βp. (10) Explain the latch up conditions in CMOS circuits. (5) 4. Consider the NMOS transistor in a 180nm process with a nominal threshold voltage of 0.4V and doping level of 8 X cm-3. The body of the transistor is tied to ground with a substrate contact. How much the threshold change at room temperature if the source is at 1.1V instead of 0V? ε si =11.7 X 8.85x10-14 F/cm. (15) UNIT II COMBINATIONAL LOGIC CIRCUITS Examples of Combinational Logic Design, Elmore s constant, Pass transistor Logic, Transmission gates, static and dynamic CMOS design, Power dissipation Low power design principles. PART A Q. BT Questions No Level Competence 1. Describe path logical effort. 2. List the methods to reduce dynamic power dissipation. 3. Calculate logical effort and parasitic delay of n input NOR gate. 4. Distinguish between static and dynamic CMOS design. 5. Explain pass transistor logic. 6. Design an AND gate using pass transistor. 7. Justify why the interconnect increase the circuit delay. 8. Define critical path. Page 4 of 12

5 9. What is Elmore constant? 10. State the advantages of transmission gates. 11. Justify the reasons for the speed advantage of CVSL family. 12. Implement a 2:1 MUX using pass transistor. 13. Narrate about logical effort. 14. Summarize the expression for electrical effort of logic circuits. 15. Illustrate the method for reducing energy consumption of a logic circuit. 16. Discuss the advantages of power reduction in CMOS circuits. 17. Point out the factors that cause static power dissipation in CMOS circuits. 18. Mention the sources of power dissipation. 19. Draw the pseudo NMOS logic gate. 20. If load capacitance increases, What will happen to CMOS power dissipation? PART B 1. Analyze the following combinational circuits using the CMOS logic: i) Two input NOR gate. (3) ii) Parity generator (3) iii) Two input NAND gate. (3) iv) Multiplexers (4) 2. Describe in detail about i) Delay estimation. (5) ii) Logical effort. (4) iii) Transistor sizing. (4) 3. With supporting diagrams, give notes on : i) Static CMOS (4) ii) Bubble pushing (4) iii) Compound gates. (5) 4. i) Analyse the logical expression in the form of basic gates using CMOS logic, F= AB + CD. (6) ii) Estimate least delay and determine input capacitance of each stage for the logic network shown in figure, which may output of the network is loaded with a capacitance represent the critical path of a more complex logic block. The output of the network is loaded with a capacitance which is 5 times larger than the input capacitance of the first gate, which is a minimum-sized inverter. (7) 1 a b c 5 5. i) Formulate the expression for minimum possible delay of multistage logic networks. (6) ii) Derive the Elmore constant for NAND and NOR gates. (7) Page 5 of 12

6 6. Illustrate the expressions using Elmore s RC delay: i) Effective resistance (6) ii) Capacitance estimation. (7) 7. Discuss briefly the principle and operation of the following along with its advantages. i) Pass Transistor logic (6) ii) Complementary Pass Transistor Logic (7) 8. Write the principle of transmission gate using the design of multiplexer. (13) 9. i) Relate with Necessary Diagrams the principle of Zipper CMOS Logic. (6) ii) Implement AND/NAND gates using Dual-Rail Domino Logic. (7) 10. i) Identify the design issues in dynamic CMOS (6) ii) Recall the factors that should be considered while designing Dynamic CMOS. (7) 11. Explain the operation of the following along with necessary diagrams i) Dynamic CMOS Domino (6) ii) NP Domino logic with necessary diagrams. (7) 12. i) Examine the characteristics of Pseudo-NMOS Circuits with the help of Inverter, NAND and NOR Gates. (6) ii) Evaluate the different methods of reducing static and dynamic power dissipation in CMOS circuits and Explain in briefly. (7) 13. Write short notes on: i)ratioed Circuits (3) ii)dynamic CMOS Circuits (3) iii) Keepers (3) iv) Multiple Ouput Dynamic Logic (4) 14. Examine with necessary diagrams and expressions: i)static power dissipation in CMOS circuits (6) ii)dynamic power dissipation in CMOS circuits (7) PART C Q. No. Questions 1. i) Implement an EXOR gate using CMOS logic. (7) ii) Evaluate the delay of the fanout-of-4(fo4) inverter. Assume the inverter is constructed in180nm process with τ=15ps. (8) BTL4 BT Level Competence Page 6 of 12

7 2. i. Draw the static CMOS logic circuit for the following expression (a) Y= ( A.B.C.D) (5) (b) Y= D(A+BC) (5) ii. Discuss in detail the characteristics of CMOS transmission gate. (5) 3. i. Construct the CMOS logic circuit for the Boolean expression Z= [A (B+C) +DE] and explain. (8) ii. Explain about DCVSL logic with suitable example. (7) 4. i) Write the expression for minimum possible delay of multistage logic networks. (8) ii) Design and estimate the frequency of n-stage ring oscillator and construct the ring oscillator from an odd number of inverter. (7) UNIT III SEQUENTIAL LOGIC CIRCUITS Static and Dynamic Latches and Registers, Timing issues, pipelines, clock strategies, Memory architecture and memory control circuits, Low power memory circuits, Synchronous and Asynchronous design. PART A Q. No Questions BT Level Competence 1. List the advantages of differential flip flops. 2. Enumerate about NORA CMOS in brief? 3. Sketch the characteristic curve of meta stable state in static latch. 4. Distinguish between a latches and flip flop. 5. Classify the sequential elements in reducing the overhead and skew. 6. Define Clock Jitter. 7. Summarize the operation modes of NORA logic. 8. Determine the property of clock overlap in the registers. 9. What is Klass semi dynamic flip flop? 10. Recall the methods of sequencing static circuit. 11. Write about pipelining? 12. Compare and Contrast Synchronous and Asynchronous Design? 13. Explain simple synchronizer circuit. 14. Formulate hold-time problem which would occur, If a data path circuits uses pulsed latches in place of flip flops. 15. Justify the advantages and applications of self-time pipelined circuits. 16. Design a 1-transistor DRAM cell. 17. Illustrate the concept of clock skew in transparent latches. 18. Give the properties of TSPC. 19. Why pipelining is need for of sequential circuits? 20. Draw the schematic of dynamic edge-triggered register. Page 7 of 12

8 PART B 1. Explain the sequencing methods of sequential static circuits. (13) 2. Discuss in detail : i) Synchronous pipelining in sequential circuits. (7) ii) Asynchronous pipelining in sequential circuits. (6) 3. Write about the latches and flip-flops in design methodology of sequential circuit design (13) 4. i) State and explain the Klass semi dynamic flip flops and differential Flip flops. (7) ii) Illustrate the enabled latches and flip flops. (6) 5. i) Design a D-latch using transmission gate. (7) ii) Evaluate a 1-bit dynamic inverting and noninverting register using pass transistor. (6) 6. i) Draw and explain the operation of conventional CMOS pulsed and resettable latches. (7) ii) Estimate about sequencing dynamic circuits. (6) 7. i) Compare the sequencing in traditional Domino and Skew tolerant Domino circuit with neat diagrams. (7) ii)elucidate a floating gate transistor and its programming methodology. (6) 8. Describe about the concept of timing issues and pipelining. (13) 9. Give a brief note on: i) CMOS S-RAM cell and Dynamic RAM cell. (7) ii) 4T and 6T SRAM cell structures (6) 10. i) Consider a flip flop built from a pair of transparent latches using non overlapping clocks. Determine the set-up time, hold time and clock-to-q-delay of the flip flops in terms of the latch timing parameters and t nonoverlap. (7) ii) Design a 2 input CVSL AND/NAND gate and a 3 input CVSL OR/NOR gate. (6) 11. Write Short notes on : i) True Single phase clocked register (7) ii) NORA- CMOS pipelined latches (6) 12. Illustrate with necessary diagrams the design and organization of CAM. (13) 13. Explain in detail about: i) Synchronizers (7) ii) Metastability. (6) 14. Demonstrate the maximum and minimum delay constraints needed to design sequential circuits. (13) PART C 1. Discuss about the design of sequential dynamic circuits and its pipelining concept. (15) 2. Explain the timing basics and clock distribution techniques in Evaluate synchronous design in detail. (15) 3. Elaborate about various static latches and registers. (15) 4. Interpret the operation of Master Slave edge triggered register. (15) Page 8 of 12

9 UNIT IV DESIGNING ARITHMETIC BUILDING BLOCKS Data path circuits, Architectures for ripple carry adders, carry look ahead adders, High speed adders, accumulators, Multipliers, dividers, Barrel shifters, speed and area trade-off. Q. No Questions PART A BT Level Competence 1. Derive the expression for critical path of an array multiplier. 2. Summarize the characteristics of Manchester carry chain adder. 3. List out the components of Datapath Why is barrel Shifters very useful in the designing of arithmetic circuits? Interpret a partial product selection table using modified 3-bit booth s recoding multiplication. 6. What is latency? Compare constant throughput/latency and variable throughput latency in active & leakage mode. List the advantages and disadvantages of full adder design using static CMOS. Analyze the concept of Dynamic voltage scaling and list its advantages. 10. Define Clock gating. 11. a schematic for Sleep transistors used on both supply and ground. 12. Examine the need of VTCMOS 13. Give the applications of high speed adder 14. Analyze the inverting property of full adder. 15. How to design a high speed adder? 16. Write about logical and architectural optimization? 17. Classify Power optimization techniques for latency and throughput constrained design. 18. Write the principle of any one fast multiplier? 19. Sketch a Manchester carry gate. 20. Elaborate the Concept of Transmission gate full adder. PART B 1. i) Describe ripple carry adder and derive the expression for worst case delay. (10) ii) Write a note on Carry Bypass adders (3) 2. Examine the concept of carry look ahead adder with neat diagram. (13) Page 9 of 12

10 3. Outline the operation of a basic 4 bit adder. Describe the different approaches of improving the speed of the adder. (13) 4. Illustrate the concepts of monolithic and logarithmic look ahead adder. (13) 5. Define shifter and give a short note on i) Barrel shifter (7) ii) Logarithmic shifter. (6) 6. i) Demonstrate how to reduce the number of generated partial products by half. (7) ii) Identify and explain the concept of Dynamic Voltage Scaling. (6) 7. Design the arithmetic logic unit (ALU) of 64 bit high end microprocessor and arithmetic operators involved in design. (13) 8. Summarize the methods involved in run time power management. (13) 9. Determine the implementation of a i)look ahead adder in dynamic logic. (7) ii)parallel Prefix adder (6) 10. Give a note on linear carry select adder. (13) 11. Examine the operation of : i)static CMOS adders. (7) ii)mirror adder (6) 12. Analyze the operation of booth multiplication with suitable examples. Justify how booth algorithm speed up the multiplication process. (13) 13. Discuss the data paths in digital processor architectures. (13) 14. Write short notes on: i) Walllace multipliers (7) ii) Dadda multipliers (6) 1. PART C Assess the structure of ripple carry adder with a neat diagram and explain its operation. How the drawback in ripple carry adder overcome by carry look ahead adder and discuss. (15) 2. Design a multiplier for 5 bit by 3 bit. Explain its operation and summarize the number of adders. Discuss it over Wallace multiplier. (15) 3. Explain a Modified Booth algorithm with a suitable example. (15) 4. Discuss the steps in designing restoring division circuit. (15) Page 10 of 12

11 UNIT V IMPLEMENTATION STRATEGIES Full custom and Semi-custom design, Standard cell design and cell libraries, FPGA building block architectures, FPGA interconnect routing procedures. PART A Q. No Questions BT Level Competence 1. What is antifuse? State its merits and demerits. 2. Classify the implementation approaches for digital integrated circuits. 3. List out the advantages and disadvantages of cell based design methodology. 4. Narrate about feed-through cells and state their uses. 5. Classify the types of Macro cells. 6. Give a note on Tape out of chip. 7. State the features of full-custom design. 8. Compare semi-custom and full custom design. 9. Describe about standard cell based ASIC design? 10. Define Fuse based FPGA. 11. Name the elements in a configuration logic Block. 12. Develop an array based architecture used in Altera MAX series. 13. Design a primitive gate array cell. 14. Explain configurable logic block. 15. Summarize the functions of Programmable Interconnect Points in FPGA. 16. Identify the issues in implementing Boolean functions on array of cells. 17. Summarize the design steps of Semicustom design flow. 18. Illustrate Composition of generic digital processor. 19. Outline the steps for ASIC design flow. Understand 20. Write the various ways of routing procedure PART B 1. (i) List and explain the components that makeup the cell based design methodology. (8) (ii) Give a short note on programming of PAL. (5) 2. (i)describe the Steps involved in semicustom design flow. (7) (ii)explain the concepts of programmable interconnect. (6) 3. (i)describe the Blocks involved in digital processor. (8) (ii)define and explain the approaches of programmable wiring. (5) 4. (i)illustrate the concepts of Mask programmable arrays. (10) (ii)identify the components involved in constructing a voltage output macrocell. (3) Page 11 of 12

12 5. Explain the types of FPGA routing techniques. (13) 6. Examine the interconnect architectures of Altera Max series (7) Xilinx XC40XX series (6) 7. (i)identify and Explain the FPGA block structure along its components. (7) (ii) Mention in detail the techniques involved in Switch box programmable wiring. (6) 8. (i)discuss the types of FPGA routing techniques. (7) (i)demonstrate the types of ASICS. (6) 9. Design an LUT-Based Logic Cell. (7) Elaborate the Classification of prewired arrays. (6) 10. (i) Compare two types of macrocells. (6) (ii) Inspect the datapaths in digital processor architectures. (7) 11. Discuss the different types of programming technology used in FPGA design. (13) 12. Categorize the semi-custom ASIC with necessary diagrams. (13) 13. Explain the classification of ASIC with necessary block diagram. (i) Full Custom ASIC (7) (ii) Semi-Custom ASIC (6) 14. Write short notes on (i) Xilinx LCA (6) (ii) Altera Max (7) PART C 1. With neat sketch explain the CLB, IOB and programmable interconnects of an FPGA device. (15) 2. Draw and explain the building blocks of FPGA with different fusing technologies. (15) (i) Explain about building block architecture of FPGA (10) (ii) Write short notes on routing procedures involved in FPGA interconnect. (5) Discuss in detail about different types of ASIC with neat diagram. (15) Page 12 of 12

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203. DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING SUBJECT : EC6601 VLSI DESIGN QUESTION BANK SEM / YEAR: VI / IIIyear B.E. EC6601VLSI