nmos, pmos - Enhancement and depletion MOSFET, threshold voltage, body effect

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1 COURSE DELIVERY PLAN - THEORY Page! 1 of! 7 Department of Electronics and Communication Engineering B.E/B.Tech/M.E/M.Tech : EC Regulation: 2016(Autonomous) PG Specialization : Not Applicable Sub. Code / Sub. Name : EC VLSI Design Unit : I LP: EC16601 Rev. No: 00 Date: Unit Syllabus: MOS TRANSISTOR PRINCIPLE (9) Fabrication Process - MOSFET, CMOS- n-well, p-well, Twin tub, SOI, CMOS inverter characteristics, Second order effects, Stick diagram, Layout diagrams, Scaling principles and fundamental limits Objective: To understand the principles of MOS transistors, CMOS technologies and Layout diagrams. No* 1 Introduction to VLSI Design - Fabrication Process MOSFET, CMOS Technologies 1,3,5 PPT 2 Fabrication Process CMOS Technology - n-well, p-well process 1,3 PPT 3 Fabrication Process CMOS Technology - Twin tub, Silicon on Insulator (SOI) 1,3 PPT 4 nmos, pmos - Enhancement and depletion MOSFET, threshold voltage, body effect 1,3,5 PPT 5 MOS transistor - Second order effects 3,5 PPT,BB 6 CMOS inverter DC characteristics 1,3,5 PPT,BB 7 Beta ratio effects, Noise Margin 1,3,5 PPT,BB 8 Stick diagram: Nmos Design and CMOS Design style 3,5 PPT,BB 9 Layout diagrams: Design rules, Layer Representation 3,5 PPT,BB 10 Scaling principles and fundamental limits Constant, Lateral and Interconnect scaling, CMOS inverter scaling Content beyond syllabus covered (if any): 3,5 PPT * duration: 50 minutes

2 COURSE DELIVERY PLAN - THEORY Page! 2 of! 7

3 COURSE DELIVERY PLAN - THEORY Page! 3 of! 7 Unit : II Unit Syllabus: COMBINATIONAL LOGIC CIRCUITS (9) Examples of Combinational Logic Design, Elmore s constant, Pass transistor Logic, Transmission gates, static and dynamic CMOS design, Power dissipation Low power design principles Objective: To impart the knowledge on the transistor circuit level design of combinational circuits 11 Examples of Combinational Logic Design: NAND Logic, NOR Logic, Compound gates 1,2,3 PPT,BB 12 Elmore s constant - Delay estimation of basic gates. 2,3 PPT,BB 13 Pass transistor Logic: Basic working, Realization of logic circuits using various pass transistor styles 14 Transmission gates: Basic working, Realization of logic circuits using Transmission gates 1,3 PPT,BB 3,4,6 PPT,BB 15 Static CMOS design: Ratioed logic 1,3,4 PPT,BB 16 Dynamic CMOS design: Domino logic, NP domino, Issues in cascading dynamic gates 1,3,5 PPT,BB - CAT-I Power dissipation: Static power dissipation 1,3 PPT,BB 18 Dynamic power dissipation,dynamic power reduction techniques 3,5 PPT,BB 19 Low power design principles, Low power logic styles 1,3 PPT,BB Content beyond syllabus covered (if any): NIL * duration: 50 mins

4 COURSE DELIVERY PLAN - THEORY Page! 4 of! 7 Unit : III Unit Syllabus: SEQUENTIAL LOGIC CIRCUITS (9) Static and Dynamic Latches and Registers, Timing issues, pipelines, clock strategies, Memory architecture and memory control circuits, Low power memory circuits, Synchronous and Asynchronous design Objective: To impart the knowledge on the transistor circuit level design of sequential circuits. 20 Static Latches and Registers: Bi stability principles, CMOS latches 1,3 PPT, BB 21 Dynamic Latches and Registers-Various CMOS styles 1,3 PPT, BB 22 Timing issues: Set up and hold time, timing metrics for sequential circuits 3 PPT, BB 23 Pipelines: Latch,register based pipeline, NOR-A CMOS logic style 1,3 PPT, BB 24 Clock strategies: Single phase, two phase,four phase clocking structures, synchronizer 3,6 PPT 25 Memory architecture and building blocks-ram,rom,cam 1,3,4 PPT, BB 26 Memory control circuits and peripheral circuits-address decoder, sense amplifiers, drivers 1,3 PPT 27 Low power memory circuits: Sources of power dissipation in memories Synchronous and Asynchronous design: Timing basics, 28 skew,clock distribution techniques. 1,3 PPT, BB 1,3 PPT, BB Content beyond syllabus covered (if any): NIL * duration: 50 mins

5 COURSE DELIVERY PLAN - THEORY Page! 5 of! 7 Unit : IV Unit Syllabus: DESIGNING ARITHMETIC BUILDING BLOCKS 9 Data path circuits, Architectures for ripple carry adders, carry look-ahead adders, High speed adders, accumulators, Multipliers, dividers, Barrel shifters, and speed area tradeoff. Objective: To understand MOS circuit realization of the various arithmetic building blocks that is common to any microprocessor or digital VLSI circuit. 29 Data path operations, Data path circuits 1,2,3 PPT 30 Architectures for ripple carry adders: Design of n- bit adders 31 Carry look ahead adders: Circuit design considerations 1,2,5 2,3 PPT PPT 32 High speed adders-carry select adder, Carry save adder, carry skip adder, Manchester adders 2,3,5 PPT 33 Accumulators, Priority encoder, Decoder-CMOS logic design 2,3 PPT, BB 34 Multipliers: Serial, parallel, Braun array multiplier 1,2,5 PPT, BB - CAT-II Booth multiplier, Wallace tree multiplier 36 Dividers, Barrel shifters 3,5 2,3 PPT, BB PPT, BB 37 Speed and area tradeoff-adders, multipliers 1,2 PPT, BB Content beyond syllabus covered (if any): Priority encoder,decoder * duration: 50 mins

6 COURSE DELIVERY PLAN - THEORY Page! 6 of! 7 Unit : V Unit Syllabus: IMPLEMENTATION STRATEGIES 9 Full custom and Semi-custom design, Standard cell design and cell libraries, FPGA building block architectures, FPGA interconnect routing procedures. Objective: To impart knowledge on architectural choices and performance tradeoffs involved in designing and realizing the circuits in CMOS technology. 38 Programmable logic devices, Full custom design 1,2,6 PPT 39 Semi custom design -Standard cell design and cell libraries 1,2,3 PPT 40 Gate array based Implementation approaches 1,2,3 PPT FPGA building block architectures: programmable logic structures- Actel FPGAs FPGA interconnect routing procedures: programmable Interconnect- Altera FPGAs FPGA interconnect routing procedures: programmable Interconnect- Xilinx FPGAs 2,3 PPT,BB 2,3 PPT 2,3 PPT 44 Algotronix, Concurrent logic 2,3 PPT,BB 45 Basics of VLSI testing 3,5 PPT,BB - CAT-III - - Content beyond syllabus covered (if any): Basics of VLSI testing * duration: 50 mins

7 COURSE DELIVERY PLAN - THEORY Page! 7 of! 7 Sub Code / Sub Name: EC16601/VLSI Design TEXTBOOKS: 1. Jan Rabaey, Anantha Chandrakasan, B.Nikolic, Digital Integrated Circuits: A Design Perspective, Second Edition, Prentice Hall of India, M.J. Smith, Application Specific Integrated Circuits, Addisson Wesley, 1997 REFERENCES: 3. N.Weste, K.Eshraghian, Principles of CMOS VLSI Design, Second Edition, Addision Wesley R.Jacob Baker, Harry W.LI., David E.Boyee, CMOS Circuit Design, Layout and Simulation, Prentice Hall of India A.Pucknell, Kamran Eshraghian, BASIC VLSI Design, Third Edition, Prentice Hall of India, Prepared by Approved by Signature Name Dr.S.R.Malathi, Mr.M.Athappan, Ms. S.Sangeethapriya Dr.S.MuthuKumar Designation Associate Professor Assistant Professor Assistant Professor HOD-EC Date Remarks *: Remarks *: * If the same lesson plan is followed in the subsequent semester/year it should be mentioned and signed by the Faculty and the HOD