CONTENTS. low power vlsi design (COMMON TO VLSI/VLSI DESIGN/VLSI SYSTEM DESIGN) OW-POWER CIRCUIT DESIGN SOURCES OF POWER DISSIPATION

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1 i low power vlsi design FOR m.tech (jntu - h&k) i year Ii semester (COMMON TO VLSI/VLSI DESIGN/VLSI SYSTEM DESIGN) CONTENTS UNIT - I [FUND FUNDAMENT AMENTALS ALS OF LOW OW-POWER CMOS VLSI DESIGN] NEED FOR LOW OW-POWER CIRCUIT DESIGN SOURCES OF POWER DISSIPATION Dynamic Power Dissipation Switching Power Dissipation Short Circuit Power Dissipation Glitching Power Dissipation Static Power Dissipation SHORT-CHANNEL DEVICES Short-Channel Effects Drain-Induced Barrier Lowering and Punchthrough Surface Scattering Velocity Saturation Impact Ionization Hot Electron Effect

2 ii UNIT - II [LOW OW-POWER DESIGN APPROACHES CHES] INTRODUCTION LOW OW-POWER DESIGN THROUGH VOL OLTAGE SCALING Influence of Voltage Scaling on Power and Delay Techniques to Overcome Difficulties Associated with Low ow-v t Circuits Variable ariable-threshold CMOS (VTCMOS) Circuits Multiple-Threshold CMOS (MTCMOS) Circuits LOW OW-POWER LOGIC ARCHITECTURAL LEVEL APPROACH Pipelining Approach Parallel Processing Approach (Hardware Replication) SWITCHED CAPACIT CITANCE MINIMIZATION APPROACHES System-Level Measures Circuit-Level Measures Mask-L -Level Measures UNIT - III [LOW VOLTAGE LOW-POWER ADDERS] INTRODUCTION STAND ANDARD ARD ADDER CELLS Half Adders Full Adders and their Various Schematic Configurations CMOS ADDER S ARCHITECTURES Ripple Carry Adders (RCA) Carry Look ook-ahead Adder (CLA) Variation of the Basic CLA Manchester Carry Chain (MCC) and Manchester Adder

3 iii Carry Select Adders (CSL) Hybrid Carry Look ook-ahead/carry Select Adder (Hybrid CLA/CSL) Carry Save Adders (CSA) LOW OLTAGE LOW OW-POWER DESIGN TECHNIQUES Trends of Technology and Power Supply Voltage Low ow-voltage oltage Low -Power Logic Styles Static and Dynamic Logic Styles XOR/XNOR Gate Implementations of Different Logic Styles Bit CLA Adder Implementations UNIT - IV [LOW OLTAGE LOW OW-POWER MULTIPLIERS TIPLIERS] INTRODUCTION OVERVIEW OF MULTIPLICA TIPLICATION TION Unsigned Multiplication Shift/Add Multiplication Algorithm Multiplication of Signed Numbers TYPES OF MULTIPLIER ARCHITECTURES Serial Multiplier Parallel Multiplier Serial-Parallel arallel Multiplier TYPES OF DIGITAL MULTIPLIERS BRAUN MULTIPLIER Architecture of Braun Multiplier Performance of Braun Multiplier Speed Consideration Enhanced Braun Multiplier

4 iv 4.6 BAUGH- UGH-WOOLEY MULTIPLIER s Complement Number System Performance Consideration BOOTH MULTIPLIER Booth s Algorithm Standard Radix-2 Booth Multiplication Rules Modified Booth Algorithm Booth Encoder WALLA ALLACE TREE MULTIPLIER TIPLIER : 2 Compressor Wallace Tree ree Construction UNIT - V [LOW OLTAGE LOW OW-POWER MEMORIES] INTRODUCTION BASICS OF ROM Chip Architecture ROM Cell Arrays LOW OW-POWER ROM TECHNOLOG OGY Sources of Power Dissipation Low -Power Techniques FUTURE TREND AND DEVELOPMENT OF ROMS BASICS OF SRAM MEMORY CELL Transistor (4T) Cell Transistor (6T) Cell The Film Transistor (TFT) Cell PRECHARGE AND EQUALIZA ALIZATION CIRCUIT

5 v 5.8 LOW OW-POWER SRAM TECHNOLOGIES OGIES Sources of SRAM Power Development of Low -Power Circuit Techniques Capacitance Reduction AC Current Reduction Pulse Operation Techniques Low -Power Sensing Technique echnique Leakage Current Reduction BASICS OF DRAM DRAM Architecture SELF-REFRESH CIRCUIT

6 vi STUDENT NOTES