An 8-bit 8-stage FIR Filter using the CMOS 28nm FDSOI Technology
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1 An 8-bit 8-stage FIR Filter using the CMOS 28nm FDSOI Technology Implementation and Simulation of TSPC Flipflop, CLA Adder and 8-bit radix-4 Booth Multiplier Sergiu Mosanu and Minyao Zhang
2 FIR overview 2
3 Simulation as proof of concept Signals are floats FIR consists of integer operation blocks Quantization is required will it work? 3
4 Simulation in python Original signal consisting of 4 harmonics. Quantized signal and quantization error. 4
5 Simulation in python Original signal frequency distribution. Quantized signal frequency distribution. 5
6 Simulation in python Filter generated coefficients based on desired frequency response [4]. 6
7 Simulation in python Coefficients of N=17 FIR filter. Quantized coefficients and quantization error. 7
8 Simulation in python Range = 0 to bit value!!! Pre-processed quantized filter output. 8
9 Simulation in python Filtered signal using float operations. Processed quantized filter output and total error. 9
10 Simulation in python FFT of filtered signal using float operations. FFT of quantized filtered signal. 10
11 True Single Phase Clocked flipflop design Schematic diagram of a TCSP flipflop. 11
12 True Single Phase Clocked flipflop design Schematic diagram of the 8-bit flipflop. 12
13 TSPC flipflop simulation TSPC flipflop 8-bit block delay element simulation. 13
14 Carry Look Ahead (CLA) Adder Propagate Generate Sum CLA Partial Full Adder component schematics. 14
15 Carry Look Ahead (CLA) Adder Look Ahead Logic Block Schematics. Uses P, G and S to compute the Carry bits 15
16 Carry Look Ahead (CLA) Adder 12-bit CLA adder full schematics. 16
17 Carry Look Ahead (CLA) Adder 12-bit CLA adder full schematics in more detail. 17
18 Carry Look Ahead (CLA) Adder Simulation Carry Look Ahead adder simulation. We tested the adder with several inputs and the results were correct. Critical test: adding all-1 signals. 18
19 Carry Look Ahead (CLA) Adder Simulation Carry Look Ahead adder delay. The measured critical delay is t HL t LH = 0.15ns. 19
20 8x8 radix-4 Booth Multiplier Grouping Partial Product Comments 0 0*M string of zeros 1 1*M a single *M a single *M end of ones 100-2*M beginning of ones 101-1*M beginning of ones 110-1*M beginning of ones 111 0*M string of ones Computes: Single Double Negate Encoder Schematics. 20
21 8x8 radix-4 Booth Multiplier Full Encoder Schematics for 8-bit multiplier. 21
22 8x8 radix-4 Booth Multiplier Decoder Schematics. Uses the Single, Double and Negate to compute partial products. 22
23 8x8 radix-4 Booth Multiplier Half adder necessary to implement two's complement negation. Half Adder Schematics. 23
24 8x8 radix-4 Booth Multiplier Full Decoder Schematics. 24
25 8x8 radix-4 Booth Multiplier Full Decoder Schematics in detail. 25
26 Full Multiplier Schematics. 26
27 8x8 radix-4 Booth Multiplier simulation Test simulation x =
28 8x8 radix-4 Booth Multiplier simulation Multiplier Delay The critical delay measured is t LH = 0.42 ns, t HL = 0.14 ns. 28
29 Finite Impulse Response Filter FIR schematics overview 29
30 Finite Impulse Response Filter FIR schematics in more detail 30
31 Finite Impulse Response Filter FIR Filter Testbench 31
32 Results and Conclusion Gate # transistors Flipflop 11 8-bit flipflip 88 CLA PFA 32 CLA LALB bit CLA bit CLA 960 Encoder 38 Decoder 36 Half Adder 22 8-bit Multiplier 2858 FIR (total) Block Leakage 0 Leakage 1 Total Dynamic power 8-bit flipflop 20 nw 15.9 nw 2.1 µw 20-bit CLA adder 26.2 nw 30.8 nw 33.4 µw 8-bit BM nw nw 46 µw VLSI is fun! (and hard work!) Achieved successful operation for the flipflops, carry look-ahead adder and booth encoding multiplier Optimized sizing for improved delay times and reduced glitches Perform Corners simulations and Monte Carlo Process Variation 32
33 References [1] Technology CMOS28FDSOI 28 nm SOI 3D [2] Latches and Flip-Flops by Dr. Paul D. Franzon, NCSU [3] CMOS Binary Full Adder - A Survey of Possible Implementations by E. Turgay, A. Daniels, M. Bacelieri, W. Berry, UKY [4] arc.id.au FIR Filter Design [5] Design of an 8x8 Modified Booth Multiplier by Robbie D'Angelo and Scott Smith [6] Digital Computer Arithmetic by Israel Koren, University of Massachusetts 33
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