Design and Performance Analysis of 64 bit Multiplier using Carry Save Adder and its DSP Application using Cadence

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1 Design and Performance Analysis of 64 bit Multiplier using Carry Save Adder and its DSP Application using Cadence Krishna Naik Dungavath Assistant Professor, Dept. of ECE, PVKKIT, Anantapuramu,, Andhra Pradesh, India. Dr. V.Vijayalakshmi Associate Professor, Dept. of ECE, Pondicherry Engineering College, Puducherry, India. Abstract: In this paper we have shown the design and implementation of multiplier in which carry save adder is used as an adder block for the addition of partial products of both multiplier and multiplicand as 64 bits and the product size is of 128 bit. Multiplication is the fundamental arithmetic operation that plays a critical role in several processors and digital signal processing systems. Digital signal processing systems need multiplication algorithms to implement DSP algorithms such as filtering where the multiplication algorithm is directly within the critical path. The Finite Impulse Response (FIR) filter is a digital filter widely used in Digital Signal Processing applications in various fields. The implementation of an FIR requires three basic building blocks i.e. Multiplication, Addition, Unit delay. In a DSP system the multiplier must be fast and must have sufficient precision (bit width) to support the desired application. A high quality filter will in general require more multiplications than one of lesser quality, so throughput suffers if the multiplier is not fast. Hence 64 bit multiplier with carry save adder is designed and the same block which is of 8 bit is implemented in FIR (8-tap) filter. A comparison between array multiplier and multiplier with carry save adder is shown and the proposed technique is efficient in terms of power. A comparison between FIR filter with array multiplier block and FIR filter with multiplier with carry save adder block is shown and the proposed technique is efficient in terms of power and speed. The code is written in Verilog and the simulation and synthesis is carried out in Cadence Encounter tool. Keywords: Cadence Encounter, Verilog, Array Multiplier, Multiplier with Carry Save Adder, FIR Filter with Array Multiplier block, FIR Filter with Multiplier with Carry Save Adder block I. INTRODUCTION The major considerations while designing the digital circuits are speed, power and area. Multiplication is a mathematical operation that at its simplest is an abbreviated process of adding an integer a specified number of times. A basic multiplier can be divided into three parts i) partial product generation ii) partial product addition and iii) final addition. Multiplication plays an important role in Digital Signal Processing (DSP) applications, such as filtering and fast Fourier transform (FFT). Parallel array multipliers are widely used to achieve high speed execution. But these multipliers consume more power. In today s VLSI system design, Power consumption has become a critical concern. For the design of low-power DSP systems the designers need to concentrate on power efficient multipliers. The impulse response of the filter can be either finite or infinite. The methods for designing and implementing of these two filter classes differ considerably. Finite impulse response (FIR) filters are digital filters whose response to a unit impulse (unit sample function) is finite in duration. This is in contrast to infinite impulse response (IIR) filters whose response to a unit impulse (unit sample function) is infinite in duration. FIR and IIR filters each have advantages and disadvantages. In some applications, the FIR filter circuit must be able to operate at high sample rates, while in other applications the FIR filter circuit must be a low power. Circuit operating at moderate sample rates.the main objective of this project to design power efficient multiplier block and to design high speed and low power FIR filter. The work carried out is described in brief as follows. Section II explains the multiplication of two numbers i.e. array multiplication. Section III represents the architecture of multiplier with carry save adder. Section IV describes the FIR filter with array multiplier block. Section V shows the FIR filter with multiplier with carry save adder block. Section VI consists of experimental results. Section VII concludes this paper Volume 7 Issue 4 December

2 Fig.1.Array Multiplication II. ARRAY MULTIPLICATION Array multiplier is well known due to its regular structure. Multiplier circuit is based on add and shift algorithm. Each partial product is generated by the multiplication of the multiplicand with one multiplier bit. The partial product are shifted according to their bit orders and then added. The addition can be performed with normal carry propagate adder. In array multiplication we need to add, as many partial products as there are multiplier bits. III.ARCHITECTURE OF MULTIPLIER WITH CARRY SAVE ADDER Fig. 2.Multiplier with Carry saves Adder Architecture In the Carry Save Addition method, the first row will be either Half-Adders or Full-Adders. If the first row of the partial products is implemented with Full-Adders, Cin will be considered 0. Then the carries of each Full- Adder can be diagonally forwarded to the next row of the adder. The resulting multiplier is said to be Carry Save Multiplier, because the carry bits are not immediately added, but rather are saved for the next stage. In the design if the full adders have two input data the third input is considered as zero. In the final stage, carries and sums are merged in a fast carry-propagate (e.g. ripple carry or carry look ahead) adder stage. IV.FIR FILTER Fig.3. Basic Form of FIR Filter Volume 7 Issue 4 December

3 Filters are signal processing components that are used to process interfered and corrupted signals. They can be classified to two main categories: analog and digital filters. Filters in these two categories are different in terms of cost, speed, accuracy, power consumption and implementation, but they are similar in the sense that they are both used to filter signals. A commonly used method of implementing digital filters is by considering a subset of the filter s impulse response. Filter designed this way are called finite impulse response (FIR) filters. The mathematical process used to get the output of a linear system according to its impulse response is the convolution. When a digital signal x[n] is to be processed by a system of impulse response h[n], the output is the result of the following equation The above equation describes how each sample of the output signal is calculated. This is an application of the widely used mathematical operation of the dot product, which consists purely of multiplication and addition. Here multiplication is carried out using array multiplier and addition by the basic adder. V.FIR FILTER WITH MULTIPLIER WITH CARRY SAVE ADDER Here the basic form of FIR Filter structure is considered. The building blocks of FIR filter is multiplier, adder and delay unit. Here in case of multiplier we consider multiplier with carry save adder block. In case of adder we use basic adder for addition. Delay element we are using is D-Flipflop.FIR filter with multiplier with carry save adder block is the new technique which is proposed to improve speed and to reduce power. VI. RESULTS The analysis is done using Cadence Encounter tool to simulate and synthesize both Array Multiplier and Multiplier with Carry Save Adder, FIR Filter with Array Multiplier and FIR Filter with Multiplier with Carry Save Adder. The code is written in Verilog HDL to optimize the power of 64 bit multiplier and to optimize the power and speed of FIR filter. Array multiplier Simulation waveforms Synthesis Report Fig bit array multiplier waveforms Volume 7 Issue 4 December

4 Power Report Multiplier with carry save adder Simulation waveforms Synthesis Report Fig bit multiplier with carry save adder waveforms Volume 7 Issue 4 December

5 Power Report FIR Filter with Array multiplier Simulation waveforms Fig.6. 8 tap FIR Filter waveforms Synthesis report Power Report Volume 7 Issue 4 December

6 Timing Report FIR Filter with multiplier with carry save adder Simulation waveforms Fig tap FIR Filter with multiplier with carry save adder Synthesis Report Volume 7 Issue 4 December

7 Power Report Timing Report The power consumption of 64 bit conventional multiplier and proposed multiplier is shown in the table. Table.1. Total, Power comparison of different multipliers. S.No Multiplier Total Power (nw) 1. Conventional Multiplier 2. Proposed Multiplier The power consumption and timing performance of 8 tap Conventional FIR filter and proposed FIR filter is shown in The table Table.2.Total Power and Timing comparison of different FIR filters S.No FIR Filter Total Power(nW) Time(Ps) 1. Conventional FIR Filter 2. Proposed FIR Filter Volume 7 Issue 4 December

8 VII. CONCLUSION This paper presents two different multipliers and two different FIR filters that are modeled using verilog. The proposed multiplier is more efficient in power than the conventional multiplier. The proposed FIR filter is more efficient in power and timing performance than the conventional FIR filter. The simulation and synthesis reports are obtained using the Cadence tool. REFERENCES [1] A text book on CMOS VLSI DESIGN, A Circuits and Systems Perspective,4th Edition by Neil H.E.Weste, [2] S. Smith, The Scientist and Engineer's Guide to Digital Signal Processing, San Diego: California Technical Publishing, [3] Nik Ghazali Nik Daud, Forkful Ridzuan Hashim, Hybrid Modified Booth Encoded Algorithm-Carry Save Adder Fast Multiplier, IEEE [4] Maroju SaiKumar, Design and Performance Analysis of Various Adders using Verilog, International Journal of Computer Science and Mobile Computing, IJCSMC, Vol. 2, Issue. 9, September [5] A. Arun, Design of Novel FIR Filter Using Add and Shift Multiplier and Carry Save Adder, IJCSEC-International Journal of Computer Science and Engineering Communications, Vol.2 Issue.3, May [6] Hesham Altwaijry, FIR Filter Design Using The Signed-Digit Number System and Carry Save Adders A Comparison, (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 4, No.12, [7] N. Jhansi, Design and Analysis of High Performance FIR Filter using MAC Unit, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 3, Issue 11, November [8] Mr. Pravin Y.Kadu1, High Speed and Low Power FIR Filter Implementation Using Optimized Adder And Multiplier Based On Xilinx FPGA, IORD Journal of Science & Technology E-ISSN: Volume 1, Issue III (MAR-APR 2014). [9] Ravi, A.Satish, A New Design for Array Multiplier withtrade off in Power and Area, IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 3, May [10 Bahram Rashidi, Bahman Rashidi and Majid ourormazd Design and Implementation of Low Power Digital FIR Filter based on low power multipliers and adders on xilinx FPGA IEEE [11] V.Vijayalakshmil, R.Seshadd, Dr.S.Ramakrishnan3 Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA IEEE Volume 7 Issue 4 December