CHAPTER 2 LITERATURE SURVEY

Transcription

1 19 CHAPTER 2 LITERATURE SURVEY 2.1 INTRODUCTION Digital signal processors and ASICs rely on the efficient implementation of arithmetic circuits to execute dedicated algorithms such as convolution, correlation and digital filtering (Chang et al 2005).The execution of these algorithms require dedicated ALU and MAC architectures. Adders, multipliers and counters are the key elements of these arithmetic units and this chapter discusses the various algorithms and architectures proposed in the design of these key elements. 2.2 ADDERS Adders lie in the critical path of a processing architecture and the critical path determine the overall performance of the system, so an investigation of various adders is carried out in the following section Full Adder Several variant logic styles have been used to design the full adder cells (Chang et al 2005)(Zimmermann and Fichtner1997)(Goel et al 2006) (Hassoune et al 2010) (Hassoune 2006)(Abu-Khather et al 1996) (Piguet and Piguet 2004). Conventional FA designs normally use only one logic style for the entire circuit. Static CMOS FA structure is based on the PMOS pull-up and NMOS pull-down transistors. Advantages of static CMOS logic style are

2 20 its sturdiness against voltage scaling and transistor sizing and thus reliable operation at low voltages. The main drawback of static CMOS logic is the number of large PMOS transistors resulting in high input loads. Another drawback is the weak output driving capability (Zimmermann and Fichtner 1997). CPL FA has complementary inputs/outputs using NMOS PT logic with CMOS output inverters. Although CPL adder cell requires less number of transistors and has high speed of operation, it suffers from threshold voltage drop problem (Chang et al 2005), (Goel et al 2006). The Transmission Gate Adder (TGA) uses both NMOS and PMOS transistors in parallel for implementing the logic. Like CMOS FA, TGA also require complementary inputs. However TGA requires lower number of transistors per stack, which makes it suitable for high speed operation (Chang et al 2005). Although TGA has fewer transistor counts, it suffers from weak driving capability making it unsuitable for complex circuits. Some full-adder designs use different logic styles for sum and carry blocks. One such adder is the CPL-TG FA (Abu-Khather et al 1996). It uses CPL XOR logic to generate the signal P = A XOR B. From the generated P, sum and carry are generated using TG logic. The use of CPL circuit reduces the number of transistors, hence reduces the power consumption (Abu-Khather et al 1996). However it suffers from weak driving capability. A more restrictive approach for the design of low power low voltage FA using CMOS and BBL was implemented by Piguet et al (1995), Piguet et al (1994). It is optimized for power dissipation using low power XOR gates (Wang et al 1994) by Hassoune et al (2010). However it suffers from weak driving capability for specific inputs which necessitates a CMOS inverter at the output.

3 21 Hassoune et al (2010) proposed an adder combining PT logic and BBL for sum and carry respectively. The logic styles used in this adder are simpler and their combination requires fewer transistors compared to CMOS FA and CPL FA (Hassoune et al 2010). However BBL-PT FA has high delay since gate of level restorer PMOS in sum block is driven by complement of output, resulting in step at output (Hassoune et al 2010). In this thesis the design of a new structure of hybrid FA combining Pseudo NMOS logic and PT is proposed and discussed in section 3.2 of chapter BCD Adder Decimal adder is an important component of ALUs designed for business and commercial applications. They are the key elements as they lie in the critical path and determine the overall performance of the system. Shirazi et al (1988) designed an adder for redundant BCD addition. Though the design involve simple conversion of a BCD number to redundant BCD and perform addition in redundant form and again convert the result back to BCD form, it suffers from high delay. In addition the conversion circuitry used, adds to the design complexity. Algorithms and adders for BCD addition are presented by Robert, and Schulte (2005) in which the design using speculative addition technique have regular structure and their correction unit is independent of the number of input operands whereas the other design using non-speculative addition have lower delays.

4 22 The use of reversible logic for the design of BCD adders was presented by (Babu and Chowdhury 2005)(Biswas et al 2008) (Ramkumar and Kittur 2012).The reversible logic adders perform well in terms of power dissipation and logic count; however it is prone to higher delay. In a pioneer work on BCD addition Veeramachaneni et al (2008) used multiplexer for the addition of correction bits. The circuit has lower delay compared to the architectures using adders for correction bit addition. Bayrakci and AhmetAkkas (2007) proposed a BCD adder with efficient carry generation using analyzer circuit. The circuit performs well in terms of delay compared to architectures mentioned in literature and shows better area performance. AnshulSingh et al (2009) designed a novel architecture for BCD addition and subtraction. The design uses three major blocks viz., PG block, prefix block and the correction block and generates carry without any extra logic thus performing better in terms of area performance compared to the BCD adder in (Veeramachaneni et al 2008). ChetanKumar et al (2011) presented a unified architecture for BCD and binary addition. Though the circuit has lower delay compared to the architectures mentioned in literature the design of post correction circuitry poses problems for multi-bit operands. Sundaresan et al (2011) in a pioneer work on design of Reduced delay BCD adder using Carry Look Ahead(CLA) adder in the initial stage being followed by carry network and correction logic in the second and third stages. Though the circuit is fast compared to the architecture in (Chetankumar et al 2011), the use of CLA adder in the initial stage increases area cost.

5 23 Al-khaleel et al (2011) proposed a correction free BCD adder in which the input operands are split and added in two stages. Stage 1 adds the most significant three bits of a four bit BCD number and its result is passed to stage 2 and added with the LSB. The latency of the architecture is very less compared to the conventional and Thapliyal et al (2006) architectures. To further reduce power and latency in BCD addition, a new adder design using flagged binary addition technique (Dave et al 2010) is proposed and discussed in section 3.3 of chapter 3 in the thesis. 2.3 MULTIPLIERS As a next part of the work, low power and high speed multiplier designs is carried out in chapter 4. As switching and critical computation of a multiplier is more compared to other arithmetic units in datapath of a processing architecture, an investigation of various multipliers was carried out to reduce latency and power dissipation of a processing system. Various architectures and algorithms for multiplication were proposed to till date include parallel multiplier using iterative algorithm by Hoffman et al (1968), Burton and Noaks (1968). However it increases the area overhead as Ripple Carry Adders (RCAs) are replaced with Carry Save Adders (CSAs). Mori (1969) proposed a multiplier architecture using Wallace s and Dadda s solution. Though the generation of partial products occurs in parallel, the use of RCA circuits for partial product accumulation increases the overall delay. Guilt (1969) had proposed a combinational circuit using Hoffmann logic for generation and accumulation of partial products. The speed of the architecture is high, however the complexity of circuit increases when the design is extended for higher bit multiplication.

6 24 Baugh and Wooley (1973) and Hwang (1979) had proposed architectures for multiplication of numbers in two s complement form. Though the algorithm is fast for both unsigned and two s complement multiplication, the use of carry save adders increases the complexity of the design. High speed low power array multipliers were proposed by MahantShetti et al (1999) and Pekmestzi (1999). The multiplier proposed by MahantShetti et al (1999) is a regular structure array multiplier based on tiled structure. Though the architecture is simple and easy to design, it has poor area performance as the number of cells grows at O(n 2 ) for an n X n multiplication. Also the delay associated with the multiplier is directly proportional to the number of bits in multiplier and multiplicand. The multiplier in (Pekmestzi 1999) uses multiplexers for partial product generation which reduces delay compared to the architecture in (Mahant Shetti et al 1999). However the irregularity of tree structure limits its efficient VLSI realization. Cornetta and Cortadella (2001) proposed a parallel multiplier based on Baugh-Wooley algorithm. The use of counter array for partial product reduction makes it suitable for high speed applications. However, it is prone to little error in the final product as the outputs of counter are speculated.

7 25 Choi and Song (2001) in a novel work proposed a parallel multiplier using Booth algorithm which generates regular partial product array with fewer partial product rows, lowering the complexity in partial product reduction and has smaller delay. However, the Booth encoder circuitry has a race problem due to the unbalanced paths from input to output, leading to higher power consumption. Efficient parallel multiplier designs were proposed in (Yeh and Jen 2000) and (Kang and Gaudiot 2006) using Booth algorithm which reduces partial product generation to half the rows. This reduces hardware circuitry and power dissipation however, the sign extension prevention and negative encoding necessitates the additional compensation bias circuitry which increases the hardware complexity. Kuang et al (2009) proposed a parallel multiplier based on Modified Booth algorithm. The architecture produces regular partial product array which is has one row of partial product less compared to the previous architectures (Choi and Song 2001), (Yeh and Jen 2000), (Kang and Gaudiot 2006) and shows good performance in terms of delay and power dissipation. Multipliers proposed in chapter 4 uses ET concept (Zhu et al 2010) for partial product accumulation which reduces delay due to carry propagation and folding technique (Parhi 2009) for area reduction. 2.4 TRUNCATED MULTIPLIERS In communication applications for an n X n multiplication only n bits are required at the output for ease of processing and transmission. Multipliers suitable for these applications have to produce most n significant bits in the final product. The least n significant bits are omitted using the concept of truncation and rounding such that the error is kept minimum.

8 26 A fixed width multiplier using constant correction and condition correction algorithms was proposed by Lim (1992).The circuit performs better in terms of error, however it requires additional hardware for generation of compensation bias which increases circuit complexity. Schulte and Swartzlander (1993) designed a fixed width multiplier by adding a constant correction bias to minimize error due to quantization of product. The circuit is hardware efficient, as the logic used for compensation bias generation is simple and limits the error within one LSB of the rounded product. However, the distribution of absolute error tends to be asymmetric making it unsuitable for multimedia applications. Kidambi et al (1996) designed a fixed width multiplier by truncating the LSBs and adding a compensation value of 1 to the least bit of the product considered. Though the circuit fair better in terms of area and speed, the overall error is high. Fixed width multipliers for signed and two s complement numbers were designed by Jou et al(1999). The architectures show good performance in terms of absolute error and power dissipation compared to Schulte and Swartzlander (1993) multiplier, however the design of compensation circuit poses difficulties as the hardware complexity of carry generation circuit increases in proportion with the number of bits truncated. A fixed width multiplier for DSP applications was proposed by Jou et al (2000). Since the circuit uses statistical tools to estimate the compensation bias for elimination of least significant n bits of the product in a n X n multiplication, it performs well in terms of mean error. However the architecture is prone to maximum absolute error in some cases.

9 27 Stine and Duverne (2003) proposed a fixed width multiplier using Constant Correction Truncation (CCT) and Variable Correction Truncation (VCT) algorithms. The architectures demonstrates better performance in terms of area cost and power dissipation, however the choice of compensation function introduces maximum absolute error in some cases, as it is determined based on probabilistic estimates. Fixed multiplier designs (Cho et al 2004), (Juang and Hsiao 2005) use modified booth algorithm for generation of partial products. The circuits perform better in terms of speed and error, however the distribution of error tends to be unsymmetrical. In case of processing applications which need iterations, the designs (Cho et al 2004), (Juang and Hsiao 2005) are not suitable as the accumulation error tends to be high. Van and Yang (2005) proposed a fixed width multiplier using Baugh-Wooley algorithm for partial product generation. Though the circuit gives little mean and mean square error, the hardware complexity of compensation circuit design increases with the number of most significant columns preserved in least part. In another pioneer work, Petra et al (2011) designed a fixed width multiplier based on linear compensation function. The architecture gives better trade off between area and accuracy, but estimation of compensation function and its hardware realization poses cost overhead. A truncated multiplier using deletion, reduction and rounding of partial product bits was proposed by Ko and Hsiao (2011). The design limits the average error to be within 1 LSB of truncated product and has less delay compared to the previous designs. Chapter 5 of the thesis concentrates on the design of reduced area truncated multipliers.

10 COUNTERS As counters act as important building blocks of fast arithmetic circuits used for frequency division, shifting operation, digital alarm clock, computer memory pointer, radio monitoring, electronic gadgets, Analog to Digital Conversion(ADC) etc., (Alioto et al 2006) (Lutz and Jaysima 1996) (Hafeez et al 2008) (Yamamoto and Fujishima 2004) (Ercegovac and Lang 2004) the research is focussed on the design of fast and efficient counter in chapter 6. As speed, power consumption and area requirements of counter are specific demands of present VLSI systems an investigation of various counter architectures are carried out. Various design techniques for up/down counter is discussed by Stan et al (1998), Evans (1986), Stan (1997) and parallel counter designs by Swartzlander (2004), Eby (1990) and Lin et al (1999). Yuan (1988) designed counter using look-ahead technique (Parhi 2009)in the carry propagation path. However, the use of large fan-in gates, limited the maximum operating frequency. A simple implementation of ripple counter was stated by Chu (1988). The drawback is that the asynchronous operation of such a counter creates problem in reading the value (because the whole counter has to be stable) and limits the maximum counting rate, especially for large counters (Ercegovac and Lang 1989). However the conventional synchronous counters can minimise the above problem but suffers from high complex logic design when the size of the counter increases, which limits the counting rate. A pipelined counter design using carry signals for exciting higher order count modules was proposed by Vuillemin (1991). However the delay

11 29 of half adders in the carry path and propagation delay of D FF limits the maximum frequency of operation. Larsson and Yuan (1993) proposed a high speed synchronous counter using efficient carry propagation circuit (Yuan and Svensson 1989). The operating frequency of the design is better compared to the Yuan (1988) architecture and the fan-in of AND gates are limited to two. However the extra backward circuit added in the design increases the area cost. High speed architecture for parallel counting was proposed by Kondo and Watnaba (1996) using carry select signal (AND of carry out signal) for enabling subsequent sections. Though the operating frequency of the design is better, it incurs high hardware complexity due to usage of more number of adders in modules at higher end. A high speed counter with better operating frequency was proposed by Hoppe et al (1998) with Johnson counter (MorrisMano 2001)in basic counting module used for generation of LSBs. The major limitation of the Hoppe et al (1998) design is lack of synchronization between basic module and higher count modules at high frequencies. To improve operating frequency Hafeez and GordonRoss (2011) designed a pipelined architecture for counter using D FFs. State look-ahead technique (Hendry 1996) is used for exciting higher counter modules from the basic module outputs. The circuit is suitable for high operating frequencies, however it suffers from more hardware complexity for large values of n. In another novel counter design by Kakarountas et al (2003), systolic counter (Stan 2004) modules are used and connected using D FFs. The triggering from one counter module to other is achieved using carry look ahead circuit proposed by Yuan (1988). Though the operating frequency of

12 30 the design is high it is not suitable for higher bit widths as the carry chain design increases hardware complexity. Chapter 7 of the thesis discusses about the design of high speed low power counter using pipelining.