Architecture Design and Validation Methods

Transcription

1 Architecture Design and Validation Methods

2 Springer-Verlag Berlin Heidelberg GmbH

3 Egon Börger (Ed.) Architecture Design and Validation Methods With 175 Figures, Springer

4 Editor Prof. Dr. Egon Börger Universita di Pisa Dipartimento di Informatica Corso Italia Pisa, Italy Library of Congress Cataloging-in-Publication Data Architecture design and validation methods / Egon Börger (ed.) p.cm. Includes bibliographical references. ISBN x I. Computer architecture. 2. Integrated circuits-very large scale integration Design and construction. I. Börger, E. (Egon), QA76.9.A73A '2-dc ACM Computing Classification (1998): B.1-2, B.6-7 ISBN ISBN (ebook) DOI / This work is subject to copyright. All rights are reserved, whether tbe whole or part of the material is concemed, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilm or in any otber way, and storage in data banks. Duplication of tbis publication or parts thereof is permitted only under the provisions of the German copyright law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer-Verlag. Violations are liable for prosecution under tbe German Copyright Law. Springer-Verlag Berlin Heidelberg 2000 Originally published by Springer-Verlag Berlin Heidelberg in 2000 Softcover reprint of the hardcover 1 st edition 2000 The use of general descriptive names, trademarks, etc. in this publication does not imply, even in tbe absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. Cover design: Künkel + Lopka, Heidelberg Typesetting: Camera-ready copy from the autbors using aspringer TEX macro package Printed on acid-free paper SPIN: /3142 GF

5 Preface This book grew out of material which was taught at the International Summer School on Architecture Design and Validation Methods, held June 23-July 5, 1997, on the Island of Lipari and directed to graduate students and young researchers. Since then the course notes have been completely elaborated and extended and additional chapters have been added so that this book offers a comprehensive presentation of the state of the art which leads the reader to the forefront of the current research in the area. The chapters, each of which was written by a group of eminent specialists in the field, are self-contained and can be read independently of each other. They cover the wide range of theoretical and practical methods which are currently used for the specification, design, validation and verification of hardware/software architectures. Synthesis methods are the subject of the first three chapters. The chapter on Modeling and Synthesis of Behavior, Control and Data Flow focusses on techniques above the register-transfer level. The chapter on Cell-Based Logic Optimizations concentrates on methods that interface logic design with physical design, in particular on techniques for cell-library binding, the back-end of logic synthesis. The chapter on A Design Flow for Performance Planning presents new paradigms for iteration-free synthesis where global wire plans for meeting timing constraints already appear at the conceptual design stage, even before fixing the functionality of the blocks in the plan. Design validation and verification is covered by two complementary approaches. The chapter on Test and Testable Design explains methods for generating test patterns which can already be supported in the design phase, in particular, built-in self-test techniques. The chapter on Machine Assisted Verification presents fully mechanized methods for the verification of combinational circuits at the gate and word level, for equivalence properties of sequential machines and for processor architectures at the instruction-set and algorithmic register-transfer level. High-level design approaches are discussed in the chapter on Models of Computation for System Design, which introduces in particular the novel concept of Co-Design Finite State Machines. The Abstract State Machine technique is applied in the chapter on Modular Design for the Java Virtual Machine Architecture, which provides a method for an on-the-fly verifiable platform-independent design of an instruction-set architecture. We are confident that not only the graduate students and young researchers but also the experts in architecture design will find this book useful. Pisa, January 2000 Egon Borger

6 Contents Modeling and Synthesis of Behavior, Control and Data Flow Raul Camposano, Andrew Seawright, Joseph Buck 1 Introduction Behavioral Synthesis High-Level Control Data Flow Conclusion References Cell-based Logic Optimization Giovanni De Micheli 1 Introduction Problem Formulation and Analysis Algorithms for Library Binding Boolean Matching Generalized Matching Conclusion References A Design Flow for Performance Planning: New Paradigms for Iteration Free Synthesis Ralph H. J. M. Otten 1 Introduction Flow Components Layout Synthesis Placement Versus Floorplan Design Global Wires Wire Planning Gate Sizing Conclusions References Test and Testable Design Hans-Joachim Wunderlich 1 Introduction Defect Analysis and Fault Modeling External Testing Self-Testable Systems-On-Chip References

7 VIII Contents Machine Assisted Verification Hans Eveking 1 Introduction Logic Verification Bit-Vector and Word-Level Verification Verification by Fixed-Point Calculations Verification Techniques for Bounded State Sequences Formally Correct Construction of Pipelined Systems References Models of Computation for System Design Luciano Lavagno, Alberto Sangiovanni- Vincentelli, and Ellen M. Sentovich 1 Introduction MOCs: Basic Concepts and the Tagged Signal Model Common Models of Computation Codesign Finite State Machines Conclusions References Modular Design for the Java Virtual Machine Architecture Egon Borger and Wolfram Schulte 1 Introduction The Trustful Virtual Machine The Defensive Virtual Machine The Diligent Virtual Machine The Dynamic Virtual Machine Related and Future Work The JVM Abstract State Machine References

8 List of Contributors Egon Borger Universita di Pisa Dipartimento di Informatica Pisa, Italy Joseph Buck Synopsys, Inc. 700 East Middlefield Road Mountain View, CA Raul Camposano Synopsys, Inc. 700 East Middlefield Road Mountain View, CA Giovanni De Micheli Computer Systems Laboratory Stanford University Stanford, CA Hans Eveking Dept. of Electrical and Computer Engineering Darmstadt University of Technology Merckstrasse Darmstadt, Germany Luciano Lavagno Politecnico di Torino Corso Duca degli Abruzzi Torino, Italy Ralph H.J.M. Otten Eindhoven University of Technology Faculty of Electrical Engineering P.O. Box MB Eindhoven The Netherlands Alberto Sangiovanni-Vincentelli University of California Berkeley Berkeley, CA Wolfram Schulte Microsoft Research Foundations of Software Engineering One Microsoft Way Redmond, WA Andrew Seawright Synopsys, Inc., 700 East Middlefield Road Mountain View, CA Ellen M. Sentovich.Cadence Berkeley Laboratories, 2001 Addison Street Berkeley, CA Hans-Joachim Wunderlich Dept. of Computer Science University of Stuttgart Breitwiesenstrasse Stuttgart, Germany