13700DF 13 Gbps D Flip-Flop Data Sheet

Transcription

1 13700DF 13 Gbps D Flip-Flop Data Sheet Applications High-speed (up to 13 GHz) digital logic High-speed (up to 13 Gbps) serial data transmission systems Broadband test and measurement equipment Features Supports data rates up to 13 Gbps Output signal swing 1200 mvpp differential Fast rise and fall times: 15 ps Single 3.3 V power supply Low power consumption: 300 mw Available as die or in LGA package Supports single-ended and differential operation Evaluation board available Description The 13700DF static D flip-flop (DFF) is designed to support data rates up to 13 Gbps. The part is nominally positive-edge triggered; however, by reversing the connections to the positive and negative clock inputs, a negative-edge triggered application can be accommodated. All differential data and differential clock inputs are DC coupled and terminated on-chip with 50 Ω resistors to ground (). For direct-coupled applications, the differential data outputs should be terminated off chip with 50 Ω resistors to. For applications requiring termination to DC levels other than, external AC coupling to a good RF ground is required. See the application note for various termination examples. The 13700DF operates from a single 3.3 V power supply and dissipates only 300 mw (typical). The 13700DF is available in a ceramic land grid array (LGA) package or in die form. The packaged part is also available on an evaluation board with SMA connectors DF_DS_Ver3.3 Inphi Proprietary Page 1 of 14

2 Block Diagram 50 Ω 50 Ω 60 Ω 60 Ω DINp DINn D Dn Q Qn DOUTp DOUTn 50 Ω 50 Ω CLKINp CLKINn CK CKn Absolute Maximum Ratings Stresses beyond those listed here may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the Operating Conditions and Electrical Specifications of this datasheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Symbol Conditions Min Max Unit Power Supply Voltage V EE V Input Signals (Data & Clock) 2 +1 V Output Signals 2 +1 V Junction Temperature Die T J C Case Temperature Package paddle T C C Shipping/Storage Temperature T STORE C Humidity RH % ESD Protection (Human Body Model) ESD Clock and Data inputs V Data outputs V Power Supply V Operating Conditions Parameter Symbol Conditions Min Typ Max Unit Power Supply Voltage VEE ± 5% Tolerance V On-Chip Power Dissipation PD mw Power Supply Current IEE ma Operating Temperature (Junction) Die TJ C Operating Temperature (Case) Package TC C Thermal Resistance junction to paddle RJC (θjc) Bottom of paddle C/W DF_DS_Ver3.3 Inphi Proprietary Page 2 of 14

3 Electrical Specifications! WARNING To prevent damage to the part: DC power must be turned off prior to connecting or disconnecting any cables. Electrical specifications guaranteed when the part is operated within the specified operating conditions. Parameter Symbol Conditions Min Typ Max Unit Maximum Data Rate BER (NRZ format) 13 Gbps Maximum Clock Frequency f MAX GHz Minimum Clock Slew Rate S MIN At CLKINp/CLKINn crossing V/ns Input High Level (Data & Clock) V IH V Input Low Level (Data & Clock) V IL V Input Amplitude (Data & Clock) Input Return Loss (Data) 1 VIN pp, Differential peak-to-peak mvpp VCLK pp Single-ended peak-to-peak mvpp RL IN < 13 GHz and Input common mode (V ICM ) db Input Return Loss (Clock) 1 RL CLK < 13 GHz db Clock Phase Margin CPM V IH +0.3V deg V IH > +0.3V deg Data Output Amplitude 2 D OUT Differential peak-to-peak mvpp Output High Voltage V OH DC coupled, referenced mv Output Common Mode V OCM DC coupled, referenced mv Output Rise/Fall Time t r /t f 20 80% ps Output Return Loss 3 RL OUT < 13 GHz db Deterministic Jitter 4, 5 J D Peak-to-peak ps Random Jitter 4, 5 J R RMS ps Clock to Data Output Delay 4, 6 Set-up & Hold Time 6, 7 (at package pins) Notes: t Q t SU & t Hld Die ps Packaged V IH +0.3V 9 7 ps V IH > +0.3V 11 7 ps 1 Inputs are designed to be a broadband match to 50 Ω impedance and are terminated with a 50 Ω resistor to. 2 Outputs are CML. Values are based on DC measurements. 3 Outputs are designed to be a broadband match to 50 Ω impedance and are terminated with a 60 Ω resistor to. 4 Valid when clock-to-data phase is near center of CPM window. 5 It should be noted that because the random and deterministic jitter of Inphi's high-speed logic parts are "in the noise" of the measurement techniques used, these specifications are conservative. The deterministic jitter (J D ) specified above is actually the peak-to-peak total jitter measured using a PRBS data pattern. The random jitter (J R ) is the RMS jitter measured on a pattern. The jitter (random and deterministic) of the source and measurement equipment was not removed from the measurement data used to derive the above specifications. 6 Values based on design simulations. 7 The setup and hold time specifications were determined from phase margin measurements and the assumption, supported by simulation, that Set-up and Hold times are equal to within a picosecond. See timing diagram on page 4 for definition DF_DS_Ver3.3 Inphi Proprietary Page 3 of 14

4 Timing Diagram DIN = DINp - DINn CLKIN = CLKINp - CLKINn 50% 50% 1/f CLK DOUTn DOUTp t Q 80% % t f 20% 80% t r Set-up and Hold Time Definition Truth Table Inputs Outputs DIN k-1 CLKIN DOUTp k DOUTn k L L H H H L Notes: DIN = DINp DINn CLKIN = CLKINp CLKINn H L Denotes a HIGH voltage level Denotes a LOW voltage level Denotes a rising clock transition DF_DS_Ver3.3 Inphi Proprietary Page 4 of 14

5 Typical DC Operating Characteristics 105 Supply Current versus Supply Voltage with Temperature as a Parameter 0.69 OUTP Amplitude versus Supply Voltage with Temperature as a Paramater Supply Current (ma) C 25 C 85 C Power Supply (V) Figure 1. Power supply current vs. power supply voltage OUTP Amplitude (V) C 25 C 85 C Supply Voltage (V) Figure 2. Single-ended, peak-to-peak output amplitude (on wafer) vs. power supply VOH (mv) Average VOH (>20 Devices) vs. Supply with Temperature as a Parameter VEE (V) VCM (mv) Average Common Mode (>20 Devices) vs. Supply with Temperature as a Parameter VEE (V) Figure 3. Single-ended, output high level (on wafer) vs. power supply Figure 4. Output common mode (on wafer) vs. power supply DF_DS_Ver3.3 Inphi Proprietary Page 5 of 14

6 Time Domain Operating Characteristics Figure 5. Output DOUTp (die on wafer); 12.5 Gbps, PRBS data pattern; 100 mv/div, 20 ps/div. Figure 6. Output DOUTp (LGA package); 12.5 Gbps PRBS data input; 100 mv/div, 17 ps/div OUTP Random Jitter versus Supply Voltage with Temperature as a Paramater 1.90 OUTP Deterministic Jitter versus Supply Voltage with Temperature as a Paramater Random Jitter (ps) C 25 C 85 C Deterministic Jitter (ps) C 25 C 85 C Supply Voltage (V) Supply Voltage (V) Figure 7. Output random jitter (on wafer) vs. Power Supply; Refer to note #3 under Electrical Specifications. Figure 8. Output deterministic jitter (on wafer) vs. Power Supply; Refer to note #3 under Electrical Specifications. OUTP Rise Time (ps) OUTP Rise Time versus Supply Voltage with Temperature as a Parameter C 25 C 85 C Supply Voltage (V) Figure 9. Output rise time (on wafer) vs. power supply OUTP Fall Time (ps) OUTP Fall Time versus Supply Voltage with Temperature as a Paramater Supply Voltage (V) C 25 C 85 C Figure 10. Output fall time (on wafer) vs. power supply DF_DS_Ver3.3 Inphi Proprietary Page 6 of 14

7 Clock to Data Phase Margin The clock to data phase margin is defined in degrees with 360 being a full period of the clock at 12.5 Gbps. It is measured by gradually adjusting the phase of the clock input relative to the data input and looking at the error rate of the D-Flip-Flop with a bit error rate tester.. As indicated in figure 11, the 13700DF s phase margin is large: typically 300. Clock Phase Margin (degrees) Clock Phase Margin versus Supply Voltage with Temperature as a Paramater: VIH= 0 V, VIL= -0.6 V Supply Voltage (V) Figure 11. Clock phase margin vs. operating conditions at 12.5 Gbps. Set-up and Hold Times Direct measurement of the set-up and hold times is difficult because it involves accurately measuring the electrical delay of the clock and input from signal generators to the package pins and knowledge of the phase between the two signals at their respective generators. Since simulations indicate that the set-up and hold times are equal to within a picosecond, they can be determined from the phase margin. Since the phase margin is typically 300, the typical set-up and hold times are one half of 60 /360 times 80 ps, or 6.7 ps DF_DS_Ver3.3 Inphi Proprietary Page 7 of 14

8 Typical Return Losses All S-parameter measurements were made single-ended. S-parameters for the packaged part are not given here due to the unavailability of calibration standards for the evaluation board. S11 (db) S11 vs. Frequency (25 C, 3.3 V), 0.0 V Data Input; N= Frequency (GHz) Figure 12. Data Input S11 vs. frequency of 33 die on wafer at V EE = -3.3 V and 25 C; Input common mode = 0 V S11 (db) S11 vs. Frequency, 0.0 V Data Input, All Conditions, Die # Frequency (GHz) C 3.5 V C 3.3 V C 3.1 V 25 C 3.5 V 25 C 3.3 V 25 C 3.1 V 85 C 3.5 V 85 C 3.3 V 85 C 3.1 V Specification Figure 13. Data Input S11 vs. frequency of one dice on wafer at V EE = -3.3 V and 25 C; Input common mode = 0 V S11 (db) S11 vs. Frequency (25 C, 3.3 V), 0.0 V Clock Input; N= Frequency (GHz) Figure 14. Clock Input S11 vs. frequency of 33 die on wafer at V EE = -3.3 V and 25 C; Input common mode = 0 V S11 (db) S11 vs. Frequency, 0.0 V Clock Input, All Conditions, Die # Frequency (GHz) C 3.5 V C 3.3 V C 3.1 V 25 C 3.5 V 25 C 3.3 V 25 C 3.1 V 85 C 3.5 V 85 C 3.3 V 85 C 3.1 V Specification Figure 15. Clock Input S11 vs. frequency of one dice on wafer at V EE = -3.3 V and 25 C; Input common mode = 0 V S22 (db) S22 vs. Frequency (25 C, 3.3 V), DC-Coupled, Logic Low; N= Frequency (GHz) Figure 16. Data Output S22 vs. frequency of 33 die on wafer at V EE = -3.3 V and 25 C; Output in logic low state; Add 3dB margin for logic high state. S22 (db) S22 vs. Frequency, DC Logic Low Out, All Conditions, Die # Frequency (GHz) C 3.5 V C 3.3 V C 3.1 V 25 C 3.5 V 25 C 3.3 V 25 C 3.1 V 85 C 3.5 V 85 C 3.3 V 85 C 3.1 V Specification Figure 17. Data Output S22 vs. frequency of one dice on wafer at V EE = -3.3 V and 25 C; Output in logic low state. Add 3dB margin for logic high state DF_DS_Ver3.3 Inphi Proprietary Page 8 of 14

9 Die Pad Layout 1 V EE 24 V EE V EE 20 V EE mm DINn 3 DINp 4 DOUTp 16 DOUTn ± 5 µm (4 sides) 6 7 CLKINp 8 CLKINn 9 10 V EE 11 V EE mm Notes: 100 µm pads on 150 µm pitch 150 ± 10 µm die thickness Name Pad Description Function DINp 4 Non-inverting Data Input Input DINn 3 Inverting Data Input Input CLKINp 8 Non-inverting Clock Input Input CLKINn 9 Inverting Clock Input Input DOUTp 16 Non-inverting Data Output Output DOUTn 15 Inverting Data Output Output 1, 2, 5, 6, 7, 10, 13, 14, 17, 18, 21,22 Ground Supply V EE 11, 12, 19, 20, 23, 24 Power Supply: Connect to 3.3 V Supply DF_DS_Ver3.3 Inphi Proprietary Page 9 of 14

10 Die Pad Locations For dimensioning purposes, reference origin (0,0) is the lower left corner of the lower left pad. Pad # Signal Name Pad Lower Left Corner X Y DINn DINp CLKINp CLKINn V EE V EE DOUTn DOUTp V EE V EE V EE V EE DF_DS_Ver3.3 Inphi Proprietary Page 10 of 14

11 LGA Pin Assignment Name Pin Description Function DINp 3 Non-inverting Data Input Input DINn 5 Inverting Data Input Input CLKINp 26 Non-inverting Clock Input Input CLKINn 24 Inverting Clock Input Input DOUTp 17 Non-inverting Data Output Output DOUTn 19 Inverting Data Output Output 2, 4, 6, 9, 12, 13, 16, 18, 20, 21, 23, 25, 27, Paddle Ground Supply V EE 10, 11, 22 Power Supply: Connect to 3.3 V Supply NC 1, 7, 8, 14, 15, 28 Not Connected NC DF_DS_Ver3.3 Inphi Proprietary Page 11 of 14

12 LGA Package Outline Drawing Top View Side View Bottom View DF_DS_Ver3.3 Inphi Proprietary Page 12 of 14

13 Order Information Part No DF-S02D 13700DF-S02L 13700DF-S02LEVB Description 13 Gbps D Flip-Flop ( 3.3 V Supply) Die 13 Gbps D Flip-Flop ( 3.3 V Supply) in LGA Package 13 Gbps D Flip-Flop ( 3.3 V Supply) in LGA Package on an Evaluation Board with SMA Connectors Contact Information Inphi Corporation 2393 Townsgate Road, Suite 101 Westlake Village, CA Phone: (805) Fax: (805) products@inphi-corp.com Visit us on the Internet at: For each customer application, customer s technical experts must validate all parameters. Inphi Corporation reserves the right to change product specifications contained herein without prior notice. No liability is assumed as a result of the use or application of this product. No circuit patent licenses are implied. Contact Inphi Corporation s marketing department for the latest information regarding this product. Qualification Notification The 13700DF-S02 is fully qualified. Please contact Inphi for the qualification report. Inphi Corporation will honor the full warranty as outlined in Section 5 of Inphi s Standard Customer Purchase Order Terms and Conditions DF_DS_Ver3.3 Inphi Proprietary Page 13 of 14

14 Version Updates: From Version3.0 to 3.1 (dated 11/07/2005): 1. Changed Rise/Fall time reference from <25 ps to 15 ps typical in the Features section on page Added the ESD specifications to the Absolute Maximum Specifications table on page Changed the notes in the Electrical Specifications section on page 3: a. Added Values are based on DC measurements. to note #1. b. Added note #3 3 It should be noted that because the random and deterministic jitter of Inphi's high speed logic parts are "in the noise" of the measurement techniques used, these specifications are conservative. The deterministic jitter (J D ) specified above is actually the peak-to-peak total jitter measured using a PRBS data pattern. The random jitter (J R ) is the RMS jitter measured on a data pattern. The jitter (random and deterministic) of the source and measurement equipment was not removed from the measurement data used to derive the above specifications. 4. Reformatted and added new graphs to the Typical Operating Characteristics section on pages 5 & Added s-parameter graphs and notes tot the Typical Return Losses section on page Changed the Limited Qualification Notification section on page 12 to indicate fully qualified. From Version 3.1 to 3.2 (dated 6/28/2006): 1. Fixed minor typographical errors. 2. Absolute Maximum table (page 2): a. Changed Input Signals maximum level from +0.6 to +1 V. b. Changed Output Signals minimum level from 1.5 to -2 V. 3. Added Thermal Resistance to Operating Conditions table (page 2). 4. Electrical Specifications table (page 3): a. Added Setup and Hold Time parameters with specs. b. Added notes 1, 3, 6 & 7. c. Changed note numbers on parameter descriptions. 5. Added the Setup and Hold Time diagram to the Timing Diagram section (page 4). 6. Added the Clock Phase Margin section (page 7). 7. LGA Package Outline Drawing (page 11): replaced the old drawing with a new drawing. The package height was incorrect (corrected from 60 mils to 66 mils). 8. Qualification Notification section: a. Added the statement that the device is radiation tolerant. From Version 3.2 to 3.3 (dated ): 1. Removed radiation tolerance statement in Qualification Notification section (page 14) DF_DS_Ver3.3 Inphi Proprietary Page 14 of 14