ENEE 359a Digital VLSI Design

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1 SLIDE 1 ENEE 359a Digital VLSI Design : Conventions, Problems, Solutions Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides (PSU), Schmit & Strojwas s slides (CMU), Dally s EE273 slides (Stanford), Wolf s slides for Modern VLSI Design, and/or Rabaey s slides (UCB). Asynchronous circuits: Erik Brunvand.

2 SLIDE 2 Overview Motivation: What Needs To Be Done? (and Why It Matters) (Elmore primer) Timing Conventions Synchronous & Source-Synchronous Self-Timed Circuits Dealing with Problems of Global Clocks Balanced Trees The Wonderful World of DLLs/PLLs

3 What Needs To Be Done? SLIDE 3 Clk SRC By the way: global clock scheme

4 SLIDE 4 Background: Elmore Delays τ Di = N k = 1 C k R ik N 3 R 4 C4 N 4 R 3 C 3 Clk SRC R 1 N 1 N 2 C1 R 2 C2

5 SLIDE 5 Background: Elmore Delays τ Di = N k = 1 C k R ik 1 τ D3 = 6 τ D4 = 7 C 1 + C 2 + 2C 3 + 2C C 1 + C 2 + 2C 3 + 3C 4 1 τ D1 = 4 τ D2 = 5 Clk SRC 1 1 C 1 + C 2 + C 3 + C C 1 + 2C 2 + C 3 + C 4

6 End Result: Clock Skew SLIDE 6 1 time unit Clk SRC In general, even nearby clocks not in synch

7 Idea: Detect 0 vs. 1 D Data D SLIDE 7 Clock V 1 This is a 1 t bit V 0 V 1 t bit V 0 This is a 0 V eye V 1 t eye V 0 EYE: space between 1 & 0

8 Basic Problem: Voltage Noise D Data D SLIDE 8 Clock V eye Data signal with t eye voltage noise Clock signal with voltage noise Voltage noise reduces operating margins

9 Basic Problem: Timing Noise D Data D SLIDE 9 Clock t eye V eye Data signal with timing noise Clock signal with timing noise Timing noise reduces operating frequency

10 Basic Problem: Both D Data D SLIDE 10 Clock t eye V eye Data signal with both noise sources Clock signal with both noise sources Note: Clock signal is just another signal subject to same constraints of voltage noise, skew and jitter as data signals

11 Eye Diagram SLIDE 11 Yes, there really is that much voltage noise; Yes, there really is that much timing noise Life sucks; deal with it.

12 SLIDE 12 Definitions: Skew clock - clock skew Sub Channel 1 Sub Channel 2 data - data skew - Static timing displacement from ideal design - Caused by differences in signal path characteristics - Total timing budget must take data-data skew, data-clock skew as well as clock-clock skew into cycle budget consideration

13 Definitions: Jitter SLIDE 13 - Dynamic timing displacement from nominal timing characteristics - Magnitude and offset of timing displacement could depend on: previous signal state(s), current signal state(s), supply voltage level(s), crosstalk, variations in thermal characteristics. Perhaps even phases of the moon (not proven).

14 Cycle Budget t tran t skew t eye SLIDE 14 t cycle t skew = max(skew) + max(jitter) t tran = Edge transition time = max(rise_time, fall_time) t eye t cycle t tran t skew

15 SLIDE 15 Timing: Clock Data Define when a value is present on a line How many 1 s? How many 0 s? Need convention to distinguish where one 1 ends and next 1 begins conventions typically mark boundaries w/ TRANSITIONS of the signal itself of an associated clock signal (original definition of synchronous ) Uncertainty in timing limits operating speed

16 Timing Conventions SLIDE 16 Apply to both inter- and intra-chip signaling

17 SLIDE 17 Setup Time Required time for input to be stable BEFORE CLOCK EDGE

18 Setup Time Fix SLIDE 18

19 Setup Time Fix II SLIDE 19

20 SLIDE 20 Hold Time Required time for input to be stable AFTER CLOCK EDGE

21 Hold Time Violations SLIDE 21

22 SLIDE 22 Basic Timing Analysis Look for longest path: clock speed Look for shortest path: check hold time Difficult problem, e.g. False Paths

23 SLIDE 23 A Tale of Two (or more) Timing Conventions Synchronous: global clock Synchronous: source-synchronous I ( open-loop meaning no control loop) Synchronous: source-synchronous II ( closed loop meaning feedback control) Asynchronous: self-timed

24 SLIDE 24 System Building Blocks DELAY ELEMENTS Nominal delay Timing uncertainty, skew, jitter COMBINATIONAL LOGIC Contamination delay Propagation delay CLOCKED STORAGE ELEMENTS Align signal to a clock Signal waits to be sampled by clock Output held steady until next clock

25 SLIDE 25 Edge-Triggered Register Samples data on rising edge of CLK Data must remain valid during an aperture of time during sampling Output held steady until next CLK edge Output is held until a contamination delay following CLK edge Tcontamination Tpropagation Output has a correct value after a propagation delay following CLK edge

26 SLIDE 26 Other Storage Elements LEVEL-SENSITIVE LATCH Passes data through when enable (clock) is high Holds data stable when enable (clock) is low DUAL-EDGE-TRIGGERED FLIP-FLOP/REGISTER Samples data at both edges of the clock Internally two interleaved flip-flops (1 posedge FF + 1 negedge FF) Allows CLK to run at same speed as data

27 SLIDE 27 Eye Diagram, Redux MAXIMUM OPERATING RATE (i.e., signaling speed) LIMITED BY THREE FACTORS: t bit Tr Transition time (rise/fall time) Tu Timing uncertainty, skew, jitter Ta Aperture time Tbit Tr + Tu + Ta (but not that simple )

28 SLIDE 28 Synchronous Timing I GLOBAL CLOCK (Conventional) EXAMPLE 6.25ns ± 0.1ns Tx 8 data lines Rx B1 B4 B1 400MHz Matched Lines ± 0.1ns (1.5cm) B4 Parameter Symbol Nominal Skew Jitter Bit Cell (data period) Tbit 2.5 ns Transmitter Rise Time Tr 1.0 ns Cable Delay Twire 6.25 ns 100 ps Receiver Aperture Ta 300 ps 100 ps 50 ps Transmitter Delay 500 ps 150 ps 50 ps Buffer Stage Delay B# 250 ps 100 ps 50 ps

29 SLIDE 29 Synchronous Timing I Sources of uncertainty: Skew (across multiple lines) of line delay B1 B1 400MHz B4 Tx 6.25ns ± 0.1ns 8 data lines Matched Lines ± 0.1ns (1.5cm) B4 Rx Jitter of Tx, Rx, and line delay Skew and jitter of global clock (usually large due to high fan-out) For best performance, center sampling edge on data eye Ta = 300ps Tbit - Tr = 1.5ns Tbit = 2.5ns Margin = 600ps Gross timing margin = 1/2 [ Tbit - Tr - Ta] = ± 600ps = 1/2 Tu?

30 SLIDE 30 An Aside Why do we simply add up the uncertainties? And why does each effectively count twice? DATA w/ no skew/jitter CLOCK w/ no skew/jitter 1 time unit 1 time unit DATA early by 1 time unit CLOCK late by 1 time unit 2 time units

31 Synchronous Timing I SLIDE 31 TIMING ANALYSIS Clock Skew: 100ps lines + 100ps B ps B4 B1 B1 400MHz B4 Tx 6.25ns ± 0.1ns 8 data lines Matched Lines ± 0.1ns (1.5cm) B4 Rx Clock Jitter: 50ps B ps B4 [CLKs times 2: one for xmit, one for recv] Transmitter: 150ps skew, 50ps jitter Receiver: 100ps skew, 50ps jitter Data Cable: 100ps skew TOTAL: 1550ps skew, 600ps jitter (BAD)

32 Synchronous Timing I LIMITS TO LINE DELAY & DATA FREUENCY B1 B4 Tx 6.25ns ± 0.1ns 8 data lines Rx SLIDE 32 B1 Conventional Wisdom: 400MHz Line Delay Must Be ODD NUMBER of HALF-BITS WHY? Matched Lines ± 0.1ns (1.5cm) B4 0 half-bits For fixed line length and tight margins, this limits the bus speeds that can be used

33 Synchronous Timing I SUMMARY B1 B4 Tx 6.25ns ± 0.1ns 8 data lines Rx SLIDE 33 GLOBALLY SYNCHRONOUS DESIGN: B1 400MHz Matched Lines ± 0.1ns (1.5cm) B4 For long wires and high speeds, only a handful of frequencies work Impractical to control uncertainties Cannot switch frequencies

34 Synchronous Timing II PIPELINED TIMING: BASIC IDEA SLIDE 34 Delay the clock by the same amount as data PLUS half a bit-cell System will work from DC to maximum theoretical frequency 1/(Tr + Tu + Ta) Defines new clock domain at receiving end

35 SLIDE 35 Synchronous Timing II SOURCES OF UNCERTAINTY SKEW: Between CLK & Data line Fixed differences in FF, Tx, Rx delays Different CLK delays to different FFs Aperture offset in Rx FF Extra offset in the delayed CLK line JITTER: In Tx clock In FF, Tx, Rx delays

36 SLIDE 36 Synchronous Timing II OPEN-LOOP PIPELINED EXAMPLE Tx Rx 6.25ns ± 0.1ns Data In 8 data lines Sync Toggle 6.25ns ± 0.1ns RClk 90 B1 B4 B1 200MHz Lines need not be matched B4 Internal Clock Network

37 Synchronous Timing II SLIDE 37 TIMING ANALYSIS Xmit data: 150ps skew, 50ps jitter Data In Toggle B1 B4 Tx 6.25ns ± 0.1ns 8 data lines 6.25ns ± 0.1ns RClk 90 Rx Sync Internal Clock Network Xmit toggle: 150ps skew, 50ps jitter B1 200MHz Lines need not be matched B4 Receiver: 100ps skew, 50ps jitter Data cable: 100ps skew Toggle clock cable: 100ps skew TOTAL: 600ps skew, 150ps jitter (BETTER)

38 SLIDE 38 Synchronous Timing III CLOSED-LOOP PIPELINED EXAMPLE Tx Rx 6.25ns ± 0.1ns Data In 8 data lines Sync Toggle 6.25ns ± 0.1ns RClk B1 B4 FSM B MHz Lines need not be matched B4 To rest of receive chip Variable delay line can cancel ALL SKEW

39 SLIDE 39 Synchronous Timing III COMPONENTS of CONTROL LOOP (DLL) Ref. Clock (Input) Variable delay line (control) Delayed Clock (Output) Rx Sync Ref. Data/CK (Input) Phase Compare Loop Filter DFF as a Phase Comparator B D Y FSM A 90 Y PHASE AB

40 SLIDE 40 Synchronous Timing III TIMING ANALYSIS Xmit data: 50ps jitter Recv data: 50ps jitter Data In Xmit toggle: 30ps skew data/toggle (0?), 50ps jitter Toggle B1 B1 200MHz B4 Tx 6.25ns ± 0.1ns 6.25ns ± 0.1ns RClk Lines need not be matched 8 data lines B4 Rx Sync FSM 90 To rest of receive chip Recv toggle: 20ps skew (0?), 50ps jitter Data cable: 100ps skew Toggle clock cable: 100ps skew TOTAL: 250ps skew, 200ps jitter (GOOD!)

41 SLIDE 41 Synchronous Timing II & III LIMITS TO LINE DELAY & DATA FREUENCY None. Data In Toggle B1 B1 200MHz B4 Tx 6.25ns ± 0.1ns RClk Lines need not be matched 6.25ns ± 0.1ns 8 data lines B4 90 Rx Internal Clock Network Sync Only limiter to bus frequency is the rate at which you can successfully transmit & receive data (e.g. Taperture + Tuncertainty + Ttransmit) Data In Toggle B1 B1 200MHz B4 Tx 6.25ns ± 0.1ns 8 data lines 6.25ns ± 0.1ns RClk Lines need not be matched B4 Rx Sync FSM 90 To rest of receive chip

42 SLIDE 42 Asynchronous Timing Basic Idea: no clocks ADVANTAGES: Achieve average-case performance (good if difference between average & worst case is large) Consume power only when needed (i.e., only when actually processing data) Easy modular composition (designer focuses on local issues, not global issues) No clock alignment required (no expensive DLLs/PLLs) No clock distribution headaches (saves design time, power consumption, chip area) Robust in the face of parameter variations (e.g., temperature/voltage fluctuations, process variations) Global synchrony is a fallacy anyway! (i.e., face the problem head-on)

43 SLIDE 43 Asynchronous Timing SELF-TIMED CIRCUITS Worst-Case Delay: sets clock period in synchronous designs (time: N * max delay) D Clk D Clk D Clk t setup t pff t p t setup t pff t p t setup t pff t p MAX Average-Case Delay: asynchronous designs achieve it (time: delay 1 + delay 2 + delay 3 ) RE ACK Handshaking RE ACK Handshaking RE ACK Handshaking RE ACK t p t detect t p t detect t p t detect

44 SLIDE 44 Asynchronous Timing HANDSHAKING PROTOCOLS Four-Phase / RTZ / Level Signaling specific protocol determines data-release point RE ACK One transaction DATA Two-Phase / NRTZ / Transition Signaling RE ACK DATA One transaction Another transaction

45 SLIDE 45 Asynchronous Timing DATA SIGNALING Bundled Data: normal data wires, one per bit, with associated valid signal RE ACK Handshaking RE ACK Handshaking RE ACK Handshaking RE ACK DATA DATA VALID DATA DATA VALID DATA DATA VALID Dual-Rail Data: two wires per bit, encoded (00 = no data, 01 = 0, 10 = 1, 11 = error) ACK RE Handshaking ACK RE Handshaking ACK RE Handshaking RE ACK

46 SLIDE 46 Asynchronous Timing GOTCHA: Glitches on output (RE line) One Solution CRITICAL PATH REPLICAS Match the critical-path delay through the combinational logic block When a start signal indicates to begin processing, send signal through REPLICA DELAY block logic block is done processing when signal exits REPLICA DELAY Replica Delay Replica Delay Replica Delay Start Start Start RE ACK Start Handshaking RE ACK Start Handshaking RE ACK Start Handshaking RE ACK DATA DATA VALID DATA DATA VALID DATA DATA VALID t p t p t p

47 SLIDE 47 Asynchronous Timing GOTCHA: Glitches on output (RE line) Another Solution DUAL-RAIL CODING VDD VDD Start B0 B1 In1 & In1 In2 & In2 In3 & In3 Pull-down Network (nfet network) Pull-down Network (same topology) Start B0/B1 = 0/0 = no data B0/B1 = 0/1 = 0 B0/B1 = 1/0 = 1 B0/B1 = 1/1 = error

48 SLIDE 48 A Tale of Three Pipelines Asynchronous: self-timed Synchronous: global clock I ( normal design: unbalanced pipe) Synchronous: global clock II (intentionally skews clock to balance pipe, uses wave pipelining)

49 SLIDE 49 Asynchronous Pipeline RE ACK Handshaking RE ACK Handshaking RE ACK Handshaking RE ACK t p =20 t detect =1 t p =10 t detect =1 t p =30 t detect =1 Say best/worst case = 0.5 (e.g. best=10/5/15) On average, graduate one result every ( ) 2 time units (say ns): roughly every 23.5ns, for an effective speed of 43MHz Delay through pipe for single item = 33/63ns

50 Synchronous Pipeline I D Clk D Clk D Clk SLIDE 50 t latch =1 t p =20 t latch =1 t p =10 t latch =1 t p =30 MAX = 31ns Clock period = 31ns By design, graduate one result every 31ns, for an effective speed of 32MHz Delay through pipe for single item = 93ns

51 Synchronous Pipeline II D Clk D Clk D Clk D Clk SLIDE 51 t latch =1 t p =20 t latch =1 t p =10 t latch =1 t p =30 CLK 1 CLK 2 21ns 10ns neg. skew CLK 3 11ns CLK 4 31ns Clock period = 21ns; intentionally skew clock to register #3 to arrive 10ns early By design, graduate one result every 21ns, for an effective speed of 48MHz Delay through pipe for single item = 63ns

52 Synchronous Pipeline II D Clk D Clk D Clk D Clk SLIDE 52 t latch =1 t p =20 t latch =1 t p =10 t latch =1 t p =30 CLK 1 CLK 2 21ns 10ns neg. skew CLK 3 11ns CLK 4 31ns Clock period = 21ns; intentionally skew clock to register #3 to arrive 10ns early By design, graduate one result every 21ns, for an effective speed of 48MHz Note: This requires use of wave-pipelining design techniques on last combinational logic block very hard to do (probably much easier to do asynchronous design)

53 Global Clock I Transmitter Receiver D D 0 2 Data 3 5 SLIDE 53 1 Clock : Assume data is stable for setup time before clock edge 1: Rising edge of transmitter clock 2: Transmitter begins to drive data (perhaps through logic) 3: Signal reaches input of receiver. 4: Rising edge of receiver clock 5: Receiver latches data and drives internal signal lines 5

54 SLIDE 54 Global Clock II: Parallel Data Transmitter Receiver D D 2 Data 3 5 Clock Data 3 5 D D transmitter input transmitter clock transmitter output 0 & 0 1 & 1 2 & 2 receiver input receiver clock 3 & 3 4 & 4 receiver output 5 & 5 - Skew and jitter eats into timing budget - Luckily, uncertainty does not accumulate beyond latches

55 Clock Skew & Pipelines SLIDE 55 t l,min t r,min t l,max t r,max D Clk t i Clk D t ø t ø t ø D Clk Ø Clock edge timing depends upon position A clock line behaves as a distributed RC line Each register sees a local clock time depending on their distance from the clock source -> clock skew Ø skew = t ø t ø (> 0 or <0) Clock skew can severely affect the performance Note: we assumed here t setup =0

56 Constraints on Skew Ø t ø Ø skew t r,min + t l,min + t i Ø t ø = t ø + Ø skew SLIDE 56 R1 DATA R2 (a) Race between clock and data Earliest time If the local clock of R2 is delayed w.r.t. R1, it might happen that the inputs of R2 change before the previous data is latched -> race Ø skew t r,min + t i + t l,min Ø Ø skew Ø Ø + T t ø t r,max + t l,max + t i t ø + T = t ø + T + Ø skew R1 DATA R2 (b) Data should be stable before clock Worst case The correct input data is stable at R2 after the worst-case propagation delay. The clock period must be large enough for the computations to settle. T t r,max + t i + t l,max Ø skew

57 Clock Constraints in Edge-Triggered SLIDE 57 (1) Ø skew t r,min + t i + t l,min (2) T t r,max + t i + t l,max Ø skew Maximum Clock Skew Determined by Minimum Delay between Latches (condition 1) Minimum Clock Period Determined by Maximum Delay between Latches (condition 2)

58 SLIDE 58 Positive and negative Skew POSITIVE SKEW: D Clk D Clk D Clk Ø Clock routed in same direction as data The skew has to satisfy (1) If it violates (1), then the circuit malfunction independently of the clock period Clock period decreases!!! NEGATIVE SKEW: D Clk D Clk D Clk Clock routed in opposite direction as data Ø (1) is satisfied implicitly. The circuit operates correctly independently of the skew Clock period increases by Ø skew

59 Clock Tree I SLIDE 59 Every branch sees same wire length and capacitance The clock skew is theoretically zero Clock distribution is a major design problem! The sub-blocks should be small enough s.t. the skew within the block is tolerable Essential to consider clock distribution early in the design process

60 Clock Tree I SLIDE 60 An on-chip clock tree

61 Clock Tree II (I with buffers) SLIDE 61 buffer chips could have +/- xx% tolerance - Large synchronous systems require all components (chips or registers) to be driven by clock signal. - Clock signal paths and buffers could introduce both skew and jitter at each stage - Jitter and skew are additive with larger systems. More buffering, more skew and jitter.

DEC Alpha 21164 SLIDE 62 9.3 M Transistors, 4 metal layers, 0.55µm Clock Freq: 300 MHz Clock Load: 3.

62 DEC Alpha SLIDE M Transistors, 4 metal layers, 0.55µm Clock Freq: 300 MHz Clock Load: 3.75 nf Power in Clock = 20W (out of 50W) Two Level Clock Distribution: Single 6-stage driver at center Secondary buffers drive left and right side Max clock skew less than 100psec Routing the clock in the opposite direction Proper timing

63 Clock Skew in Alpha SLIDE 63

64 SLIDE 64 Dual Edge Clocking Data Clock - Only one edge of clock latches data - Duty cycle of clock signal is not relevent - Clock signal operating at 2X switching rate of data - Always a clock edge where you need one Data Clock - Both edges of clock used to latch in data - Duty cycle & rise/fall times of clock must be even - Clock signal must be phase shifted by 90 degrees relative to phase of data signal - How do you get 90 degrees??

65 Phase Locked Loop SLIDE 65 D VCO Freq/ Phase Loop Filter φ out - Given a data signal, recover the frequency and phase of the data signal, generate local reference clock φ out - Local reference clock may be frequency multiple of input clock - PLL depends on data input to provide enough signal transitions to lock onto, else PLL could lose coherency. - Modern processors utilize PLL s for frequency multiplication

66 Voltage Controlled Oscillator SLIDE 66 Ring Oscillator - VCO may be designed from ring oscillator where voltage controls the number of (odd) stages of inverters in the feedback ring L C(v) LC Oscillator (conceptual illustration) - VCO may be designed from resonant oscillator where voltage controls capacitance in LC circuit.

67 Delay Locked Loop SLIDE 67 D φ r Phase Comp φ Loop Filter φ out - Given a data signal and reference clock, compare and adjust phase of local clock signal by φ - Unlike PLL, requires reference clock - Hence, no need to recover clock signal with VCO - Modern DRAM with dual edged clocking utilizes DLL s for phase compensation. (gets you 90 degrees)

68 Zero-Skew Clock Distribution SLIDE 68 PLL or DLL

69 DLL in DDR SDRAM This represents a delay D of the clock signal from clock input pad to data output drivers D CK EXT CK Buffers CK EXT CK INT SLIDE 69 DRAM Array CMD READ D EXT CK INT Data D EXT Additional delay through D drivers Ideally, these two edges would be aligned This represents a delay D of the clock signal from clock input pad to data output drivers Delay DLL + D D Delay DLL The DLL delays the internal clock (CK INT ) so that the total delay equals one full clock cycle, and thus CK INT is now in sync with CK EXT thus, D EXT is also (roughly) in sync with CK EXT CK EXT Delay CK Buffers CK EXT Delay introduced by DLL CK INT DRAM Array CMD READ Filter D EXT Phase Comp CK INT Data D EXT Additional delay through D drivers These two edges now more closely aligned The Phase Comparison, Loop Filter, and Variable Delay components constitute a DLL