Low-overhead solutions for clock generation and synchronization.

Transcription

1 Low-overhead solutions for clock generation and synchronization. Monday, March 10/ 2003 A presentation in the series on ULSI Configurable Systems. Gord Allan PhD Candidate Carleton University

2 Outline Presentation Progress Ultra Large Scale (ULSI) Configurable Systems Adjustable Delay Elements A Pausable Numerically Controlled Oscillator (NCO) All digital Phase-Locked Loops and Frequency Synthesis Hybrid Analog and Digital Extreme Range PLLs Calibrated Delay Lines and DLLs Clock-Data Recovery (CDR) Single Cycle Acquisition PLLs Frequency Re-synthesis Phase Adjustment Skew Compensation High speed reconfigurable links

3 Ultra Large Scale Configurable Systems Architecture USB I/FFT ADC DAC Switch Cap Filters PLL DDFS FP FP Modulator FPGA Fabric Systolic Array FIRs FEC ARM ARM ARM DMA IIRs Cryto up Peripherals Interface ARM DMA Cache Cache Local Storage Cache... System Memory Our architecture: Many sub-systems on a chip/board. Subsystems are fully isolated from oneanother IO is configured via software. On demand system configuration and processing. Timing Issues FPGA Subsystems operate on independent clocks. -Low overhead clock generation. Communications reequire fault-tolerant, high-throughput re-synchronization.

4 System Timing: A Key Component Delays Adjustable Delay Element Low Power Ideally no static current. Low Area Wide-Range, Fine Resolution High operating frequency Mixed signal control Linear delay characteristic Composed of standard library elements Low Noise More on this later Digital IN Delay = 100pS to 1000ps, Increments of 10pS. Control Word Digital Out

5 Some Conventional Options Starved Invertor Switched Capacitance Delays RFP RFN Good Wide- Range Potentially Low Noise Standard Cell (AOI) Bad Power, Area Non-linear No dig. Control Touchy Analog References Typical delay 100pS inf Switched Paths Good Wide-Range Nearly Linear Potential Alg ctrl. Std Cells Low Noise Bad Power penalty. Typical delay 300pS Lower max. speed. Glitching 3000pS slow slow Good Area, Power High Speed Dig. Library Element Bad Low-Range Effects edges differently. Little alg. Control. Good Wide- Range Std Cells Low Noise -fast mode Bad Power Definite glitching. Poor resolution. No alg. ctrl. Typical delay 100pS 120pS Typical delay 200pS 600pS

6 More advanced Approaches Adjustable Drive Self-Starved Invertor Delays Good Fine Resolution Potentially Linear Bad Typical delay 200pS Low-Range. Custom tweaking reqd. 300pS slow Good Area, Power Wide Range Linearity Mixed Signal Ctrl Externally Tunable Typical delay 120pS Bad Low resolution. Low Max speed. Noise sensitive. 1000pS Glitchless Switched Capacitor Parallel Invertor Chain TX Gate Bleeder Good Wide-Range Nearly Linear Potential Alg ctrl. Std Cells Low Noise Bad Power penalty. Larger Area Lower max. speed. Typical delay 400pS 3000pS Good Med Resolution (~30 ps) Potentially Linear Std Cells Typical delay 200pS Bad ~Area ~Power Med- Range Poor alg control. 400pS

7 Delay Element Recap Delays slow slow Hybrids are not only possible, but are encouraged. The delay element to use depends largely on the application requirements. Is it passing High or Low frequency signals? What is the required delay range? Does glitching matter? Fine or coarse control resolution?

8 Numerically Controlled Oscillator NCOs RUN PASS CLK T = 2*(Tdelay + Tinv) Freq adj. NCO All digital, Numerically Controlled Oscillator. An example Delay Element: f = 2.3GHz ~ 150 MHz Intervals f = 1.1GHz Speed Setting AVG Variation Frequency Typical Case: 27C (GHz) Worst Case: 100C % Best Case: 0C % Typical Power: This is one of the more power hungry f = 1.25 GHz, 1.8V 720 uw 580 fw/hz ~ 6 flip-flops With custom sizing, power can be nearly halved.

9 An Aside MOS Noise Ring Oscillators are highly non-linear. Difficult to analyze. Noise causes the delay through each stage to vary randomly about the mean. Translates to jitter in the output frequency Single MOS: Thermal Noise + Flicker (1/f) Noise NCOs V 2 i ( f ) = 4kT g m + K WLCox f 2 V i Low Noise RC = 100 ps 1kΩ 100fF 10kΩ 10fF Low Power, Area RC = 100 ps Large Transistors (WL) High W/L ratios Fewer Stages Larger Cox Poorer Area, Power, Speed Poorer Area, Power, Range Poorer Range t ox is smaller as technology scales. Moral: For noise immunity, add capacitance instead of resistance. In this work me make the conscious choice to focus on power andarea, not noise. For circuits which interface to RF, noise must be a priority.

10 A Poor Man s PLL: Digitally Matching a Reference Digital PLLs FreqUP Ref Freq Detect FreqDN Freq adj. NCO Phase Adjust Phase Detect Advance Recede Start the ring oscillator running at full speed. The frequency detector will force the NCO delay to rise, thus lowering the frequency. Once the frequency falls below the reference, the NCO will be commanded to reverse course, and raise the frequency. Provided the delay through the feedback loop is controlled, we then know that the frequencies are roughly aligned, and we can use a similar approach to align the phase. Once locked, the oscillator will toggle between the two digital frequencies that surround the reference frequency this introduces a quantization based jitter

11 A Poor Man s PLL: Clock Multiplication Digital PLLs FreqUP Ref Freq Detect FreqDN Freq adj. NCO Phase Adjust Phase Detect Advance Recede Divider The same approach as for an analog PLL. Add a clock divider into the feedback path. The frequency and phase detectors will work to keep the two signals it sees matched. The frequency detector forces the NCO to put out a frequency faster than the reference. Thus, by inserting a simple counter in the feedback path, we can generate integer multiples of the reference frequency. N fdbk

12 A Poor Man s PLL: Digital Clock Synthesis Digital PLLs Ref Divider 1 1 R R R R FreqUP FreqDN Freq adj. NCO Phase Adjust Advance RST not shown. Recede Divider Including a divider on the reference, we can generate nearly arbitrary frequencies: f clk = f ref * (N fdbk /M ref ) However, if the rationals N and M are large, then special considerations must be taken to unsure stability of the system. There is still the problem of quantization induced jitter

13 Improving Jitter: Hybrid PLL Hybrd PLLs 100M Osc Freq 0.1M Lock some units digitally, pass on only the required number to analog control MHz ref Time Ref PFD CP Filter Analog Control Digital Freq Detect No quantization based noise potentially suitable for RF and switched cap filtering. Wide Range, Quick Locking, More stability than conventional analog PLL

14 Hybrid Analog/Digital PLL Example Simulates a hybrid lock to a 12.5 Mhz reference frequency. NCO is composed of 7 self-starved delay elements Hybrd PLLs 8 speed settings from 8 to 35 Mhz in ~3 Mhz steps. Start Running Quickly Slow Down when told We are no longer too fast Lock, and give analog control Roughly locked analog takes over.

15 Calibrated Delay Line / Delay Locked Loop Can be used in place of a PLL in many case. Locks the delay through a line to a particular reference. DLLs Snapshot of values through the chain at +ve edge clk. When reference edge peeks out of the delay chain, decide whether to increase or decrease the delay through the line. REFERENCE D Q D Q D Q Logic: Is the falling edge at the tail of the line? Yes Locked, No INC or DEC delay appropriately. Note: FSM must be tolerant to metastable inputs. Single sided form is usefull for clock manipulation generating offset phases, etc With dual-rails, we can force an external signal to undergo the same delay as the reference Usefull for highly accurate timing measurements as in ADC.

16 Clock and Data Recovery: Single Cycle Acquisition PLLs Quick PLL Typical Clock-recovery solutions require a PLL is trained before sampling data. An analog PLL would typically require hundreds of training pulses. A typical digital PLL would require 10s of pulses. There should be NO REASON why we can t lock to a transmitter s timing in ONE training pulse. D1 D0 Local Oscillator Line IN

17 Clock and Data Recovery: Single Cycle Acquisition PLLs Quick PLL D1 D0 Line IN Line IN D Q Snapshot of values through the chain at +ve edge clk. D Q Local Oscillator D Q Logic: Search for the falling edge, set that MUX into feedback. (Requires 2 gates + a latch for each stage) D Q D Q When training pulse peeks out of the delay chain: find the falling edge turn on the feedback loop creates a ring oscillator with the period of the training pulse Concerns: Resolution of MUXs Range vs. Area and Power Logic Delay compensation Extra precautions (not shown) protect against metastability. Note: We can use further transition information in the data to adjust the frequency accordingly.

18 Clock and Data Recovery: Frequency Re-Synthesis CDR 1) The training pulse fires off an oscillator at the same frequency as the transmitter. D1 D0 Line IN Glitcher Local Oscillator 2) We then use transition information in the data to update the frequency up or down. Problems: Very fine resolution NCO. Transition activity must be enforced. First pulse is slow to set off the clock. Stability is an issue. Data Line Set 1 2 Start Oscillator Transition Update CLK

19 Clock Data Recovery: Phase Alignment Assume a global frequency locked clock which has random phase relation across the chip. CDR Phase Alignment The data and clock will arrive within T seconds of each other. Attempt to pull the signals into phase before being sampled. Two paths race each other through interlocked latches extra delay is added to the path who is ahead. With slower clocks, the maximum pull-in range extends requires more racer stages at lower speeds Clock Data Clock Up to T D0 D1 Reasonable for T=0.5-2nS, f = 500Mbps 2Gbps. Data Phase Mis-Alignment Rather than pull into-phase, just ensure they are far enough out of phase. Prevent transitions near a clock-edge. Danger window T = set-up + hold time If the synchronizing bit transitions near an edge, bump it out of the way. Clock Data D0 D0 D1 D1 Practical concerns add to the safety window, and, the maximum speed of operation = 1 / (2*T window ) Danger Removes Delay to avoid clock edge. Suitable below 750 Mbps

20 Clock Data Recovery: Skew Adjustment Timing signal is transmitted along with the data. Bussed signals may not be routed together, and therefore experience different delays. simultaneously transmitted signals may arrive many clock cycles apart To solve After a handshake, an initial training pulse (all ones) is sent simultaneously along every channel. The receiver measures the relative delays in each path and compensates to remove skew. The transmitter can then send bit/nibble serially at ~ 750 Mbps/channel. CDR Clock Interconnect skew Skew Correction Data Channel(s) Measurement is performed with delay elements and interlocked sets of RS latches. Can compensate for arbitrary skew across the interconnect limited only by how much maximum compensation one wishes to add Lowering clock speed will solve any skew beyond HW limits.

21 High-Speed Self-Synchronizing Synchronizing IO System IO Using the timing circuits permit: Low power and area, pausable NCOs Efficient CDR schemes for Gbps serial links. Skew-correction across an arbitrary interconnect. ROUTE CONTROLLER Variable Freq Pausable OSC Source Subsystem Data WREN Variable Freq Pausable OSC Serial Data SYNC ACK Serial Low Area/Power Configurable Within architecture we can provide: Dynamic Routing Flow Control Error Detection and ARQ A simple synchronous interface to subsystems. Serial Data SYNC ACK Data RDREQ Variable Freq Pausable OSC Sink Subsystem

22 Conclusion Architecture Delays NCOs Digital PLLs Hybrd PLLs DLLs Quick PLL CDR System IO Pausable clocks of arbitrary frequency Fully digital Low-area, low-power local oscillators. Fast, Rough, timing locks without analog circuits High-throughput, error-tolerant, bit-serial links across domains Provide simple synchronous interfaces to generic IP modules Potentially unsuitable for RF mixing, and other jitter intolerant systems For Questions Offline: Gord Allan gallan.doe.carleton.ca Web:

23 Appendix: Timing Based Analog-Digital Conversion ADC Case 1: Case 2: An analog voltage into the VCO produces a variable rate clock. The clock period is measured, and converted to a digital word. An analog voltage charges a capacitor at a variable rate. We measure the time it takes to discharge. The time is measured in ticks of a very high frequency reference.