ENEE 359a Digital VLSI Design

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1 SLIDE 1 ENEE 359a Digital VLSI Design Some & How to Deal with Them Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides (PSU), Schmit & Strojwas s slides (CMU), Dally s EE273 slides (Stanford), Wolf s slides for Modern VLSI Design, and/or Rabaey s slides (UCB).

2 SLIDE 2 Overview Circuit Integrity Project-review presentation Capacitive Resistive Inductive

3 SLIDE 3 RF and Circuit Integrity in Digital Systems Prof. Electrical & Computer Engineering blj@umd.edu AFOSR-MURI Annual Review, October 2004

4 SLIDE 4 Overview How Digital Circuits & Systems Are Built, and Some Ways in Which They Fail Components of Digital Systems RF- and Temperature-Related Vulnerabilities Data Inputs and Networks Clock Inputs and Networks Power/Ground Inputs and Networks Circuit Design: Our Device-Under-Test Recent Work Comparison of Vulnerability: DUT s Clock/Data Inputs [DUT: test chip fabricated in AMI s 0.5µm process] Custom Chip Design & Fabrication for ESD Studies Future Work

5 Digital Systems: A Primer Simple Digital Circuit: VDD SLIDE 5 Simple Digital System: VDD pad Data pad I/O Buffers State Storage Clk pad Combinational Logic D Clk Q Q GND pad

6 Digital Systems: A Primer Components of Digital Systems SLIDE 6 Data Source Clock Source Logic State D Q Clk Q Logic State D Q Clk Q Most systems are pipelined: Multiple logic blocks operating simultaneously Highly synchronous: lock-step operation

7 SLIDE 7 Digital Systems: A Primer Components of Digital Systems VDD pad VDD Data pad Clk pad Logic D Clk Q Q Logic D Clk Q Q VSS pad ESD + I/O Buffers Register GND Register Groundplanes play significant role: Provide references for input amplifiers Allow CMOS circuits to behave as signal repeaters (with high input impedance, low output impedance)

8 Digital Systems: A Primer Components of Digital Systems SLIDE µm ESD diodes I/O buffers ESD diodes I/O Pads play significant role: Enormous capacitances, require enormous gates to drive them (and the pins & off-chip traces) Big gates => big currents; fast clocks => small dt VDD/VSS leads have inductance => Ldi/dt noise

9 SLIDE 9 Digital Systems: A Primer Components of Digital Systems VDD VDD Data Clk Logic D Clk Q Q Logic D Clk Q Q VSS ESD + I/O Buffers Register GND Register At the bottom are just a bunch of MOSFETs

10 SLIDE 10 Digital Systems: A Primer Components of Digital Systems VDD VDD Data Logic Logic Clk VSS ESD I/O Buffers Register GND Register At the bottom are just a bunch of MOSFETs Each register shown holds one bit Each I/O pad requires its own ESD, receivers, & drivers Logic blocks can be arbitrarily large/complex

11 SLIDE 11 Circuit Integrity: Data How To Make This System Fail VDD VDD Data Logic Logic Clk VSS ESD I/O Buffers Register GND Register RF that makes it this far (past initial I/O buffers) has corrupted the system: only solution is to use higher level bus- or packet-encoding techniques Corrupted data can lead to incorrect results, software crash/reboot, transmission to remote nodes, etc.

12 SLIDE 12 Sequential Circuits Primer SET-UP and HOLD times D Q CLK CLK t SETUP t HOLD D DATA STABLE t CLK-to Q Q OUTPUT VALID Storage elements (latches, registers) expect data and clock edges to be timed perfectly (e.g., within 20ps)

13 SLIDE 13 Sequential Circuits Primer SET-UP and HOLD time, metastability CLK t t SETUP HOLD D CLK Q t phl t plh Data must not transition near clock edges Corollary: Perturbations on clock network (e.g., noise spikes, thermal-related delays) achieve same results

14 SLIDE 14 Circuit Integrity: Clock How To Make This System Fail VDD VDD Data Logic Logic Clk VSS ESD I/O Buffers Register GND Register RF that makes it this far (past initial I/O buffers) has corrupted the system: packet-encoding techniques that might detect data corruption are inapplicable Unwanted clock edges likely result in metastability, lead to incorrect results, most likely system crash

15 SLIDE 15 Circuit Integrity: Clock Maximum clock-frequency calculations VDD VDD Data Logic Logic Clk VSS ESD I/O Buffers Register GND Register Logic delay = 800ps = 550ps Critical path determines minimum clock period (in this example: 800ps + register overhead + skew/etc. =1000ps total, or 1GHz [as opposed to 750ps/1.33GHz])

16 SLIDE 16 Circuit Integrity: Clock How To Make This System Fail VDD Hot-Spot VDD Data Logic Logic Clk VSS ESD I/O Buffers Register GND Register Logic delay = 800ps = 550ps This portion of the system logic heats up, experiences more delay than other areas Thermal gradients in synchronous systems disastrous (consider tight timing margins in GHz systems)

17 SLIDE 17 Circuit Integrity: V DD & V SS How To Make This System Fail VDD VDD Data Logic Logic Clk VSS ESD GND>V ILThese Register GND Register inverters might not switch Localized (or global) ripples on groundplanes can cause logic to misbehave, inputs to be misinterpreted (e.g. suppose Data/Clk = 1, V > V IL on gate of 2nd INV) Causes same effects as data/clock corruption

18 SLIDE 18 Circuit Integrity DISTINGUISHING CHARACTERISTICS of the NETWORKS in DIGITAL SYSTEMS: CLK: Only Edges Matter DATA: Both Timing and Levels Matter VDD/GND: Even Small Changes in Level (e.g., 5 10%) Matter CLK/DATA: Enter Via ESD Protection VDD/GND: 1/2 ESD (shunts one to other)

19 SLIDE 19 Our Research Question Comparing CLK and DATA inputs, which is more important: The distinguishing characteristics of the way those inputs will be used in the digital system or circuit? The levels and frequencies of injected RF? Our Device Under Test (counter): D Q OUT Clock Source Clk Q Just about simplest possible digital system [Last Year s Results: evaluated vulnerability of CLK input]

20 Our Device Under Test SLIDE 20 Internal Oscillator CLK 8-bit Ripple Counter, Chip Built via MOSIS Full-Custom Design (except for pad frame) Fabricated in AMI s 0.5µm Technology 3.3V power supply CLKSEL mux D Q D Q D Q D Q Q Q Q Q c7 c2 c1 c0

21 SLIDE 21 Our Device Under Test VDD CLK CLKSEL Internal Oscillator D Q Q OUT VSS ESD Circuitry Input Buffers Invert Select 3-nand MUX (int/ext clk) Points of Interest: Digital system built from complementary gate designs (high input impedance, low output impedance). CLK only driving MUX, one DFF (see previous slide). => CLK and CLKSEL see virtually identical loads.

22 Experimental RF Set-Up SLIDE 22 RF Amplifier (33 20 db Coupler HPF Input Probe Output Probe RF Isolator DUT RF Pulsed Source LPF Pull-up Resistor Load Resistor Power Meter RF Detector Vbias Power Amp 33dB at 1GHz Freq 800MHz 4.2Ghz with 1.2W max power

23 Test Board CLK & CLKSEL SLIDE 23 Counter Output

24 SLIDE 24 Test Scenarios RF VDD CLK Internal Oscillator D Q Q CLKSEL OUT VSS VDD Internal Oscillator CLK RF CLKSEL VSS D Q Q OUT

25 SLIDE 25 CLK vs. CLKSEL Inputs Power-v-Freq. required to cause incorrect behavior (state change in digital logic) Power Triggering Levels (dbm) Injected Power (ClK) Injected Power (CLKSEL) (MHz)

26 Input Impedance CLK pin CLKSEL pin SLIDE 26 CLK pin, old set-up

on-chip pads to accommodate input probes Designed & fabricated two chips

27 Recent Work: ESD ESD Test Chip I (die photo) for Rodgers & Firestone ESD Test Chip II (layout) for Rodgers & Firestone SLIDE 27 Custom-designed on-chip pads to accommodate input probes Designed & fabricated two chips (one on right just back from fab) allow probing at various points between PAD and internals

28 SLIDE 28 Future Work New Test Structures (e.g., to emulate larger designs, differentiate between CLK & DATA) Vss Vdd

29 SLIDE 29 Future Work Using same board, test the power rail Design new board that differentiates GND input pin from IC s ground plane, to test the ground pin s susceptibility

30 SLIDE 30 Acknowledgments, etc. GRAD STUDENTS: Vincent Chan, Cagdas Dirik, Samuel Rodriguez, Hongxia Wang INVALUABLE AID: Todd Firestone and John Rodgers FOR MORE INFO:

31 SLIDE 31 Capacitive CROSS TALK Largely capacitive at current switching speeds inductive coupling is major concern in I/O of mixed signal circuits (e.g. RF). Translation: pay attention to the cut-off frequency. C c V in? In general, V in 0

32 SLIDE 32 Capacitive Coupling Influenced by impedance of coupled line: Wire Y is driven: V y is transient Wire Y is floating: V y is persistent Floating: V x C xy X Y (floating) V y C y V y = V x C xy C y + C xy

33 SLIDE 33 Capacitive Coupling Influenced by impedance of coupled line: Wire Y is driven: V y is transient Wire Y is floating: V y is persistent Driven: V x C xy X Y (driven) V y R y C y V y = V x Z y C xy t rise

34 SLIDE 34 Floating-Coupling Example X is (logically unrelated) wire crossing over circuit in the metal-1 layer. Because this is a dynamic circuit, the output is floating when PDN=>false. Example assumes capacitance to poly wire Y (gate for inverter); node Y is precharged during PRE stage to 2.5V, wire X undergoes 2.5 -> 0V. V DD CLK C XY Y In 1 In 2 In 3 PDN C Y X 2.5 V CLK 0 V 3 x 1 µm overlap: 0.19 V disturbance

35 SLIDE 35 Driven-Coupling Example t r _ τ XY = R Y (C XY +C Y ) t (nsec) Transient decays with time constant τ xy = R y (C xy + C y )

36 SLIDE 36 Crosstalk & Technology Crosstalk vs. Technology Pulsed Signal 0.12m CMOS 0.16m CMOS Black line quiet Red lines pulsed Glitches strength vs technology 0.25m CMOS 0.35m CMOS

37 SLIDE 37 Some Solutions to Capacitive Crosstalk Proportional noise source: Increasing Vdd will not help Avoid floating nodes: use keeper circuits, e.g.: VDD VDD CLK Keeper MOSFET: weak enough to be overpowered INPUT/S Pull-down Network (nfet network) OUTPUT CLK Keep sensitive nodes from full-swing signals Make rise/fall time large (but it can increase power) Use differential signaling: turns cross-talk into common-mode noise source Don t have long parallel wires Wires on adjacent metal levels: perpendicular Shield wires by inserting VDD/GND wires between (works in same plane as well as in vertical dimension)

38 SLIDE 38 Capacitance & Wire Delays Recall rise time: R V(t) C What if is C is not a constant? C c Miller Effect Both terminals of capacitor are switched in opposite directions (0 -> Vdd, Vdd -> 0) Effective voltage is doubled and additional charge is needed (from Q=CV) Bottom Line: RC time constant doubles.

39 Capacitance & Wire Delays r is ratio between capacitance to neighbor and to GND: SLIDE 39 Wire delay may vary over 500% between worst & best case, due solely to activity on wires

40 Solutions to Wire-Delay Prob. Dense Wire Fabric V S G S V S SLIDE 40 V G S S V S Trade-off: Cross-coupling capacitance 40x lower, 2% delay variation Increase in area and overall capacitance

41 SLIDE 41 Solutions to Wire-Delay Prob. In Encoder Bus Decoder Out Bus encoding to reduce bad transitions

42 I/O Pad Drivers, revisited SLIDE µm ESD diodes I/O buffers ESD diodes I/O Pads constrain your design: Enormous capacitances, require enormous gates to drive them (plus the pins & off-chip traces) This represents 1000x capacitive load of on-chip gate Big gates => big currents; fast clocks => small dt VDD/VSS leads have inductance => Ldi/dt noise

43 SLIDE 43 Transistor Sizing Sizing for Large Capacitive Loads A 1 (W p1 /W n1 ) A 3 (W p1 /W n1 ) C in1 A 0 (W p1 /W n1 ) A 2 (W p1 /W n1 ) C load Supose C load large (e.g. bond pads, etc.) Scale each inverter (both FETs in the circuit) by a factor A (input capacitances scale by A) If input C to last inverter * A = C load (i.e., C load looks like N+1 th inverter) then we have: Input C of last inverter = C in1 A N = C load Rearranging: A = [C load C in1 ] 1/N

44 SLIDE 44 Transistor Sizing Sizing for Large Capacitive Loads A 1 (W p1 /W n1 ) A 3 (W p1 /W n1 ) C in1 A 0 (W p1 /W n1 ) A 2 (W p1 /W n1 ) C load Capacitances increase by factor of A left to right Resistances decrease by factor of A left to right Total delay (t phl + t plh ): (R n1 +R p1 ) (C out1 +AC in1 ) + (R n1 +R p1 )/A (AC out1 +A 2 C in1 ) + = N (R n1 +R p1 ) (C out1 +AC in1 ) Find optimal chain length: N opt = ln(c load C in1 )

45 SLIDE 45 Example C in = 2.5fF 0.25µm C load = 20pF Load is ~8000x that of single inverter s input capacitance: find optimal solution.

46 Example.5/ /.7 3.6/ /4.9 27/13 72/36 194/97 523/ /706 SLIDE 46 (sizes in microns) C load = 20pF N opt = ln(20pf/2.5ff) = 8.98 => 9 stages Scaling factor A = (20pF/2.5fF) 1/9 = 2.7 Total delay = (t phl + t plh ) = N (R n1 +R p1 ) (C out1 +AC in1 ) = N (R n1 +R p1 ) (C out1 + [C load C in1 ] 1/N C in1 ) (assume C in1 = 1.5C out1 = 2.5 ff) = 9 (31/9 + 13/3) (1.85fF fF) = 602 ps (0.6 ns)

47 SLIDE 47 But Wait! You don t (necessarily) need the optimal arrangement You can (perhaps) get away with a slower circuit Say, for example, you want 1GHz (1ns) 0.6ns is overkill Minimize (integer) N to obey t p,max A ln( Fan-out) = N Fan-out 1 N t p0 ln( A) (requires numerical methods)

48 SLIDE 48 Example, revisited 0.25µm C in = 2.5fF C load = 20pF Load is ~8000x that of single inverter s input capacitance: find optimal solution. If t p,max = 1ns (and not 0.6ns) we can have N=4 Scaling factor A = (20pF/2.5fF) 1/4 = 9.46

49 SLIDE 49 Example, revisited C in1 =2.5fF N opt => 4 stages 0.5/0.25 µm (0.5/0.25) = 44.8/22.4 µm (0.5/0.25) = 4.7/2.4 µm (sizes in microns) (0.5/0.25) = 423/212 µm Scaling factor A = (20pF/2.5fF) 1/4 = 9.46 C load Total delay = (t phl + t plh ) = N (R n1 +R p1 ) (C out1 +AC in1 ) = N (R n1 +R p1 ) (C out1 + [C load C in1 ] 1/N C in1 ) (assume C in1 = 1.5C out1 = 2.5 ff) = 4 (31/9 + 13/3) (1.85fF fF) = 793 ps (0.8 ns)

50 SLIDE 50 Example, revisited C in1 =2.5fF 0.8ns Versus: 0.5/0.25 µm (0.5/0.25) = 44.8/22.4 µm (0.5/0.25) = 4.7/2.4 µm (sizes in microns) (0.5/0.25) = 423/212 µm C load.5/ /.7 3.6/ /4.9 27/13 72/36 194/97 523/ /706 µm 0.6ns (sizes in microns) C load = 20pF Reduced area, reduced current, reduced capacitance, nearly same speed (better parasitics, ground bounce effects)

51 SLIDE 51 Can we do better? C in1 =2.5 ff 0.5/0.25 µm 20 * 20 (0.5/0.25) = 200/100 µm 20 (0.5/0.25) = 10/5 µm C load N opt => 3 stages Scaling factor A = (20pF/2.5fF) 1/3 = 20 Total delay = (t phl + t plh ) = N (R n1 +R p1 ) (C out1 +AC in1 ) = N (R n1 +R p1 ) (C out1 + [C load C in1 ] 1/N C in1 ) (assume C in1 = 1.5C out1 = 2.5 ff) = 3 (31/9 + 13/3) (1.85fF fF) = 1210 ps (1.2 ns)

52 Tri-State Buffers V DD SLIDE 52 En V DD In En En Out In En Out Inverting tri-state buffer Increased output drive Non-inverting tri-state buffer

53 SLIDE 53 Designing Large Transistors D(rain) S D G D S(ource) S G(ate)

54 Designing Large Transistors GND SLIDE 54 Out

I/O Pads, again Bonding Pad SLIDE 55 100 µm

55 I/O Pads, again Bonding Pad SLIDE µm Out V DD In GND Where have you seen this before?

56 I/O Pad Drivers, revisited SLIDE µm ESD diodes I/O buffers ESD diodes Oh yeah

57 SLIDE 57 Resistive Basic Idea: IR drops over long distances Power Rails VDD R CLK VDD V V R V Possible to get relatively large non-zero voltage at input: reduces noise margins

58 SLIDE 58 Power/Ground Distribution V DD GND Logic Logic V DD V DD GND (a) Finger-shaped network GND (b) Network with multiple supply pins

59 SLIDE 59 Resistive IR Drops and RC Delay over long wires (remember: delay of wire is quadratic w/ its length) Solution: repeaters or pipelining Instead of this: Do this: Or this: D Q D Q D Q D Q CLK Q Q Q Q

60 SLIDE 60 Inductive L di/dt noise (ground bounce): VDD Current flow changes direction when input (thus output) values change VDD L ( 0) IDEAL Magnitude of current change is di The time to switch directions is dt The voltage-drop induced on this wire at time of switching is L di/dt L ( 0) REALISTIC

61 SLIDE 61 Inductive L di/dt noise (ground bounce): VDD 1 Another inverter, elsewhere. What comes out here? VDD L ( 0) I/O Driver: V = L di/dt = voltage-drop induced on this wire V L ( 0) V REALISTIC

62 Inductive Simultaneous Switching Noise: FCRAM side VDDQ(Pad) SLIDE 62 DQS (Pin) DQ0-15 (Pin) VSSQ(Pad) Controller side DQS (Pin) DQ0-15 (Pin) skew=158psec skew=102psec

EE141-Spring 2007 Digital Integrated Circuits

EE141-Spring 2007 Digital Integrated Circuits Lecture 22 I/O, Power Distribution dders 1 nnouncements Homework 9 has been posted Due Tu. pr. 24, 5pm Project Phase 4 (Final) Report due Mo. pr. 30, noon