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7 Lecture/s Interconnects SLIDE 1 ENEE 359a Digital Electronics Interconnects Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides (PSU), Schmit & Strojwas s slides (CMU), Dally s EE273 slides (Stanford), Wolf s slides for Modern VLSI Design, and/or Rabaey s slides (UCB).

8 Lecture/s Interconnects SLIDE 2 Overview Wires and their physical properties (MOSFETs, too ) LC/RC/RLC transmission lines, characteristic impedance, reflections Dynamic considerations (e.g. skin effect) The Bottom Line: propagation delay, transistor sizing, inductive (Ldi/dt) noise, capacitive coupling, signal degradation, various rules of thumb for design

9 Lecture/s Interconnects Metal Layers in ICs SLIDE 3 IBM s 6-layer copper interconnect

10 Lecture/s Interconnects Some Transmission Lines SLIDE 4 Insulating jacket Outer shield Inner dielectric Inner conductor conductor dielectric Coaxial Cable Microstrip Gnd Twisted Pair dielectric conductor dielectric conductor Gnd Gnd Stripline conductor dielectric

11 Lecture/s Interconnects SLIDE 5 Cross Section of PCB Board M1 (signal layer) FR4 Dielectric M2 (Ground plane) M3 (Power plane) M4 (signal layer) FR4 Dielectric M1 (signal layer) M2 (Ground plane) M3 (signal layer) M4 (signal layer) M5 (Power plane) M6 (signal layer)

12 Lecture/s Interconnects SLIDE 6 Wires in Digital Systems Physically, wires are Stripguides on (and in) printed circuit-board cards, layed over & sandwiched between groundplanes Stripguides on ICs, layered atop each other Conductors in cables & cable assemblies Connectors We tend to treat them as IDEAL wires No delay (equipotential) No capacitance, inductance, or resistance They are NOT ideal To build reliable systems, must understand properties & behavior

13 Lecture/s Interconnects Metal Layers in ICs metal 3 SLIDE 7 metal 2 metal 1 vias poly poly n+ p-tub n+ Remember the RC Constant τ?

14 Lecture/s Interconnects SLIDE 8 Metal Layers & Capacitances metal 2 metal 3 metal 1 vias poly poly n+ p-tub n+ On-chip wires run in multiple layers with no explicit return planes (ground is used as implicit return) Thus, almost all capacitance of on-chip wire is to other wires (same plane, different plane, etc.) Capacitance of MOSFET scales with Vdd

15 Lecture/s Interconnects SLIDE 9 Metal Layers & Resistances metal 2 metal 3 metal 1 vias poly poly n+ p-tub n+ Resistance of conductor proportional to length/width, depends on material (resistivity), causes delay & loss Resistance of wire scales with square root of signaling frequency (at high speeds) ( skin effect ) Process scaling tends to increase resistance

16 Lecture/s Interconnects Wire Resistance SLIDE 10 h l w r l R = ρl/a = ρl/(wh) for rectangular wires (on-chip wires & vias, PCB traces) R = ρl/a = ρl/(πr 2 ) for circular wires (off-chip, off-pcb) Material Resistivity ρ (Ω-m) Silver (Ag) 1.6 x 10-8 Copper (Cu) 1.7 x 10-8 Gold (Au) 2.2 x 10-8 Aluminum (Al) 2.7 x 10-8 Tungsten (W) 5.5 x 10-8

17 Lecture/s Interconnects Sheet Resistance SLIDE 11 R = ρl/(wh) = l/w ρ/h for rectangular wires Sheet resistance R sq = ρ/h Material Sheet resistance R sq (Ω/sq) n, p well diffusion 1000 to 1500 n+, p+ diffusion 50 to 150 polysilicon 150 to 200 polysilicon with silicide 4 to 5 Aluminum 0.05 to 0.1

18 Lecture/s Interconnects Wire Capacitance Common wire cross-sections/permittivities: SLIDE 12 Material ε r Air 1 Teflon 2 Polymide 3 SiO Glass-epoxy (PCB) 4 Alumina 10 h Silicon 11.7 Permittivity ε = ε 0 ε r Permittivity of free space ε 0 = x F/m

19 Lecture/s Interconnects SLIDE 13 Inductance When conductors of transmission line are surrounded by uniform dielectric, capacitance & inductance are related: CL = εµ Inductive effects can be ignored if the resistance of the wire is substantial enough (as is the case for long Al wires with small cross section) if rise & fall times of applied signals are slow enough So inductance must be considered for off-chip signals (even power/ground) for future even-higher-speed on-chip signalling

20 Lecture/s Interconnects SLIDE 16 Wires & Models Example Wires: Type W R C L On-chip 0.6 µm 150k Ω/m 200 pf/m 600 nh/m PC Board 150 µm 5 Ω/m 100 pf/m 300 nh/m 24AWG pair 511 µm 0.08 Ω/m 40 pf/m 400 nh/m In a situation, use a model of wires that captures the properties we need: ideal, lumped L, R, or C LC, RC, RLC transmission line General LRCG transmission line Appropriate choice of model depends on signaling frequency f 0 = R πL

21 Lecture/s Interconnects SLIDE 17 General LRCG Model Model an infinitesimal length of wire, dx, with lumped components L, R, C, and G (inductance, resistance, capacitance, and conductance) Drop across R and L Current into C and G 2 V x 2 = For G=0: 2 V x 2 = V x I x = = RI GV + + I L t 2 V V RC + LC t t 2 V C t V V RGV + ( RC + LG) + LC t t 2 2

22 Lecture/s Interconnects Impedance SLIDE 18 s = 2πjƒ = jω (typical assumption: G = 0) An infinite length of LRCG transmission line has impedance Z 0 Driving a line terminated into Z 0 is same as driving Z 0 In general, Z 0 is complex and frequency-dependent For LC lines (operating at high frequencies), Z 0 is real-valued and independent of frequency

23 Lecture/s Interconnects SLIDE 19 Cut-off Frequency f 0 Z 0 R dx L dx C dx G dx Z 0 = R + jωl G + jωc 1 2 Low Freq R >> jωl R dx C dx Z 0 find f 0 where R == jωl R f 0 = πL R L = Z jωc 0 = --- C High Freq lossless LC R << jωl L dx C dx - Transmission lines have characteristic frequency f 0 - Below f 0 RC model, Above f 0 LC model

24 Lecture/s Interconnects Cut-off Frequency f 0 SLIDE 20 Frequency

25 Lecture/s Interconnects SLIDE 21 Cut-off Frequency f 0 II 0.5µ 0.5µ SiO 2 FR4 Dielectric 5 mil 0.7 mil L = 0.6 nh/mm C = 73 nf/mm R dc = 120Ω /mm f 0 = 32 GHz L = 0.5 nh/mm C = 104 ff/mm R dc = 0.008Ω /mm f 0 = 2.5 MHz ~RC Model for on chip interconnects ~LC Model for PC Board traces 1 mil = inch Z 0 = L C nh 2 = ~= 70 Ω 0.1 pf Example from Poulton 1999 ISSCC Tutorial

26 Lecture/s Interconnects SLIDE 22 RC Lines (low frequency) 2 V x 2 = V V RGV + ( RC + LG) + LC t t 2 R >> jωl, governed by diffusion equation: 2 2 V x 2 = RC V t Signal diffuses down line, disperses: R increases w/ length d C increases with d Delay & rise time both increase with RC, thus with d 2 For a typical wire: R = 150KΩ/m C = 200pF/m τ = RC = 30 µs/m 2 = 30 ps/mm 2 0mm 2.5mm 5mm 7.5mm 10mm

27 Lecture/s Interconnects SLIDE 23 LC Lines (high frequency) 2 V x 2 = V V RGV + ( RC + LG) + LC t t 2 R << jωl, governed by wave equation: 2 2 V x 2 = LC V t 2 V i ( x, t) Z Z 0 + R S Waveform on line is superposition of forward- and reverse-traveling waves: V f = VS t x -- v V r Waves travel with velocity v = (LC) -1/2 What happens when the wave gets to the end of line?

28 Lecture/s Interconnects SLIDE 24 RLC/G Lines (general case) 2 V x 2 = V V RGV + ( RC + LG) + LC t t 2 Ignoring G, wave propagation equation: 2 2 V x 2 RC V = LC V t t 2 Lossy transmission line, dispersive waves: 2 Substrate-doping-dependent dispersion of a picosecondscale pulse in propagation of an on-chip transmission line

29 Lecture/s Interconnects SLIDE 25 RC vs. RLC Output response of inverter with step input: VDD L VDD R p? C in R n L GND In reality, we have a non-zero inductance in series with the RC circuit. (Inductors and capacitors both have memory )

30 Lecture/s Interconnects SLIDE 26 RC vs. RLC Output response of inverter with step input: Vdd inductor causes slow start-up for switch RC Model RLC Model V tl 0 tens of ps Result: slower reponse time, ringing

31 Lecture/s Interconnects SLIDE 27 Impedance and Reflections Terminating a Transmission Line: I f I r V i Z 0 ZT I T Telegrapher s Equations: k r I r = --- = = I i V r V i Z T Z Z T + Z 0 Reflection coefficient k r may be complex for complex impedances Z T i.e., the reflected wave may be phase-shifted from the incident wave. For real-valued Z T the reflection coefficient is real, and the phase shift is either 0 (k r positive) or π (k r negative).

32 Lecture/s Interconnects SLIDE 28 Impedance and Reflections k r I r = --- = = I i V r V i V B Z T Z Z T + Z 0 V A Z 0 Z0 V C Matched Termination, k r = 0 Va Vb Vc Z 0 Z T = Va Vb Vc Open-Circuit Termination, k r = 1 Z 0 Z T = 0 Va Vb Vc Short-Circuit Termination, k r = -1

33 Lecture/s Interconnects SLIDE 29 Impedance and Reflections 400Ω S 50Ω, 5ns R 1V 1KΩ

34 Lecture/s Interconnects SLIDE 30 Impedance and Reflections 400Ω S 50Ω, 5ns R 1V 1KΩ V Z 0 i = VS = V = 0.111V Z 0 R S Z k T Z rr = = = Z T + Z Z k T Z rs = = = Z T + Z Values are typical for 8-mA CMOS driver with 1kΩ pullup

35 Lecture/s Interconnects SLIDE 31 Impedance and Reflections 400Ω S 50Ω, 5ns R 1V 1KΩ Vwave Vline time t Vi Vr Vi Vr Vi Vr Vi Vr Vi

36 Lecture/s Interconnects SLIDE 32 Impedance and Reflections 400Ω S 50Ω, 5ns R 1V 1KΩ Vline TIME

37 Lecture/s Interconnects Reflections, Z S < Z 0 SLIDE 33 V I Z S V S Z 0 TD = 250 ps V L Z L Z S = 25 Ω Z 0 = 50 Ω Z L = inf Ω V I = 0v 2v V S = V I Z S Z S + Z 0 = 2 * = V k r (load) = Z L - Z 0 inf - 50 = = 1 Z L + Z 0 inf + 50 k r (source) = Z S - Z = = Z S + Z

38 Lecture/s Interconnects Reflections, Z S < Z 0 SLIDE 34 k r (load) = 1 k r (source) = V I Z S V S Z 0 TD = 250 ps V L Z L Time (ps) V S V L v 0 v v 1.33 v v 2.66 v v v v v 1.77v

39 Lecture/s Interconnects SLIDE 35 Reflections, Z S < Z 0 Volts 2.5v V load V source 2.0v 1.5v 1.0v 0.5v Time (ps) 1750

40 Lecture/s Interconnects SLIDE 36 Add In Capacitance 50Ω S 50Ω, 5ns R 1V What if we throw in a capacitor (i.e., reality?) Simple case: matched impedance at source end Receiving end Vline Source end TIME

41 Lecture/s Interconnects Impedance and Reflections DIMMs SLIDE 37 Package Pins & Connectors DRAMs CPU Mem Contr. PCB Traces Electrical connections over physical contacts Modern systems have MANY, MANY, MANY potential sources of impedance-mismatch and/or reflections

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44 Memory Systems Architecture and Performance Analysis Capacitive Termination I Spring 2005 ENEE 759H Lecture13.fm V S Z 0 V L David Wang V I Z S Z L SLIDE 40 Z L = 0; Short Circuit Z L = inf; Open Circuit ρ = 0 - Z S 0 + Z S ρ = -1 ρ = Z L Z L ρ = 1 - Capacitors behave like short circuit when not charged. Once charged, behaves like open circuit.

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46 Memory Systems Architecture and Performance Analysis What is a Stub? Spring 2005 ENEE 759H Lecture13.fm David Wang trace terminating resistor SLIDE 42 Z 0 = 50 Ω trace pkg bond wire 5nH 50 Ω 50Ω 75Ω GND 0.2 pf 2 pf pad & rx Stub - Signal path inside of package also significant

47 Memory Systems Architecture and Performance Analysis Series Stub Terminated Logic Spring 2005 ENEE 759H Lecture13.fm Z 0 = 50 Ω 25 Ω bond wire 5nH David Wang series resistor 0.2 pf GND 2 pf pad & rx SLIDE 43 Reflection Coefficient = ρ = Z L - Z S Z L + Z S ρ = = Series resistor isolates stub from line - reduces ringing - reduces power

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55 Lecture/s Interconnects SLIDE 46 Inductive Noise L di/dt noise (ground bounce): VDD Current flow changes direction when input (thus output) values change VDD L ( 0) IDEAL Magnitude of current change is di The time to switch directions is dt The voltage-drop induced on this wire at time of switching is L di/dt L ( 0) REALISTIC

56 Lecture/s Interconnects SLIDE 47 Inductive Noise L di/dt noise (ground bounce): VDD 1 Another inverter, elsewhere. What comes out here? VDD L ( 0) I/O Driver: V = L di/dt = voltage-drop induced on this wire V L ( 0) V

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60 Lecture/s System Timing SLIDE 12 Definitions: Skew clock - clock skew Sub Channel 1 Sub Channel 2 data - data skew - Static timing displacement from ideal design - Caused by differences in signal path characteristics - Total timing budget must take data-data skew, data-clock skew as well as clock-clock skew into cycle budget consideration

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62 Lecture/s System Timing Definitions: Jitter SLIDE 13 - Dynamic timing displacement from nominal timing characteristics - Magnitude and offset of timing displacement could depend on: previous signal state(s), current signal state(s), supply voltage level(s), crosstalk, variations in thermal characteristics. Perhaps even phases of the moon (not proven).

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64 Lecture/s System Timing Global Clock I Transmitter Receiver D Q D Q 0 2 Data 3 5 SLIDE 53 1 Clock : Assume data is stable for setup time before clock edge 1: Rising edge of transmitter clock 2: Transmitter begins to drive data (perhaps through logic) 3: Signal reaches input of receiver. 4: Rising edge of receiver clock 5: Receiver latches data and drives internal signal lines 5

65 Lecture/s System Timing SLIDE 54 Global Clock II: Parallel Data Transmitter Receiver D Q D Q 2 Data 3 5 Clock Data 3 5 D Q D Q transmitter input transmitter clock transmitter output 0 & 0 1 & 1 2 & 2 receiver input receiver clock 3 & 3 4 & 4 receiver output 5 & 5 - Skew and jitter eats into timing budget - Luckily, uncertainty does not accumulate beyond latches

66 Lecture/s System Timing What Needs To Be Done? SLIDE 3 Clk SRC By the way: global clock scheme

67 Lecture/s System Timing SLIDE 4 Background: Elmore Delays τ Di = N k = 1 C k R ik N 3 R 4 C4 N 4 R 3 C 3 Clk SRC R 1 N 1 N 2 C1 R 2 C2

68 Lecture/s System Timing SLIDE 5 Background: Elmore Delays τ Di = N k = 1 C k R ik 1 τ D3 = 6 τ D4 = 7 C 1 + C 2 + 2C 3 + 2C C 1 + C 2 + 2C 3 + 3C 4 1 τ D1 = 4 τ D2 = 5 Clk SRC 1 1 C 1 + C 2 + C 3 + C C 1 + 2C 2 + C 3 + C 4

69 Lecture/s System Timing End Result: Clock Skew SLIDE 6 1 time unit Clk SRC In general, even nearby clocks not in synch

70 Lecture/s System Timing Clock Tree I SLIDE 59 Every branch sees same wire length and capacitance The clock skew is theoretically zero Clock distribution is a major design problem! The sub-blocks should be small enough s.t. the skew within the block is tolerable Essential to consider clock distribution early in the design process

71 Lecture/s System Timing Clock Tree I SLIDE 60 An on-chip clock tree

72 Lecture/s System Timing Clock Tree II (I with buffers) SLIDE 61 buffer chips could have +/- xx% tolerance - Large synchronous systems require all components (chips or registers) to be driven by clock signal. - Clock signal paths and buffers could introduce both skew and jitter at each stage - Jitter and skew are additive with larger systems. More buffering, more skew and jitter.

73 Lecture/s System Timing DEC Alpha SLIDE M Transistors, 4 metal layers, 0.55µm Clock Freq: 300 MHz Clock Load: 3.75 nf Power in Clock = 20W (out of 50W) Two Level Clock Distribution: Single 6-stage driver at center Secondary buffers drive left and right side Max clock skew less than 100psec Routing the clock in the opposite direction Proper timing

74 Lecture/s System Timing Clock Skew in Alpha SLIDE 63

75 Lecture/s System Timing Phase Locked Loop SLIDE 65 D VCO Freq/ Phase Loop Filter φ out - Given a data signal, recover the frequency and phase of the data signal, generate local reference clock φ out - Local reference clock may be frequency multiple of input clock - PLL depends on data input to provide enough signal transitions to lock onto, else PLL could lose coherency. - Modern processors utilize PLL s for frequency multiplication

76 Lecture/s System Timing Voltage Controlled Oscillator SLIDE 66 Ring Oscillator - VCO may be designed from ring oscillator where voltage controls the number of (odd) stages of inverters in the feedback ring L C(v) LC Oscillator (conceptual illustration) - VCO may be designed from resonant oscillator where voltage controls capacitance in LC circuit.

77 Lecture/s System Timing Delay Locked Loop SLIDE 67 D φ r Phase Comp φ Loop Filter φ out - Given a data signal and reference clock, compare and adjust phase of local clock signal by φ - Unlike PLL, requires reference clock - Hence, no need to recover clock signal with VCO - Modern DRAM with dual edged clocking utilizes DLL s for phase compensation. (gets you 90 degrees)

78 Lecture/s System Timing Zero-Skew Clock Distribution SLIDE 68 PLL or DLL

79 Lecture/s System Timing DLL in DDR SDRAM This represents a delay D of the clock signal from clock input pad to data output drivers D CK EXT CK Buffers CK EXT CK INT SLIDE 69 DRAM Array CMD READ DQ EXT CK INT Data DQ EXT Additional delay through DQ drivers Ideally, these two edges would be aligned This represents a delay D of the clock signal from clock input pad to data output drivers Delay DLL + D D Delay DLL The DLL delays the internal clock (CK INT ) so that the total delay equals one full clock cycle, and thus CK INT is now in sync with CK EXT thus, DQ EXT is also (roughly) in sync with CK EXT CK EXT Delay CK Buffers CK EXT Delay introduced by DLL CK INT DRAM Array CMD READ Filter DQ EXT Phase Comp CK INT Data DQ EXT Additional delay through DQ drivers These two edges now more closely aligned The Phase Comparison, Loop Filter, and Variable Delay components constitute a DLL

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81 Lecture/s System Timing Idea: Detect 0 vs. 1 D Q Data D Q SLIDE 7 Clock V 1 t bit V 0 This is a 1 V 1 t bit V 0 This is a 0 V eye t eye V 0 V 1 EYE: space between 1 & 0

82 Lecture/s System Timing Basic Problem: Voltage Noise D Q Data D Q SLIDE 8 Clock V eye Data signal with t eye voltage noise Clock signal with voltage noise Voltage noise reduces operating margins

83 Lecture/s System Timing Basic Problem: Timing Noise D Q Data D Q SLIDE 9 Clock t eye V eye Data signal with timing noise Clock signal with timing noise Timing noise reduces operating frequency

84 Lecture/s System Timing Basic Problem: Both D Q Data D Q SLIDE 10 Clock t eye V eye Data signal with both noise sources Clock signal with both noise sources Note: Clock signal is just another signal subject to same constraints of voltage noise, skew and jitter as data signals

85 Lecture/s System Timing Eye Diagram SLIDE 11 Yes, there really is that much voltage noise; Yes, there really is that much timing noise Life sucks; deal with it.

86 Lecture/s System Timing SLIDE 64 Dual Edge Clocking Data Clock - Only one edge of clock latches data - Duty cycle of clock signal is not relevent - Clock signal operating at 2X switching rate of data - Always a clock edge where you need one Data Clock - Both edges of clock used to latch in data - Duty cycle & rise/fall times of clock must be even - Clock signal must be phase shifted by 90 degrees relative to phase of data signal - How do you get 90 degrees??

87 Lecture/s System Timing Cycle Budget t tran t skew t eye SLIDE 14 t cycle t skew = max(skew) + max(jitter) t tran = Edge transition time = max(rise_time, fall_time) t eye t cycle t tran t skew

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89 Lecture/s System Timing SLIDE 15 Timing: Clock Data Define when a value is present on a line How many 1 s? How many 0 s? Need convention to distinguish where one 1 ends and next 1 begins conventions typically mark boundaries w/ TRANSITIONS of the signal itself of an associated clock signal (original definition of synchronous ) Uncertainty in timing limits operating speed

90 Lecture/s System Timing Timing Conventions SLIDE 16 Apply to both inter- and intra-chip signaling

91 Lecture/s System Timing SLIDE 17 Setup Time Required time for input to be stable BEFORE CLOCK EDGE

92 Lecture/s System Timing Setup Time Fix SLIDE 18

93 Lecture/s System Timing Setup Time Fix II SLIDE 19

94 Lecture/s System Timing SLIDE 20 Hold Time Required time for input to be stable AFTER CLOCK EDGE

95 Lecture/s System Timing Hold Time Violations SLIDE 21

96 Lecture/s System Timing SLIDE 23 A Tale of Two (or more) Timing Conventions Synchronous: global clock Synchronous: source-synchronous I ( open-loop meaning no control loop) Synchronous: source-synchronous II ( closed loop meaning feedback control) Asynchronous: self-timed

97 Lecture/s System Timing SLIDE 24 System Building Blocks DELAY ELEMENTS Nominal delay Timing uncertainty, skew, jitter COMBINATIONAL LOGIC Contamination delay Propagation delay CLOCKED STORAGE ELEMENTS Align signal to a clock Signal waits to be sampled by clock Output held steady until next clock

98 Lecture/s System Timing SLIDE 25 Edge-Triggered Register Samples data on rising edge of CLK Data must remain valid during an aperture of time during sampling Output held steady until next CLK edge Output is held until a contamination delay following CLK edge Tcontamination Tpropagation Output has a correct value after a propagation delay following CLK edge

99 Lecture/s System Timing SLIDE 26 Other Storage Elements LEVEL-SENSITIVE LATCH Passes data through when enable (clock) is high Holds data stable when enable (clock) is low DUAL-EDGE-TRIGGERED FLIP-FLOP/REGISTER Samples data at both edges of the clock Internally two interleaved flip-flops (1 posedge FF + 1 negedge FF) Allows CLK to run at same speed as data

100 Lecture/s System Timing SLIDE 27 Eye Diagram, Redux MAXIMUM OPERATING RATE (i.e., signaling speed) LIMITED BY THREE FACTORS: t bit Tr Transition time (rise/fall time) Tu Timing uncertainty, skew, jitter Ta Aperture time Tbit Tr + Tu + Ta (but not that simple )

101 Lecture/s System Timing SLIDE 28 Synchronous Timing I GLOBAL CLOCK (Conventional) EXAMPLE 6.25ns ± 0.1ns Tx 8 data lines Rx B1 B4 B1 400MHz Matched Lines ± 0.1ns (1.5cm) B4 Parameter Symbol Nominal Skew Jitter Bit Cell (data period) Tbit 2.5 ns Transmitter Rise Time Tr 1.0 ns Cable Delay Twire 6.25 ns 100 ps Receiver Aperture Ta 300 ps 100 ps 50 ps Transmitter Delay 500 ps 150 ps 50 ps Buffer Stage Delay B# 250 ps 100 ps 50 ps

102 Lecture/s System Timing SLIDE 29 Synchronous Timing I Sources of uncertainty: Skew (across multiple lines) of line delay B1 B1 400MHz B4 Tx 6.25ns ± 0.1ns 8 data lines Matched Lines ± 0.1ns (1.5cm) B4 Rx Jitter of Tx, Rx, and line delay Skew and jitter of global clock (usually large due to high fan-out) For best performance, center sampling edge on data eye Ta = 300ps Tbit - Tr = 1.5ns Tbit = 2.5ns Margin = 600ps Gross timing margin = 1/2 [ Tbit - Tr - Ta] = ± 600ps = 1/2 Tu?

103 Lecture/s System Timing SLIDE 30 An Aside Why do we simply add up the uncertainties? And why does each effectively count twice? DATA w/ no skew/jitter CLOCK w/ no skew/jitter 1 time unit 1 time unit DATA early by 1 time unit CLOCK late by 1 time unit 2 time units

104 Lecture/s System Timing Synchronous Timing I SLIDE 31 TIMING ANALYSIS Clock Skew: 100ps lines + 100ps B ps B4 B1 B1 400MHz B4 Tx 6.25ns ± 0.1ns 8 data lines Matched Lines ± 0.1ns (1.5cm) B4 Rx Clock Jitter: 50ps B ps B4 [CLKs times 2: one for xmit, one for recv] Transmitter: 150ps skew, 50ps jitter Receiver: 100ps skew, 50ps jitter Data Cable: 100ps skew TOTAL: 1550ps skew, 600ps jitter (BAD)

105 Lecture/s System Timing Synchronous Timing I LIMITS TO LINE DELAY & DATA FREQUENCY B1 B4 Tx 6.25ns ± 0.1ns 8 data lines Rx SLIDE 32 B1 Conventional Wisdom: 400MHz Line Delay Must Be ODD NUMBER of HALF-BITS WHY? Matched Lines ± 0.1ns (1.5cm) B4 0 half-bits For fixed line length and tight margins, this limits the bus speeds that can be used

106 Lecture/s System Timing Synchronous Timing I SUMMARY B1 B4 Tx 6.25ns ± 0.1ns 8 data lines Rx SLIDE 33 GLOBALLY SYNCHRONOUS DESIGN: B1 400MHz Matched Lines ± 0.1ns (1.5cm) B4 For long wires and high speeds, only a handful of frequencies work Impractical to control uncertainties Cannot switch frequencies

107 Lecture/s System Timing Synchronous Timing II PIPELINED TIMING: BASIC IDEA SLIDE 34 Delay the clock by the same amount as data PLUS half a bit-cell System will work from DC to maximum theoretical frequency 1/(Tr + Tu + Ta) Defines new clock domain at receiving end

108 Lecture/s System Timing SLIDE 35 Synchronous Timing II SOURCES OF UNCERTAINTY SKEW: Between CLK & Data line Fixed differences in FF, Tx, Rx delays Different CLK delays to different FFs Aperture offset in Rx FF Extra offset in the delayed CLK line JITTER: In Tx clock In FF, Tx, Rx delays

109 Lecture/s System Timing SLIDE 36 Synchronous Timing II OPEN-LOOP PIPELINED EXAMPLE Tx Rx 6.25ns ± 0.1ns Data In 8 data lines Sync Toggle 6.25ns ± 0.1ns RClk 90 B1 B4 B1 200MHz Lines need not be matched B4 Internal Clock Network

110 Lecture/s System Timing Synchronous Timing II SLIDE 37 TIMING ANALYSIS Xmit data: 150ps skew, 50ps jitter Data In Toggle B1 B4 Tx 6.25ns ± 0.1ns 8 data lines 6.25ns ± 0.1ns RClk 90 Rx Sync Internal Clock Network Xmit toggle: 150ps skew, 50ps jitter B1 200MHz Lines need not be matched B4 Receiver: 100ps skew, 50ps jitter Data cable: 100ps skew Toggle clock cable: 100ps skew TOTAL: 600ps skew, 150ps jitter (BETTER)

111 Lecture/s System Timing SLIDE 38 Synchronous Timing III CLOSED-LOOP PIPELINED EXAMPLE Tx Rx 6.25ns ± 0.1ns Data In 8 data lines Sync Toggle 6.25ns ± 0.1ns RClk B1 B4 FSM B MHz Lines need not be matched B4 To rest of receive chip Variable delay line can cancel ALL SKEW

112 Lecture/s System Timing SLIDE 39 Synchronous Timing III COMPONENTS of CONTROL LOOP (DLL) Ref. Clock (Input) Variable delay line (control) Delayed Clock (Output) Rx Sync Ref. Data/CK (Input) Phase Compare Loop Filter DFF as a Phase Comparator B D Q Y FSM A 90 Y PHASE AB

113 Lecture/s System Timing SLIDE 40 Synchronous Timing III TIMING ANALYSIS Xmit data: 50ps jitter Recv data: 50ps jitter Data In Xmit toggle: 30ps skew data/toggle (0?), 50ps jitter Toggle B1 B1 200MHz B4 Tx 6.25ns ± 0.1ns 6.25ns ± 0.1ns RClk Lines need not be matched 8 data lines B4 Rx Sync FSM 90 To rest of receive chip Recv toggle: 20ps skew (0?), 50ps jitter Data cable: 100ps skew Toggle clock cable: 100ps skew TOTAL: 250ps skew, 200ps jitter (GOOD!)

114 Lecture/s System Timing SLIDE 41 Synchronous Timing II & III LIMITS TO LINE DELAY & DATA FREQUENCY None. Data In Toggle B1 B1 200MHz B4 Tx 6.25ns ± 0.1ns RClk Lines need not be matched 6.25ns ± 0.1ns 8 data lines B4 90 Rx Internal Clock Network Sync Only limiter to bus frequency is the rate at which you can successfully transmit & receive data (e.g. Taperture + Tuncertainty + Ttransmit) Data In Toggle B1 B1 200MHz B4 Tx 6.25ns ± 0.1ns 8 data lines 6.25ns ± 0.1ns RClk Lines need not be matched B4 Rx Sync FSM 90 To rest of receive chip

115 Time CK CMD DATA A DATA B DATA C Memory Controller Clock domains: CK DQS CMD Bus DATA Bus DRAM A DRAM B DRAM C Delay through each DRAM equals quarter of an hour on clock Data from A: Data from B: Data from C: