Overcoming Obstacles to Closing Timing for DDR and Beyond. John Ellis Sr. Staff R&D Engineer Synopsys, Inc.

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Overcoming Obstacles to Closing Timing for DDR3-1600

1 Overcoming Obstacles to Closing Timing for DDR and Beyond John Ellis Sr. Staff R&D Engineer Synopsys, Inc.

2 Agenda Timing budgets Mbps? Static vs. Dynamic Uncertainty Sources Benefits of Deskew Technologies Reducing Dynamic Uncertainty Crosstalk, ISI and Reflections Package Power Delivery Conclusions 2

3 DDRn Timing DDR Interfaces are Source Synchronous Total delay doesn t matter (within reason) Delay difference or Skew is Critical Strobe (DQS) Set up Hold Vref ASIC DRAM1 DRAM2 Strobe Data (DQ) Delay of DQ must tightly match the delay of differential DQS Optimal Strobe placement maximizes Set up and Hold Data Vref (Data Write Shown) 3

4 Three Regions of Uncertainty Host Launch signals in quadrature during Write Operations, Center Strobe within Data during Reads SDRAM Receive signals during Writes, launch edge-aligned during Reads Interconnect Maintain alignment and signal integrity between Host and SDRAM Power delivery 90 Strobe Write Strobe Read Data Launched 90 Out of Phase with Strobe Data Received Edge- Aligned with strobe 4

5 Uncertainty Contributors within the Host Signal skew between Data and Strobe within the PHY Clock Skew with in the PHY Across silicon process and line width variation Jitter from source clock or DLL if applicable Delay differences between rising and falling edges. Granularity of delay line structures 5

6 SDRAM Consumes ~50% of the Available Read and Write Budgets at 1600Mbps+ Set Up and Hold Output Skew and Hold Skew Factor 6

7 Agenda Timing budgets Mbps? Static vs. Dynamic Uncertainty Sources Benefits of Deskew Technologies Reducing Dynamic Uncertainty Crosstalk, ISI and Reflections Package Power Delivery Conclusions 7

Static Uncertainty Static uncertainty is timing uncertainty that does not vary with switching patterns or number of signals switching Example Routing skew between DQ and DQS Skew:

8 Static Uncertainty Static uncertainty is timing uncertainty that does not vary with switching patterns or number of signals switching Example Routing skew between DQ and DQS Skew: PCB, PHY, Internal Clock Skew Deskew can remove most static uncertainty Training sequence implemented Bits are first aligned Strobe is placed in center of newly constructed eye. 8

9 Dynamic Uncertainty Dynamic uncertainty will vary with switching patterns. Example Crosstalk, ISI, SSO pushout, reflections from modal impedance changes Cannot be reliably deskewed since it can vary on a bit by bit basis. ISI A Q Crosstalk SSO Pushout 9

10 Agenda Timing budgets Mbps? Static vs. Dynamic Uncertainty Sources Benefits of Deskew Technologies Reducing Dynamic Uncertainty Crosstalk, ISI and Reflections Package Power Delivery Conclusions 10

11 Dynamic Uncertainty Crosstalk. Timing Impact of Cross section No coupling Odd Mode Even Mode In Stripline: Signals will travel at the same velocities no matter what coupling modes are excited because of the uniform dielectric. In Microstrip: Different coupling modes will travel at different velocities because of the impact of the mixed dielectric cross section. Stripline Microstrip 11

12 Different Modes Yield Different Flight Times No Coupling Odd Mode Even Mode Odd coupled arrives 27ps earlier Even coupled arrives 31ps later Total uncertainty is 59 ps 12

13 Longer Length = Greater Divergence ODD EVEN 59ps 2 routed length yields 59ps of uncertainty ODD 2 Routed Length EVEN 148ps 6 routed length yields 148ps of uncertainty 6 Routed Length 13

14 Striplines Have Equal Mode Velocities Whether uncoupled or Even or Odd coupled, mode velocities are the same in stripline. 148ps ODD 6 Microstrip EVEN Total divergence in 6 of stripline ~30ps EVEN ODD and UNCOUPLED 30ps 6 Stripline 14

15 Options for Reducing Timing Divergence Increased spacing equals increase isolation Increased soldermask thickness yields more uniform dielectric constant No Coupling Odd Mode Even Mode 15

16 Intersymbol Interference and DDR Signaling 2 Vs. 6 1 Load Vs. 2 Loads 554ps 525ps 554ps 500s Routed lengths on DDR signals are relatively short, < 6 typically. Fly-by Address can be considerably longer The number of SDRAM loads will have a larger ISI effect on the interface. 16

17 Termination Mismatch can be a Significant Contributor 468ps 525ps 17

18 ISI and Reflections lead to Uncertainty at the Vref Level 95ps 39ps 24ps 19ps 22ps 24ps 18

19 Switching Modes also Impact PCB Impedance 59Ω TDR traces 71Ω 49Ω 19

20 How SSO Impacts Timing 303ps 294ps 73ps 257ps 230ps 20

21 Use DDR Devices as a Guide for Power Ratios DDR3 SDRAM Device Try to match the via/ball count to the number of power/ground pad connections as closely as possible 21

22 Carry Ratios Through Entire Connection 1/2 the number of connections as a minimum should be the goal. It is important that the via/ball connections be regularly spaced around the die to minimize the size of the current loops. Place signal trace vias near vias from the reference layer to minimize current loop size and resulting crosstalk 22

23 Agenda Timing budgets Mbps? Static vs. Dynamic Uncertainty Sources Benefits of Deskew Technologies Reducing Dynamic Uncertainty Crosstalk, ISI and Reflections Package Power Delivery Conclusions 23

24 In Summary As data rates exceed 1600Mbps, the SDRAM requirements will consume ~50% of the budget. Deskew solutions are available, but they will only correct for static offsets between the data and its related strobe. They don t work on dynamic contributors. Good interconnect design can retrieve a great deal of margin. Pay attention to modal effects especially in microstrip configurations. Pay attention to package power/ground to signal ratios as well as placement of vias and balls to control inductance. 24

25 25 Predictable Success

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