An Engineer s Guide to Automated Testing of High-Speed In ter faces

Transcription

1

2 An Engineer s Guide to Automated Testing of High-Speed In ter faces

3 For a list ing of re cent ti tles in the Artech House Mi cro wave Li brary, turn to the back of this book.

4 An Engineer s Guide to Automated Testing of High-Speed In ter faces José Moreira Hubert Werkmann artechhouse.com

5 Li brary of Con gress Cataloging- in- Publication Data A cata log rec ord for this book is avail able from the U.S. Li brary of Con gress. Brit ish Li brary Cat a logu ing in Pub li ca tion Data A cat a logue re cord for this book is avail able from the Brit ish Li brary. ISBN Cover de sign by Igor Valdman 2010 ARTECH HOUSE 685 Can ton Street Norwood, MA All rights re served. Printed and bound in the United States of Amer ica. No part of this book may be re pro duced or uti lized in any form or by any means, elec tronic or mechanical, in clud ing pho - tocopying, recording, or by any information storage and retrieval system, without permission in writ ing from the pub lisher. All terms men tioned in this book that are known to be trade marks or ser vice marks have been ap pro pri ately cap i tal ized. Artech House can not at test to the ac cu racy of this in for ma tion. Use of a term in this book should not be re garded as af fect ing the va lid ity of any trade mark or ser vice mark

6 Para os meus pais Inês e José e o meu irmão Carlos José Moreira For everyone who supported me getting to the next levels whenever, wherever Hubert Werkmann

7

8 Contents Preface xvii 1 Introduction Characterization and Design Verification Production Testing Accuracy and Correlation The ATE Test Fixture The Future 7 References 7 2 High-Speed Digital Basics High-Speed Digital Signaling Out-of-Band Signaling Data Eye Diagram Differential Signaling Transmission Line Termination Time and Frequency Domains The Concept of Bandwidth and Its Pitfalls Bit Error Rate Jitter Jitter Histogram Jitter Categorization 26 vii

9 viii An Engineer s Guide to Automated Testing of High-Speed Interfaces Amplitude Noise and Conversion to Timing Jitter Jitter in the Frequency Domain Classification of High-Speed I/O Interfaces Hardware Building Blocks and Concepts Phase Locked Loop (PLL) Delay Locked Loop (DLL) Clock and Data Recovery (CDR) Pre-Emphasis/De-Emphasis and Equalization 49 References 53 3 High-Speed Interface Standards PCI Express Application Areas PCI Express Fundamentals PCI Express Details PCI Express Protocol Electrical Specifications ATE Test Requirements Test Support Test Challenges HyperTransport Application Areas HyperTransport Protocol Electrical Specifications Test Support Test Requirements Test Challenges XDR DRAM Application Areas XDR Fundamentals XDR DRAM Details XDR Protocol Electrical Specifications ATE Test Requirements Test Support Test Challenges GDDR SDRAM Application Areas 107

10 Contents ix GDDR Fundamentals GDDR5 Details GDDR5 Protocol Electrical Specifications ATE Test Requirements Test Support Test Challenges Other High-Speed Digital Interface Standards 127 References ATE Instrumentation for Digital Applications Digital Pin Electronics ATE Card CDR and Phase Tracking Equalization Time Interval Analyzer or Time Stamper Timing Jitter Injection Amplitude Noise and Common Mode Voltage Injection Bidirectional and Simultaneous Bidirectional Support Protocol Engine ATE Loopback Path Parametric Measurements Sampler/Digitizer ATE Card Aliasing Digitizer Sampler Parametric Measurements with Sampled Data Undersampling of High-Speed I/O Signals Coherency Equation Capturing Digital Waveforms Special Considerations for Coherent Sampling with Digital ATE Channels Power Supplies 160 References Tests and Measurements Bit and Pattern Alignment Bit Alignment Pattern Alignment 168

11 x An Engineer s Guide to Automated Testing of High-Speed Interfaces 5.2 Functional Test Shmoo Tests Fundamental Driver Tests Rise/Fall Time Data Eye Diagram BER Bathtub Curve Skew Pre-Emphasis and De-Emphasis Measurement Driver Jitter Tests Jitter Histogram RMS Jitter Peak-to-Peak Jitter Measuring the Jitter Spectrum Random and Deterministic Jitter Separation Measuring the Data Dependent Jitter Jitter Measurement Correlation Driver Amplitude Noise Fundamental Receiver Tests Setup and Hold Receiver Sensitivity Receiver Jitter Tolerance Random Jitter Tolerance Sinusoidal Jitter Tolerance DDJ Jitter Tolerance Testing the Receiver Equalizer PLL Characterization Jitter Transfer Frequency Offset Spread Spectrum Clocking Other Tests Impedance Tests Return Loss Measurement Errors 233 References 234

12 Contents xi 6 Production Testing Golden Device System Level Test Instrument-Based Testing: At-Speed ATE Physical Implementation Parametric Testing Instrument-Based Testing: Low-Speed ATE Double Data Clocking Channel Multiplexing Near-End Loopback Testing Instrument-Based Testing: Bench Instrumentation Active Test Fixture Multisite Testing Driver Sharing for Multisite Applications 263 References Support Instrumentation Oscilloscopes Real-Time Oscilloscopes Equivalent-Time Sampling Oscilloscopes Bit Error Rate Tester Time Interval Analyzer Spectrum Analyzer Vector Network Analyzer Arbitrary Waveform and Function Generators Noise Generators Sinusoidal Clock Sources Connecting Bench Instrumentation to an ATE System Signal Integrity Synchronization External Reference Clock Impact on Jitter Measurements Coaxial Cables and Connectors Coaxial Cables 287

13 xii An Engineer s Guide to Automated Testing of High-Speed Interfaces Coaxial Connectors Accessories Power Splitters and Power Dividers/Combiners Attenuators, Blocking Capacitors, and Terminations Pick-Off T Delay Lines Probes Balun Rise Time Converters 308 References Test Fixture Design Test Fixtures High-Speed Design Effects Reflections Due to Impedance Mismatches Conductor Losses Dielectric Losses Crosstalk Impedance Controlled Routing Microstrip and Striplines Differential Routing Via Transitions Interlayer Vias Pogo Pin Vias DUT BGA Ballout Sockets Socket Electrical Characterization Relays Bidirectional Layout Wafer Probing Stack-Up Power Distribution Network Power Planes Decoupling Capacitors Socket Inductance 383

14 Contents xiii Power Distribution Network Design Power Distribution Network Simulation 384 References Advanced ATE Topics ATE Specifications and Calibration Accuracy and Resolution Understanding OTA and EPA Linearity and Edge Placement Accuracy Calibration Multiplexing of ATE Channels Focus Calibration Skew Calibration Data Eye Height Calibration Jitter Injection Data Eye Profile Testing of High-Speed Bidirectional Interfaces with a Dual Transmission Line Approach Including the DUT Receiver Data Recovery in Driver Tests Protocol Awareness and Protocol-Based Testing Testing Multilevel Interfaces with Standard Digital ATE Pin Electronics Signal Path Characterization and Compensation Signal Path Loss Compensation: De-Embedding Characterization in the Frequency Domain Signal Path Loss Compensation: Equalization ATE DC Level Adjustments Correction of Force Levels for DUT Input Pins Correction of Levels for DUT Output Pins 442 A References 445 Introduction to the Gaussian Distribution and Analytical Computation of the BER 449 A.1 The Gaussian Distribution 450

15 xiv An Engineer s Guide to Automated Testing of High-Speed Interfaces A.2 Computation of the BER for a System with Only Gaussian Random Jitter 453 A.3 Computation of the α(ber) Value 456 A.4 Properties of the Error Function erf(x) and Complementary Error Function erfc(x) 458 References 459 B The Dual Dirac Model and RJ/DJ Separation 461 B.1 The Dual Dirac Jitter Model 461 B.2 RJ/DJ Separation with the Q-Factor Algorithm 465 References 467 C Pseudo-Random Bit Sequences and Other Data Patterns 469 C.1 Pseudo-Random Bit Sequences 469 C.2 Pseudo-Random Word Sequences 470 C.3 Other Important Patterns 472 References 473 D Coding, Scrambling, Disparity, and CRC 475 D.1 Disparity 476 D.2 8B/10B Coding 478 D.3 Scrambling 481 D.4 Error Detection 484 D.4.1 Parity Bits 485 D.4.2 Checksums 485 References 488 E Time Domain Reflectometry and Time Domain Transmission (TDR/TDT) 491 E.1 TDR 492 E.1.1 Measuring the Impedance of a Trace with a TDR 493 E.1.2 Measuring the Round-Trip Delay of a Signal Trace 494 E.1.3 Measuring Discontinuities on a Signal Path with a TDR 495

16 Contents xv E.1.4 Measuring the Return Loss with a TDR 495 E.2 TDT 497 E.2.1 Measuring the Step Response 497 E.2.2 Measuring the Insertion Loss with a TDT 498 E.2.3 Measuring Crosstalk Using a TDT and an Extra Sampler 498 E.3 Differential TDR/TDT Measurements 499 References 501 F S-Parameters 503 F.1 Simulating and Synthesizing Time-Domain Responses from S-Parameters 509 F.2 S-Parameters of Coupled Differential Pairs and Structures 511 References 513 G Engineering CAD Tools 515 G.1 Circuit Simulators 515 G.2 3D EM Field Solvers 518 G.3 2D Planar Field Solvers 518 G.4 Power Integrity 520 G.5 Model Generation 521 G.6 Other Tools 521 References 524 H Test Fixture Evaluation and Characterization 525 H.1 Measuring the Test Fixture Performance 525 H.1.1 Test Coupons 527 H.1.2 Test Fixture Socket and Socket Via Field Probing 529 H.2 Measuring the Test Fixture Power Distribution Network 535 References 540 I Jitter Injection Calibration 543 I.1 Sinusoidal Jitter Injection Calibration 543 I.1.1 The J 1 /J 0 Bessel Approach 544 I.1.2 The RJ Subtraction Approach 548

17 xvi An Engineer s Guide to Automated Testing of High-Speed Interfaces I.2 Random Jitter Injection Calibration 551 I.3 ISI Jitter Injection Calibration 555 References 557 About the Authors 559 Index 561