Building IBIS-AMI Models From Datasheet Specifications

Transcription

1 TITLE Building IBIS-AMI Models From Datasheet Specifications Eugene Lim, (Intel of Canada) Donald Telian, (SiGuys Consulting) Image

2 SPEAKERS Eugene K Lim Hardware Design Engineer, Intel Corporation eugene.k.lim@intel.com intel.com Eugene K Lim is a hardware design engineer in the Non Volatile Memory(NVM) System Engineering group at Intel Corporation. He has developed FPGA designs for NAND emulation systems, design production and silicon validation PCBs. In addition to PCIe PHY compliance validation, he is currently responsible for the group s product DDR3/4, ONFI4 interface signal integrity and PCIe/SATA Signal Integrity Kits. Eugene received his BSEE and MSc degrees from McGill University. Donald Telian Founder, SiGuys Consulting telian@siguys.com siguys.com Donald Telian is an independent Signal Integrity Consultant and Owner of SiGuys. Building on over 30 years of SI experience at Intel, Cadence, HP, and others, his recent focus has been on helping customers correctly implement today s Multi-Gigabit serial links. His numerous published works on this and other topics are available at his website Donald is widely known as the SI designer of the PCI bus and the originator of IBIS modeling and has taught SI techniques to thousands of engineers in more than 15 countries.

3 AGENDA: Building AMI Models Introduction AMI Model Development Lab Measurement & Correlation Summary Building AMI Models

4 INTRODUCTION Tx CHANNEL Rx To model a serial link: Tx, Channel, Rx What? No models? whining What do I have? (similar models, spec models, tool models ) What can I do? (tdr, vendor help, continuous improvement ) How to form (and improve) an AMI model when it s not there

5 AMI Template Models FFE an alternative solution. Tr/Tf CTLE DFE AMI dlls AMI Model

6 AGENDA Introduction AMI Model Development Tx / Rx Parameters Issues & Solutions Lab Measurement & Correlation Summary Building AMI Models

7 DEVELOPMENT: TX PARAMETERS Model FIR Filter parameters: tx_tap_preset, Tx Preset Labels tap_filter.-1, pre cursor or C -1 tap_filter.0, main cursor or C 0 tap_filter.1, post cursor of C +1 Model AFE parameters: Rs, Transmitter Impedance Trf, Rise/Fall Time Tx_swing, Diff Voltage Swing Cc, Transmitter Capacitance Tx_DCD, Tx Duty Cycle Distortion Tx_Dj, Tx Deterministic Jitter Tx_Rj, Tx Random Jitter

8 DEVELOPMENT: TX ISSUES & SOLUTIONS Vendor provided C -1, C 0 and C +1 values were not in normalized ratio format. Given equation in Figure 4-41, the respective ratio of C -1, C 0 and C +1 to Full Swing values were used for the model tap_filter parameters. Preshoot and De-emphasis values were obtained from equation in Figure 4-42 from Va, Vb, Vc provided by vendor. PCIe Gen3 Base Spec Rev3.0

9 DEVELOPMENT: RX PARAMETERS Model Analog Model parameters: Rt, Rx Differential Impedance Cc, Rx Capacitance Model AGC Filter parameters: Level, Rx gain/attenuator value Model Peaking Filter parameters: poles,zeros,gains, describes the CTLE frequency response Model CDR parameters: Rj,Dj CDR jitter parameters

10 DEVELOPMENT: RX CTLE PCIe Gen3 Base Spec Rev3.0 Device RX CTLE Frequency Response has wider range of peaking filter gains compared to PCIe Spec CTLE frequency response.

11 DEVELOPMENT: RX ISSUES & SOLUTIONS Device Model Device has feedback path between CTLE and ATT. Purpose of the feedback path in device is to limit the signal range presented to DFE block. To model this behavior, the following sequence was used: 1. Use gains in Peaking Filter to adjust the peak of all CTLE curves to zero on the Y db axis 2. Adjust AGC value until outer eye height stayed in the correct amplitude range across various system route lengths, with DFE off 3. Plot outer eye height vs length to confirm acceptability 4. If amplitude range is unacceptable, return to step 2. If acceptable, lock down AGC value.

12 DEVELOPMENT: RX ISSUES & SOLUTIONS AGC = off AGC = fixed CTLE Settings Voltage range is 5x wider without use of AGC Plot of Outer Eye Height (mv) vs Channel length (inches) fits within DFE signal input requirement with AGC value fixed (blue). Length range and CTLE variation (green) confirms DFE voltage bounded

13 AGENDA: Building AMI Models Introduction AMI Model Development Lab Measurement & Correlation TX RX Summary Building AMI Models

14 LAB: TX Correlation Setup PCIe Compliant Base Board (CBB) used for testing. Eye diagram measurements on scope using Transmitter PCIe preset P5. Simulated eye diagram includes parasitics from both SSD model and PCIe CBB model.

15 LAB: TX Correlation Result Model correlates measurements within 5%

16 LAB: RX Jitter Tolerance Measurement Test Configuration according to AIC Rx Jiiter Tolerance test (2.8) from PCIe Architecture PHY Test Spec Rev3.0 Target Stressed Eye Height 46mV +0/-5mV. Target Stressed Eye Width /-2ps.

17 LAB: RX Jitter Tolerance Result Simulated knee frequency is similar to measured Loop bandwidth of clock recovery model can be controlled with clock_recovery.step and clock_recovery.count parameters. Eye widths are mapped to BERs using jitter parameters

18 LAB: RX Interference Injection Setup Differential voltage noise injected to data pattern is increased until specified BER. Above process repeated over frequency range to obtain differential noise frequency response.

19 LAB: RX Interference Injection Result Datapath gain variation is inversely proportional to differential noise response. Similar frequency response observed in model CTLE curves. Constraints on test equipment limits the measurement frequency range.

20 LAB: RX Sensitivity Result BER sensitive to signal amplitude and the minimum latch overdrive. Configurable with RX_Receive_Sensitivity parameter in model. Datapath loses must be subtracted to derive correct values of RX Sensitivity.

21 AGENDA: Building AMI Models Introduction AMI Model Development Lab Measurement & Correlation Summary Building AMI Models

22 SUMMARY Building AMI Models from Datasheet Information Process demonstrated, issues raised and solved Measurement and simulation are used to further refine and correlate the model Process can be applied for various simulation tools Currently template syntax is vendor-specific Template models have both limitations and efficiencies Accurate AMI models can be developed, when none exist

23 FOR MORE INFORMATION AMI Expert Panel Discussion: TODAY 3:45 5pm, Ballroom C Accurate AMI Analysis - Whose Responsibility Is It? IBIS-AMI Specs: Intel SSD Design Kits: Authors: eugene.k.lim@intel.com, telian@siguys.com Websites:

24 Thank You! --- QUESTIONS?