DesignCon Applying IBIS-AMI techniques to DDR5 analysis. Todd Westerhoff, SiSoft Doug Burns, SiSoft Eric Brock, SiSoft

Transcription

1 DesignCon 2018 Applying IBIS-AMI techniques to DDR5 analysis Todd Westerhoff, SiSoft Doug Burns, SiSoft Eric Brock, SiSoft

2 This page intentionally blank to support double-sided printing. Yes, we know it s old fashioned but some us still like it! 2

3 Abstract DDR5 memory is slated to run at speeds from 3200 MT/s to 6400 MT/s. These speeds are well into the range where Tx/Rx equalization is used to ensure reliable signal transmission in serial channel applications. DDR5 is expected to make use of the same techniques (FIR, CTLE, DFE) to improve signal quality when the final DDR5 specification is published. While DDR5 signaling speeds have reached traditional SerDes speeds, there are significant differences between DDR and serial channel applications, including: Shorter lower loss channels with more discontinuities and reflections Multiple driver / receiver combinations Multiple signal terminations Single-ended signaling Variable network topologies (DIMMs present or absent) Short transmission bursts followed by network I/O reconfiguration Bi-directional signaling At first, application of SerDes equalization techniques and AMI models seems like an obvious approach to improving DDR5 signal quality. A closer inspection reveals that the design problems incurred by DDR5 topologies are quite different than the signaling challenges that SerDes equalization techniques were originally designed to overcome. However, thoughtful application of AMI models and AMI simulation techniques can highlight which DDR5 signal quality issues are significant and what techniques can best be used to overcome them. This paper looks at the challenges of achieving reliable data transmission for a DDR5 data net operating at a variety of speeds. We discuss how AMI-style analysis can be used to identify which data transfers are the limiting factors in high speed performance and what equalization / modeling techniques can be used to address them. 3

4 Author s Biographies Todd Westerhoff, VP Semiconductor Relations at SiSoft, has over 38 years of experience in electronic system modeling and simulation, including 20 years of signal integrity experience. He is responsible for SiSoft's activities working with semiconductor vendors to develop high-quality simulation models. Todd has been heavily involved with the IBIS-AMI modeling specification since its inception. He has held senior technical and management positions for Cisco and Cadence and worked as an independent signal integrity consultant. Todd holds a BEEE degree from the Stevens Institute of Technology in Hoboken, New Jersey. Douglas Burns, VP of Support and Consulting Services, manages SiSoft's consulting and support services group. In this role, Doug actively interfaces with customers from both the technical and sales perspective and defines the customized solutions needed to address customer issues. As a member of SiSoft s leadership team, he also plays a significant role in the definition and direction of SiSoft s software products. Doug has over 30 years of experience leading teams engaged in a broad range of technical disciplines. Doug holds seven patents in computer system design and his expertise spans a wide range of engineering disciplines including: System Architecture, VLSI design, Package Design, Timing Analysis (chip and system level), Signal Integrity, Power Integrity, and Project Management. Doug graduated Magna cum Laude from the University of Massachusetts with a BSEE degree and received his MSEE degree from Northeastern University. Eric Brock, SiSoft Principal Member of Technical Staff, received his BS in Electrical Engineering and a BS in Physics from Portland State University in After graduating, Eric worked at Digital Equipment Corporation and Compaq as a Signal Integrity Engineer in the Alpha Development Group. Eric joined SiSoft in 2002 and has worked as a consultant on the design and verification of hundreds of high-speed parallel and serial interfaces, both proprietary and industry standard. More recently, he has been involved in the design of multi-ghz serial links and SERDES modeling. 4

5 Introduction DDR memory interfaces have evolved to the point where they are operating well beyond the speeds where transmit and receive equalization was first used to improve signal quality in high speed serial links. DDR5, the next generation of memory technology, is expected to start at 3200 MT/s and reach 6400 MT/s over its lifetime. Transmit and receive equalization appeared toward the end of the DDR4 cycle and is expected to be a standard part of DDR5, although the exact details have not been finalized. The Evolution of DDR SI Analysis DDR analysis was originally based on what many of us think of as legacy SI analysis methods. Topologies and terminations were tuned through simulations to maximize signal quality. A data net was then simulated for each combination of driver and receiver, noting the delay to input s switching threshold. Signal flight times were derived by normalizing the observed delay against the driver s output switching behavior into a standard loading condition. The resulting flight times were then used with timing equations to compute the setup and hold margins for the associated read and write transactions. Over time DDR set the standard for source synchronous signaling, where the sampling clock (strobe) used by the receiver was synchronously driven by the data s source, traveling in the same direction as the data. The sampling clock was a distinct signal and not embedded within the data itself. As DDR memories have evolved, the mechanisms that controllers use to ensure optimize read/write operations have become quite sophisticated. Modern controllers ensure correct timing of clock / data / strobe / control signals by adjusting signal skew at the controller. As a result, DDR signal integrity is increasingly focused on optimizing the eye at the receiver by defining independent termination settings for each read/write transaction and assuming that the controller will configure device timing and sensing thresholds accordingly. This shift to eye opening analysis as opposed to combined signal integrity and timing analysis has been accompanied by the realization that the vanishingly small timing margins associated with high device speeds cannot be met 100% of the time. As a result, advanced simulation techniques are used that allow the user to predict how large the receiver eye is at a given probability level for instance, whether a reference mask impinges on the eye opening with a probability level below 1e-12. This allows users to predict a bit error rate (BER) for DDR simulation, using similar techniques to those used for serial channel analysis since the advent of IBIS-AMI modeling in Please note that predicting the probability of a bit error is independent of whether the interface can tolerate the presence of that error. The simulation techniques we present focus on the probability that a bit will be detected incorrectly, but not what the consequences of that error will be (i.e. whether the system will crash or detect the error and recover). 5

6 IBIS-AMI Models The IBIS Algorithmic Modeling Interface (IBIS-AMI) modeling specification [1] was originally introduced to support end to end analysis of high speed serial links with both transmitter (Tx) and receiver (Rx) equalization. It is a combination of modeling and simulation methodologies that are based on a specific set of assumptions: Analog I/O (receiver termination / driver output) circuitry operates in its linear region Device pin circuitry can be separated into analog and algorithmic components Tx/Rx EQ algorithms can be described using executable code linked into a simulator at runtime IBIS-AMI models support two different types of simulation: Statistical simulation, which generates an eye diagram directly through superposition. This method creates an eye diagram that represents the effects of an extremely long (2**128 bits or greater), random non-repeating bit pattern. It is important to note that the actual bit pattern does not exist; the eye is computed directly from an equalized impulse response returned by the AMI models. This technique is further discussed in [2]. Time-Domain (also called bit by bit) simulation, which simulates the network s response to a specific bit pattern. Because IBIS-AMI simulation separates circuit simulation from equalization processing, effective simulation speeds are much greater, making simulations of 1M bits or more practical. Advantages of IBIS-AMI models and techniques for DDR simulations include: Ability to predict operating margins to very low (1e-15) probability levels Ability to run large numbers of cases quickly. A Statistical AMI simulation takes 1-2 seconds and represents > 1e15 bits while SPICE simulation takes 1-5 minutes and represents < 100 bits. Ability to quickly analyze trade-offs in topologies, termination, equalization, etc. Since DDR applications are now featuring equalization capabilities in their transmitters and receivers, it seems logical to apply IBIS-AMI models to DDR5 interfaces. It s worth noting that IBIS-AMI models were originally designed for analyzing differential serial channels, which have notably different characteristics from DDR topologies: Interconnect length o Serial channels typically have Nyquist of -20dB or more. DRAM channels are typically a few inches long and low-loss by typical SerDes standards perhaps as little as -3dB. Topology branches (stubs) and ringing o Serial channels have no or very minimal stubs. A DRAM topology with multiple DIMMs will have long branches associated with the DIMMs in the middle of the topology. Energy in these branches will reflect, greatly contributing to ringing in the system. Multiple driver/receiver combinations o Each DDR data net supports different read/write transactions between the controller and DRAM(s). Optimizing interconnect for one transaction may come at the expense of another. 6

7 Variable topologies (populations) o Serial channels do not change their topology. DDR topologies include DIMM sockets that may or may be populated, and DIMM characteristics can vary. Tunable driver/receiver impedance o DDR I/O have tunable output and input impedances. The permutations of drive and receive termination settings easily reach into the thousands. Serial channel transmitter / receivers may have tunable impedance, but choices are usually limited. Continuous operation vs. bursts o Serial channels never stop, DDR topologies communicate in bursts. Unidirectional vs. Bidirectional o Serial channel device pins are unidirectional (they either transmit or receive), while DDR device pins are bi-directional to support both Read and Write operations. These differences notwithstanding, applying AMI models and simulation techniques to DDR topologies provides useful insight into what DDR operating margins will be and why. Example DDR5 Data Net Figure 1 shows the topology of a hypothetical data net. A DDR controller is connected to 2 DIMM slots, each of which have two DRAM loads (a dual slot, dual rank system). For simplicity s sake, we ve fixed the trace lengths and the value of the DIMM series resistors. We will study the different driver/receiver combinations, their associated drive impedance / receive termination settings and determine how Tx/Rx equalization can help improve the design s operating margin. Figure 1. Hypothetical DDR5 DQ topology 7

8 Optimizing Driver and Termination Settings There are 8 possible driver / receiver combinations, or transactions, for this topology. The lower DIMM slot is slot 1, and when only one DIMM is populated, it is plugged in here. The upper DIMM slot in the diagram is DIMM slot 2. Our analysis assumes 2 populated slots and because the routed lengths to the DRAMs in each DIMM are identical, we can reduce the number of simulation cases we need to consider down to 4: Controller to DIMM1 (whether DRAM1 or DRAM2) Controller to DIMM2 (whether DRAM1 or DRAM2) DIMM1 to Controller (whether DRAM1 or DRAM2) DIMM2 to Controller (whether DRAM1 or DRAM2) For simplicity s sake, we ll assume that the Controller and the DRAMs have the same Tx/Rx equalization capabilities, although that will typically not be the case. Controllers tend to have more sophisticated equalization /de-skewing capabilities and are expected to determine the EQ settings for DRAM memories with DDR5. In this study, we assume all the I/O s have the same capabilities so we can focus on an analytical methodology. First, we need to focus on the output driver / input on-die termination (ODT) capabilities of our I/O, and determine the best combination of settings for each of our 4 transactions. When a device is driving a signal onto the net, it has three different output impedance settings: DQ_ZO34 Generic DDR5 34 Ohm Driver DQ_ZO40 Generic DDR5 40 Ohm Driver DQ_ZO48 Generic DDR5 48 Ohm Driver When a device is acting as the target receiver for a transaction or is simply acting as a terminator on the net, it has 8 possible settings to choose from: DQ_IN_ODTOFF Generic DDR5 Receiver with No ODT DQ_IN_ODT34 Generic DDR5 Receiver with 34 ohm ODT DQ_IN_ODT40 Generic DDR5 Receiver with 40 ohm ODT DQ_IN_ODT48 Generic DDR5 Receiver with 48 ohm ODT DQ_IN_ODT60 Generic DDR5 Receiver with 60 ohm ODT DQ_IN_ODT80 Generic DDR5 Receiver with 80 ohm ODT DQ_IN_ODT120 Generic DDR5 Receiver with 120 ohm ODT DQ_IN_ODT240 Generic DDR5 Receiver with 240 ohm ODT Our DQ net will have a single driver, a single target receiver and three devices requiring termination for each transaction. The number of possible settings is therefore: (Driver Settings) * (Receiver Settings) * (Terminator Settings)**3 = 3 * 8 * 8**3 = 12,288 combinations 8

9 With 4 transactions to study, that gives us 49,152 simulations just to pick driver and receiver / termination settings! Fortunately, we can make some simplifying assumptions to reduce the size of our study: DRAMs on the DIMM not driving or receiving will use identical impedance settings. The inactive DRAM on the target DIMM will be so close to the target DRAM (< 2 mm) that we don t want that termination to do much and can configure it to a higher impedance setting. We won t turn off the termination completely at the target receiver. Figure 2. Driver / receiver / termination settings exploration The collection of settings we explore for each transaction is shown in Figure 2. Instead of 12,288 combinations for each transaction, we explore: (3 driver) * (7 target DIMM / receiver) * (3 target DIMM / terminator) * (4 non-target DIMM / terminator) settings = 252 settings. which is a reasonable compromise between studying the complete design space and limiting simulation run times. Our simulation environment lets us define the settings to be explored, automatically generates the simulation cases, runs simulations, then presents the resulting simulation measurements and waveforms. In this part of the study, we measure timing and voltage margin against a reference eye mask as shown in figure 3. Figure 3. Eye mask at receiver input pad Having the ability to run a large set of simulation cases and measure the resulting margins gives rise to the question which case is best? It s obvious that we re not going to compare 252 cases visually, so we 9

10 need to pick a metric that we can use to evaluate the cases relative to one another. If we choose voltage margin against our mask as our metric and plot all 252 Controller to DIMM1 transactions, we get: Figure 4. Voltage margin against mask This scatterplot in Figure 4 shows voltage margin (Y axis) against the simulation case (X axis). Driver impedance is the most significant variable, causing 3 distinct sets of distributions based on the driver s output impedance of 34, 40 and 48 ohms. In this study, a lower output impedance and more power increases margin. While we also need to ensure adequate eye width (timing margin), close inspection of our results showed that eye width wasn t a problem no matter which settings we chose, making eye height margin the relevant metric to examine. If we pick the data point with the largest voltage margins and examine the case to see the associated simulation setup, we get: Figure 5. Optimized driver/receiver/termination settings This is interesting; the termination on the receiving DIMM (DIMM1) is essentially disabled with the target receiver (DRAM1) set to 240 ohms and the other terminator turned off completely. Each of the terminators on the non-target DIMM are set to 60 ohms, basically terminating any signal that reaches them. Looking at the eye at the target receiver s pad, we see significant margin: 10

11 Figure 6. Optimized eye with mask We can repeat this process for each of our 4 transactions to optimize driver/receiver/termination settings, at which point our voltage and timing margins look something like this: Figure 7. Optimized timing/voltage margins for each transaction It s clear that DIMM2, the DIMM in the middle of our topology, is going to be our limiting factor as we try to make this net run faster, with write transactions being somewhat more difficult than read transactions. With that in mind, let s focus on the Controller to DIMM2 write transaction and see what happens to those margins as we run the net at higher speeds. For our next set of experiments, we run the Controller to DIMM2 transaction at speeds from 3200 MT/s to 6400 MT/s in increments of 400 MT/s. Running that speed sweep and plotting the resulting voltage margin against our reference mask gives us: Figure 8. Controller to DIMM2, voltage margin vs. data rate 11

12 The black reference line indicates a 0V margin, or the point where the eye opening just touches the reference mask. The reference mask in this case is +/- 55mV around the eye s center point, so a voltage margin of -55mV represents a completely closed eye. Note that the reference mask size will normally reduce with increasing data rate; we re omitting that to keep things simple. There are some interesting trends here worth noting. The first data point represents 3200 MT/s, the second 3600 MT/s, the third 4000 MT/s, and so on. Why is the difference in margin between the first and second data points (3200 MT/s and 3600 MT/s) so large, and how can it be that the fourth data point (4400 MT/s) has more margin than the second (3600 MT/s)? Pulse Response Analysis One good way to investigate this is to use pulse response analysis, which simulates and plots the network s response to a 1 Unit Interval (UI) pulse. In an ideal system, all of the pulse s energy at the receiver will be contained within two UI s that include the pulse s rising and falling edges. The signal will transition from its steady state level to its maximum amplitude and back down to the steady state level within that period. In an actual system, high frequency loss widens the pulse response and impedance discontinuities create reflections that cause energy to bounce back and forth long after those 2 UI have passed. So how does this look for our 3200 MT/s and 3600 MT/s cases? It looks like this: Figure 9. Pulse responses vs. time, 3200 MTs and 3600 MT/s This plot shows both waveforms as a function of time (how most of us would plot this if asked). The network is the same, but the stimulus rate is slightly different, so the two pulse responses are slightly offset. As it turns out, this method of looking at the relative data isn t particularly insightful. 12

13 If we change the X axis to unit intervals, effectively scaling each waveform based on its respective data rate, the differences start to become clearer: Figure 10. Pulse responses vs. UI, 3200 MTs and 3600 MT/s The differences between waveforms are now more clearly pronounced, but what do they mean and how do they affect the design s operating margin? What s critical is understanding where the waveforms will be sampled by the input clock, because that s the only time the input voltage really matters. At the point where we sample any given bit, ISI from previous bits superimposes energy on the bit being sampled. If we can define the point where the pulse response will be sampled, we can predict the ideal eye height in the absence of ISI and also predict how ISI from previous bits will affect the eye height we see in practice. In our analysis, we use a method known as the hula hoop algorithm [3] to predict the point in time where we expect the pulse response will be sampled. We then shift the pulse response so the sampling point occurs at time 0, and shift voltages so the pulse response starts at 0 volts. This allows the pulse voltage at the sampling time and ISI voltages to be read directly off the plot. We refer to this as aligning the pulse waveform. 13

14 If we plot the aligned pulses for the 3200 MT/s and 3600 MT/s cases, we get: Figure 11. Aligned pulse responses, 3200 MTs and 3600 MT/s and now the picture comes into focus. The voltage at time 0 for each waveform represents the eye height in the absence of ISI, and the voltages at all other UI intervals are ISI voltages. Assuming a random data pattern, the eye opening will be the voltage at time zero minus the sum of the absolute values of the ISI voltages. Comparing 3200 MT/s (blue) to 3600 MT/s (red), we see that the 3200 MT/s waveform has slightly more voltage at the sampling time, but its real advantage is that its ISI voltages are much less. At +2, +3, +4 and +5 UI (green markers for clarity), the 3600 MT/s waveform peaks at exactly the wrong instant, maximizing ISI, while the 3200 MT/s waveform fares much better. Thus, the reflections on this net make 3600 MT/s a poor choice of operating speed. Let s continue this analysis by comparing 3600 MT/s (red) to 4400 MT/s (cyan). Our margin plot in Figure 8 showed that the faster speed would somehow work better for this network. Let s look at the aligned pulse responses for those two speeds: Figure 12. Aligned pulse responses, 3600 MTs and 4400 MT/s 14

15 Here again, the aligned pulse responses make it clear at 3600 MT/s, the reflections fall in exactly the wrong places, while at 4400 MT/s they do not. Thus it isn t the faster speed that causes the problem with this topology, it s the location and timing of the reflections. If we look at eye diagrams against the mask (a more typical way of doing this), we see the same story: Figure 13. Eye diagram with mask, 3600 MT/s Figure 14. Eye diagram with mask, 4400 MT/s Each of these eyes are plotted with the X-axis in UI to make them easier to compare. It s clear that the eye at 4400 MT/s is more balanced and there s something odd about the eye at 3600 MT/s. The important point here is that the aligned pulse responses made it easier to use to understand what was going on and what to do about it. 15

16 Using Driver / Receiver Equalization But how can we improve signal margins further once we ve optimized the driver/receiver/termination settings? DDR5 is promising driver / receiver equalization, but what kind of equalization do we need and how do we configure it? We began seeing driver equalization (Finite Impulse Response or FIR filters) and receiver Continuous Time Linear Equalizers in some controllers during the DDR4 era. Tx FIR filters and Rx CTLE filters are familiar devices and have been used in differential serial links for years. The challenge with these filters is they are primarily designed to deal with large levels of loss at the network s Nyquist frequency. This type of loss is characterized by a long, regular tail in the network s pulse response, resulting in many bits worth of significant ISI. By managing the pulse response tail (usually at the expense of pulse height), these filters improve signal margin. The challenge with DDR technologies is that the primary problem isn t loss it s reflections and ringing. Serial channels are long, DDR topologies are short. Serial channels have a single driver and receiver with well controlled impedances, DDR topologies have multiple driver/receivers, poorer noise control due to single-ended signaling and are full of branches. The equalization technology best suited to DDR topologies is probably the Decision Feedback Equalizer (DFE), which will reduce reflections based on a specific ISI pattern [3]. Tx FIR filter and Rx CTLE filters provide an equalization characteristic that spans many bit times but is essentially independent of the topologies being equalized it s up to the user to select the proper setting based on the topology. Traditional DFEs, on the other hand, adapt to the characteristics of the network being equalized, but only provide ISI abatement for as many bits as the DFE has taps. The power of the DFE is that the equalization can vary from bit to bit based on the circuit topology, rather than the fixed equalization curves exhibited by Tx FIR and Rx CTLE filters. In the case of DDR5, the details of DFE equalization and how it will work have not been finalized. It is highly unlikely that DRAM DFEs will adapt their behavior during actual operation, as adaptation circuits use considerable power and silicon area. It s more likely that DRAM DFEs will have their tap coefficients determined during a training sequence performed in conjunction with the controller, and then have those coefficients fixed during actual operation. From a simulation standpoint, we can effectively emulate this behavior by setting up our DFE model so the taps lock and stop adapting once they settle. 16

17 Let s take a closer look at our problematic 3600 MT/s aligned pulse response: Figure 15. Aligned pulse response at 3600 MT/s with ISI voltages In Figure 15 we show the pulse voltage at the sampling time and the first 7 ISI voltages. The theoretical maximum eye height is 513mV, but the first seven ISI cursors add up to 393 mv, leaving us with only 120mV of predicted eye height. What would happen if we used a DFE to correct for the ringing in this network, and how many DFE taps would we need? What would be the best tradeoff between DFE taps and eye height? We can perform a first order analysis with the data we read off the plot in Figure 15. We know that our uncorrected eye height will be approximately 120mV. For as many taps as we have in our DFE, we can add those ISI voltages back into the eye height, making the broad assumption that the DFE can completely correct the ISI for each tap bit. Those calculations look like this: 600 DFE Taps vs. Eye Height Eye Height mv DFE Taps mv % Improvement ISI % ISI % ISI % ISI % ISI % ISI % ISI % Figure 16. Theoretical eye height vs. DFE taps 17

18 With no DFE, we have an eye height of 120mV. With a 1 tap DFE, we get 154mV back and our eye height becomes 274mV, and so on. There is still some ISI after 7 bit times with this network, but we neglect it in this first order analysis because it s small. We don t need a large number of DFE taps to make a big difference here it looks like one or two would be enough. To see how this works in practice, we augment our DDR models by adding programmable Tx/Rx equalization through IBIS-AMI. To keep the analysis simple, the only equalization we ll use is the Rx DFE, which we will allow to adapt and lock as discussed earlier. Figure 17. DDR topology with IBIS-AMI models This schematic is extended from the one we started with; now the A block in I/O models indicates that an IBIS-AMI model has been added and equalization settings can be configured by the user. With the addition of Rx equalization, the receiver test point for our network also shifts. With a legacy DDR I/O model, the test point for the eye opening is usually at the device s die pad. When we add equalization with IBIS-AMI models, the test point shifts to the output of the equalization circuit, usually referred to as the sampling latch. This is a different point in the network, and its input requirements (i.e. its eye mask) will almost certainly be different than the eye mask requirements at the device pin or die pad. In our analysis for this paper, we ve used a rectangular eye mask for the die pad and a diamond shaped mask at the output of the IBIS-AMI model to make the two measurement points easier to discern. The actual eye masks will vary based on individual devices and speeds; we ve used simple masks in this paper to make the analytical methodology easier to follow. 18

19 So what happens when we use 2 DFE taps at 3600 MT/s? If we plot the eye at the die pad (before equalization) against its respective mask, we get: Figure MT/s at Die Pad Using only DFE equalization with 2 taps and observing the input to the sampling latch we get: Figure MT/s at Sampling Latch which is clearly a big improvement. Note the diamond-shaped eye mask noting that we are sampling at the output of the equalization circuitry. 19

20 How did our eye height predictions fare? Well, not quite as well as we might have hoped: Figure 20. Simulated eye heights at sampling latch For no DFE equalization, we estimated 120mV and the simulator reported 111mV, which indicates there was still ISI beyond the points in the pulse response we measured. For two taps, we estimated 374mV and got 301mV from simulation. For 4 taps, we estimated 459mV and got 343mV from simulation, and for 8 taps we estimated 513mV and got 355 mv from simulation. This tells us that the DFE model in our simulation isn t cancelling out the ISI as completely as we hoped. We understand that our hand calculations were only a first order estimate, but this is still more than expected. That s a great point for investigation but beyond the scope of this paper. Finally, let s repeat the speed study we did earlier but with the addition of varying numbers of DFE taps to see how they affect design margin. In Figure 21 we plot the voltage margin against the diamond shaped eye mask at the sampling latch. Data rate was swept from 3200 MT/s to 6400 MT/s in increments of 400 MT/s. The data points show the design margin using no DFE (red), 2 DFE taps (blue), 4 DFE taps (green) and 8 DFE taps (yellow). Generally, we see the same trend we noted for the 3600 MT/s case; 2 taps give significant benefit with diminishing returns after that. There are some interesting cases here worth exploring but also beyond the scope of this paper - for instance, the 4000 MT/s case (Row 3) shows that 2 taps and 4 taps give virtually the same result and suggests that the result with 4 taps is somewhat worse than the result with 2 taps. This is unexpected and points to something about our DFE model that is probably worth understanding. Analyses similar to that shown in Figure 21 reveal how design margin changes with data rate, and provide the tools to apply enough but not too much equalization for the design task at hand. Figure 21. Operating margin vs. speed vs. DFE taps 20

21 Applying AMI Models to DDR5 Analyses In the remaining sections we begin the discussion of problems that arise when applying AMI models in a DDR5 context. The discussion is meant to raise the issues and various solutions, while not providing conclusive answers. This is done to acquaint the reader with challenges currently being explored to extend IBIS-AMI for DDR5 and provide solutions that can be implemented in practice. Modeling DDR5 DFE Training With SerDes channels, the Rx DFE typically trains itself during operation, but with DDR5 memories, the Rx DFE is expected to operate with fixed tap values. The memory s DFE tap values will be determined during a training procedure at system power up, where the controller evaluates different EQ settings to determine the best settings for a particular interface. The details of the training protocol will be specific to individual controller (not part of the DDR5 spec), and as this paper is written, the manner in which DDR5 memory indicates the merits of a given setting have not been resolved. Thus, with so much of the process undefined, what are we supposed to do from a simulation standpoint? Do we (a) attempt to faithfully model all the interactions between the controller and memory during the training procedure, (b) simply fix the DFE tap settings ourselves, or (c) something else? For our study, we chose option (c). Our goal was to model the effect of the DFE training procedure without having to model the details of the exact method. This proved to be fairly simple we allowed the Rx DFE AMI model to adapt like any other DFE, giving the taps enough time to settle, then locked the DFE taps settings for simulation processing. We set the DFE s lock time at the point where the Rx s Ignore Bits setting expired, so all of the data collected by the AMI simulator corresponded to fixed-tap operation. This gave us the benefit of having optimized tap settings for each simulation case without having to run a blind sweep analysis to figure out what the best DFE tap settings were. But how do we modify an AMI model so that the DFE taps lock at the right instant in time? For this study, we used an environment that allowed us to compile AMI models from MATLAB source code. We used a DFE model that was originally designed for SerDes channel simulation and adapted it for our DDR5 study. To incorporate our DFE lock feature, we defined a new AMI input parameter that told the model when to stop adapting. Once that new parameter is defined, locking the DFE taps takes one line of new code: if (dfe_lock > bits_processed) To test the effect of the dfe_lock, we compiled the AMI model and ran two sets of stimulations in our AMI simulator. In the first simulation, we let the DFE taps adapt continually, and in the second simulation we locked the DFE taps halfway through the simulation. In both simulations, we set Ignore_Bits to correspond to the halfway point in the simulation, so each eye diagram only represents the second half of the run. 21

22 When we let the DFE taps adapt for the whole run, we get: Figure 22. DFE tap lock disabled We can see that the DFE taps have largely stopped adapting by the halfway point they re clearly drifting, but the pattern repeats. The tap drift is due to periodicity in the input pattern a intriguing effect that we don t have time to get into here. When we lock the DFE taps at the halfway point, we get: Figure 23. DFE tap lock enabled at halfway point 22

23 But how much difference does locking the DFE taps make in the results? If we plot the two eyes with the same scale, we get: Figure 24. Eye diagram comparison with DFE tap lock which is not much difference at all. Plotting the inner eye contours for these two cases, we get: Figure 24. Eye contour comparison with DFE tap lock What does this tell us? It tells us that our tap locking algorithm is working as expected, and suggests (at least for this case) that we had a reasonable approximation of operating margin even before we implemented the tap lock. 23

24 Modeling Clock-Forwarded Architectures with AMI Most AMI Rx models include a clock-recovery loop and return clock tick data to the AMI simulator indicating when the Rx output waveform should be sampled. DDR5 is a clock-forwarded architecture, where the sampling clock is not recovered from the data stream. We mentioned that we started with an AMI model originally developed for SerDes use how should we adapt the model to represent a clockforwarded architecture? One simple way is to use the same approach we used for the DFE lock adaptation at the point where Ignore_Bits expires. This approach allows the CDR to adapt based on the delay of the interconnect - so the output eye is properly centered, but disables CDR tracking for the recorded portion of the simulation. We extended our AMI model as before, this time adding a cdr_lock parameter that enabled us to test the effects of locking the DFE and CDR independently. In the figure below, DFE taps are locked at the halfway point in both cases. The only variable is whether the CDR is allowed to adapt over the whole run or locked at the halfway point: Figure 25. Eye diagram comparison with CDR lock If you look closely, you ll see that the bottom eye the one with the CDR locked as Ignore_Bits expires, appears to be wider than the eye where the CDR continues to adapt. That s indeed the case, and if we plot the two eye contours we see the figure on the following page: 24

25 Figure 26. Eye contour comparison with CDR lock This is counter-intuitive: why would the eye where the CDR is locked be wider than the eye where the CDR is active? The answer turns out to be that the CDR is interacting with the repeating data pattern. Our CDR is a first-order (Bang-Bang) model, and the clock phase dithers in response to the data pattern. When we allow the CDR to continue to adapt, that behavior closes the eye (as seen by the sampling clock) by about 0.06UI. When we lock the CDR, the drifting stops and the eye (as seen by the sampling clock) gets slightly larger. Power Noise, Nonlinear Behavior and Tx/Rx Jitter The IBIS-AMI specification explicitly makes the assumption that the Tx driver and Rx terminator circuits operate in a linear fashion. This is a fixed part of the IBIS-AMI specification and all models and analytical methods that follow from it. This assumption allows us to characterize the analog channel (Tx driver + interconnect + Rx termination) using an impulse response and then combine that impulse response with algorithmic model processing to predict end to end link behavior. This assumption of linearity may be reasonable for serial channels and differential I/O, but we re clearly pushing the limits with DDR5 and single-ended signaling. At the time this paper is being written, AMI modeling for single-ended I/O is still in its infancy, and how well IBIS-AMI can be adapted to model traditional single-ended effects like Simultaneously Switching Outputs (SSO) is unknown. How should we deal with the eye width (timing) and eye height (voltage) collapse of the received eye associated with SSO? There are several different methods currently being explored: 1. Use power-aware IBIS models to create the analog channel impulse response and perform algorithmic model processing in the usual way 2. Use power-aware IBIS models to characterize eye height/width collapse associated with I/O power rails and then: a. Increase the height/width of the eye mask used to assess simulation results b. Adjust the receiver latch voltage thresholds used to assess simulation results c. Introduce Tx/Rx jitter and noise into the simulation setup d. A mixture of 2a, 2b and 2c 25

26 In our study, we chose to investigate method 2c, using existing IBIS-AMI facilities for injecting noise and jitter into simulations. With this scheme, the interface is simulated in a legacy (non-ami) fashion, with and without power modeling, to derive budgetary factors for voltage noise and jitter. We will skip the discussion of how those numbers are derived here and focus on how eye collapse can be modeled as jitter. IBIS-AMI specifically models Tx jitter (Random, Deterministic, DCD and Sinusoidal) as directly modulating Tx output switching behavior. Rx jitter, by contrast, modulates the recovered clock, while Rx noise modulates the signal at the data input to the sampling latch. To test this approach, we ran 3 different simulation cases: 1. A reference simulation (no jitter on either the Tx or Rx) 2. A simulation with Tx Determinstic Jitter (Tx_Dj, uniformly distributed bounded jitter) 3. A simulation with Rx Determinstic Jitter (Rx_Dj, uniformly distributed bounded jitter) We chose Dj because it is bounded jitter, using a large value (0.2 UI peak-peak) so effects on the eye opening will be readily discernable. If we plot the 3 resulting eyes together: Figure 27. Effects of Tx and Rx jitter on eye diagrams We see that the effects of Tx and Rx jitter are different, so examining the eye contours will allow us to see those details more closely. 26

27 Plotting the eye contours (red = no jitter, blue = Tx_Dj, green = Rx_Dj) for these cases: Figure 28. Effects of Tx and Rx jitter on eye contours Here again, the results are both intriguing and complex. Remember that Tx jitter modulates the signal driving the channel, while Rx jitter modulates the sampling clock. Digging into the details of why Tx/Rx jitter affects the results the way it does is beyond this paper s scope. What methodology is best for modeling power compression and associated nonlinear behavior in DDR5 interfaces? At this instant, AMI modeling for single-ended signals is just getting underway and although these are real phenomena, there s not a lot of agreement within the industry on how to model and simulate these effects. DDR5 is obviously a huge design-in market, with lots of players and applications, and there s no shortage of opinion on which phenomena matter, which don t, and what modeling methods are appropriate. The good news here is that IBIS-AMI gives us an established modeling and simulation base to build on, such that we can explore different ways to create models and consider how to extend IBIS-AMI for DDR5 applications. It feels somewhat unsatisfying to say we will have to wait and see (especially after 27 pages!) but that s exactly where we are at this point in time. The good news is that we have the right tools in hand to experiment and determine the best path forward. 27

28 Summary In this paper, we have reviewed a process for analyzing and optimizing signal integrity on DDR5 data nets. We started by exploring the different driver / receiver transactions and optimizing driver / receiver / termination settings. We outlined the use of pulse response analysis to provide additional insight into the unique challenges of a particular DDR topology and what to do about them. We also introduced the concept of driver / receiver equalization and used IBIS-AMI models to explore how specific equalization techniques could be used to increase the design s operating margin. Finally, we looked at some specific DDR5 features and phenomena to see how they might be handled within the current feature set for IBIS-AMI models. The process presented here is NOT a complete methodology for analyzing DDR5 interfaces. Topics for further investigation include: Performing signal integrity and timing for address / command / clock nets Optimizing DQS signaling Validating DQS to DQ timing Rolling up signal integrity and timing for nibbles/bytes Balancing Driver and Receiver equalization settings AMI modeling for DDR5 analysis is still new and evolving. We have attempted to highlight some of the critical issues that need to be addressed / standardized and some methods that might be used to address them. Along the way, we ran across few items worthy of continued investigation and (hopefully) another paper or two. 28

29 References [1] IBIS 6.1 specification, IBIS website, [2] Sanders, Statistical signal analysis (SSA) demystified, EETimes online, [3] Telian, Steinberger, Katz, New SI Techniques for Large System Performance Tuning, DesignCon