Two for One: SerDes Flows for AMI Model Development
|
|
- Deborah Flynn
- 5 years ago
- Views:
Transcription
1 Two for One: SerDes Flows for AMI Model Development Corey Mathis, Ren Sang Nah (MathWorks) Richard Allred, Todd Westerhoff (SiSoft) DesignCon 2016 IBIS Summit Santa Clara, California January 22, 2016 * Adapted from the DesignCon 2016 paper Leveraging SerDes Flows for AMI Model Development Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 1
2 Background Good AMI models are hard to develop Analog / algorithmic partitioning IBIS-AMI requirements: samples per bit Portability issues between EDA tools AMI development typically occurs after the fact AMI Models are customer collateral Created by different group Limited testing before distribution Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 2
3 Architectural models SerDes Design Created up-front to define architecture & budgets Limited design detail, execute relatively fast Good for design budgets & control loop behavior Implementation models Detail varies from architectural to gate to circuit level A snapshot of the design at a point in time This presentation is based on Architectural models Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 3
4 An AMI Model Primer Fundamental Assumption Model Components Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 4
5 AMI_Init Model configuration parameters Impulse response processing Linear, Time-Invariant (LTI) AMI Simulation Primer AMI_Getwave Waveform processing Clock ticks Non-Linear, Time-Varying (NLTV) AMI_Close Clean up & exit Algorithmic Model Network Characterization (Circuit Simulation) Channel Simulation (Signal Processing) Channel Simulation For more info: Understanding IBIS-AMI Simulations, DesignCon 2015 Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 5
6 SerDes Architectural Exploration Typical flow: end to end link in Architectural simulator Our flow: leverage strengths of Architectural and AMI simulators Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 6
7 IBIS-AMI Model Development Loop AMI Simulator Test case generation Batch & regression tests Architectural Simulator Interactive design & analysis Test case debugging Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 7
8 Leveraging Existing Infrastructure Build on existing capabilities for embedded software code generation Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 8
9 Mixing Structure and Code Key parts of SerDes designs are often implemented as code Ability to mix structure and code is critical Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 9
10 Creating Algorithmic Models Identify model type Identify AMI parameters Generate Code & Compile Based on design characteristics (Init/LTI or Getwave/NLTV) C++ code.ami file Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 10
11 TX: 4 tap filter IBIS-AMI Model Types Simple, linear, non-adaptive Init or LTI model Complex, non-linear, adaptive Getwave or NLTV model RX: CTLE, Saturation, 8 tap DFE, CDR Design characteristics drive proper IBIS-AMI model type Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 11
12 A Simple AMI Transmitter 4 tap TX with normalization captured two ways Structural model MATLAB code Channel behavior with & without equalization Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 12
13 Generated C++ Code AMI wrapper Model behavior Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 13
14 Architectural vs. AMI Results Architectural simulation ends, AMI simulation run for more bits Test bench Output waveform comparison Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 14
15 USB 3.0 Receiver Model Low power mobile receiver with multi-protocol support Design challenge: balance AGC, linear/non-linear EQ and CDR USB3.0 On-the-Go (OTG) support especially challenging Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 15
16 Model Correlation Simulator to Simulator Architectural Model AMI Model Simulator to Hardware Receiver hardware reports eye height and width based on sampling clock Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 16
17 Other Findings Internal models External (customer) models Expose extra controls and outputs Internal testing & design tuning Internal regression testing Fewer exposed controls & outputs Early models for key customer feedback Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 17
18 Throughput Other Findings AMI Compliance AMI models run 4-8x faster than their Architectural counterparts Running AMI simulations in parallel can provide ~150x speedup for regression testing AMI requires models run at any setting of samples per bit Architectural models can be set up to meet this requirement Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 18
19 AMI Parameters AMI RX Model Saturation Block Code, Continuous Time, Time-Domain CDR/DFE Code, Sampled Time, Time-Domain Peaking Filter Structural, Continuous Time, Frequency-Domain Clock Ticks output Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 19
20 AMI RX - Architectural Simulation Pad Data Clock Position Latch CDR Inc./Dec. Early / Late Count DFE Taps Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 20
21 AMI RX Compiled Model Eye Diagram Output Clock Output Control Inputs Performance Test Simulation Time Reference Time Relative Speed Statistical 1 sec 1 sec 1.000x TimeDomain_008spb 1.46 min/mbit 1.30 min/mbit 0.889x TimeDomain_016spb 1.87 min/mbit 1.46 min/mbit 0.783x TimeDomain_032spb 3.33 min/mbit 2.60 min/mbit 0.781x TimeDomain_064spb 7.97 min/mbit 6.02 min/mbit 0.755x TimeDomain_128spb min/mbit min/mbit 0.814x Simulation Speed Compliance - Samples/Bit Compliance - Block Size Comparable to hand-written models Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 21
22 Summary AMI models can be created from Architectural models normally created during the SerDes design cycle The parameters exposed in an AMI model can be varied depending on the application Models produced with this process behave just like any other well-constructed AMI model Two for One: SerDes Flows for AMI Model Development DesignCon 2016 IBIS Summit 22
Two for One: Leveraging SerDes Flows for AMI Model Development
TITLE Two for One: Leveraging SerDes Flows for AMI Model Development Todd Westerhoff, SiSoft Corey Mathis, MathWorks Image Authors: Corey Mathis, Ren Sang Nah (MathWorks) Richard Allred, Todd Westerhoff
More informationIBIS-AMI Terminology Overview
IBIS-AMI Terminology Overview Walter Katz, SiSoft wkatz@sisoft.com Mike Steinberger, SiSoft msteinb@sisoft.com Todd Westerhoff, SiSoft twesterh@sisoft.com DAC 2009 IBIS Summit San Francisco, CA July 28,
More informationComparison of Time Domain and Statistical IBIS-AMI Analyses
Comparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft Asian IBIS Summit 2017 Shanghai, PRC November 13, 2017 9 Combinations of TX and RX Model Types AMI file has: GetWave_Exists
More informationComparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft
Comparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft Asian IBIS Summit 2017 Taipei, ROC November 15, 2017 9 Combinations of TX and RX Model Types AMI file has: GetWave_Exists
More informationIBIS-AMI Modeling Recommendations European IBIS Summit 2010
IBIS-AMI Modeling Recommendations European IBIS Summit 2010 May 12, 2010 Hildesheim, Germany Kumar Keshavan Ken Willis Presented by Srdjan Djordjevic Agenda When is AMI required? IBIS-AMI key concepts
More informationExtending IBIS-AMI to Support Back-Channel Communications DesignCon IBIS Summit February 3, 2011 Santa Clara, CA
Extending IBIS-AMI to Support Back-Channel Communications DesignCon IBIS Summit February 3, 2011 Santa Clara, CA Kumar Keshavan - Sigrity Marcus Van Ierssel Snowbush IP (Gennum) Ken Willis - Sigrity Agenda
More informationIBIS-AMI Correlation and BIRD Update
IBIS-AMI Correlation and BIRD Update SiSoft IBIS-ATM Working Group 4/1/08 Signal Integrity Software, Inc. Overview DesignCon IBIS Summit presentation demonstrated interoperability and performance SiSoft
More informationIBIS 5.0 AMI Basic Principles. Basis for existing models and existing flows
IBIS 5.0 AMI Basic Principles Basis for existing models and existing flows Walter Katz IBIS AMI October 20, 2009 Signal Integrity Software, Inc. High Speed SerDes Challenges and Simplifications Simplifications
More informationEfficient End-to-end Simulations
Efficient End-to-end Simulations of 25G Optical Links Sanjeev Gupta, Avago Technologies Fangyi Rao, Agilent Technologies Jing-tao Liu, Agilent Technologies Amolak Badesha, Avago Technologies DesignCon
More informationINTRODUCTION TO IBIS-AMI. Todd Westerhoff, SiSoft Mike LaBonte, SiSoft Walter Katz, SiSoft
INTRODUCTION TO IBIS-AMI Todd Westerhoff, SiSoft Mike LaBonte, SiSoft Walter Katz, SiSoft SPEAKERS Image Image Mike LaBonte Senior IBIS-AMI Specialist, SiSoft mlabonte@sisoft.com www.sisoft.com An EDA
More informationDesignCon 2010 Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement
DesignCon 2010 Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement Todd Westerhoff, Signal Integrity Software, Inc. twesterh@sisoft.com Adge Hawes, IBM adge@uk.ibm.com
More informationCreating Broadband Analog Models for SerDes Applications
Creating Broadband Analog Models for SerDes Applications Adge Hawes, IBM adge@uk.ibm.com Doug White, Cisco dbwhite@cisco.com Walter Katz, SiSoft wkatz@sisoft.com Todd Westerhoff, SiSoft twesterh@sisoft.com
More informationBridging the Measurement and Simulation Gap Sarah Boen Marketing Manager Tektronix
Bridging the Measurement and Simulation Gap Sarah Boen Marketing Manager Tektronix 1 Agenda Synergy between simulation and lab based measurements IBIS-AMI overview Simulation and measurement correlation
More informationGetting the Most from IBIS-AMI: Tips & Secrets from the Experts
Getting the Most from IBIS-AMI: Tips & Secrets from the Experts Panel Discussion: Tuesday January 31, 2017, 4:45-6pm Moderator: Donald Telian, SiGuys Welcome to the 2017 AMI Panel Discussion Getting the
More informationA SerDes Balancing Act: Co-Optimizing Tx and Rx Equalization Settings to Maximize Margin. Donald Telian, Owner SiGuys Todd Westerhoff, VP SiSoft
A SerDes Balancing Act: Co-Optimizing Tx and Rx Equalization Settings to Maximize Margin Donald Telian, Owner SiGuys Todd Westerhoff, VP SiSoft AGENDA A SerDes Balancing Act Introduction Co-Optimization
More informationMulti-Gigabit Serial Link Simulation with Xilinx 7 Series FPGA GTX Transceiver IBIS-AMI Models
White Paper: 7 Series FPGAs WP424 (v1.) September 28, 212 Multi-Gigabit Serial Link Simulation with Xilinx 7 Series FPGA GTX Transceiver IBIS-AMI Models By: Harry Fu, Romi Mayder, and Ian Zhuang The 7
More informationBuilding IBIS-AMI Models from Datasheet Specifications
DesignCon 2016 Building IBIS-AMI Models from Datasheet Specifications Eugene Lim, Intel Corporation Donald Telian, SiGuys Abstract Some high-speed SerDes devices do not come with IBIS-AMI models. For situations
More informationIBIS-AMI: New Users, New Uses
IBIS-AMI: New Users, New Uses Panel Discussion: Wednesday January 31, 2018, 3:45-5pm Moderator: Donald Telian, SiGuys Welcome to the 2018 AMI Panel Discussion IBIS-AMI: New Users, New Uses o Donald Telian,
More informationDemonstration of SerDes Modeling using the Algorithmic Model Interface (AMI) Standard
DesignCon 2008 Demonstration of SerDes Modeling using the Algorithmic Model Interface (AMI) Standard Michael Steinberger, Signal Integrity Software, Inc. msteinb@sisoft.com, 715-720-4112 Todd Westerhoff,
More informationDesignCon Applying IBIS-AMI techniques to DDR5 analysis. Todd Westerhoff, SiSoft Doug Burns, SiSoft Eric Brock, SiSoft
DesignCon 2018 Applying IBIS-AMI techniques to DDR5 analysis Todd Westerhoff, SiSoft Doug Burns, SiSoft Eric Brock, SiSoft This page intentionally blank to support double-sided printing. Yes, we know it
More informationEDI CON USA Addressing DDR5 design challenges with IBIS-AMI modeling techniques. Todd Westerhoff, SiSoft Doug Burns, SiSoft Eric Brock, SiSoft
EDI CON USA 2017 Addressing DDR5 design challenges with IBIS-AMI modeling techniques Todd Westerhoff, SiSoft Doug Burns, SiSoft Eric Brock, SiSoft This page intentionally blank to support double-sided
More informationBackchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard
Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard By Ken Willis, Product Engineering Architect; Ambrish Varma, Senior Principal Software Engineer; Dr. Kumar Keshavan, Senior
More informationWhat is New in Wireless System Design
What is New in Wireless System Design Houman Zarrinkoub, PhD. houmanz@mathworks.com 2015 The MathWorks, Inc. 1 Agenda Landscape of Wireless Design Our Wireless Initiatives Antenna-to-Bit simulation Smart
More informationEQUALIZERS. HOW DO? BY: ANKIT JAIN
EQUALIZERS. HOW DO? BY: ANKIT JAIN AGENDA DFE (Decision Feedback Equalizer) Basics FFE (Feed-Forward Equalizer) Basics CTLE (Continuous-Time Linear Equalizer) Basics More Complex Equalization UNDERSTANDING
More informationDesignCon IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems. Hongtao Zhang, Xilinx Inc.
DesignCon 2015 IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems Hongtao Zhang, Xilinx Inc. hongtao@xilinx.com Fangyi Rao, Keysight Technologies fangyi_rao@keysight.com Xiaoqing Dong, Huawei Technologies
More informationBuilding IBIS-AMI Models From Datasheet Specifications
TITLE Building IBIS-AMI Models From Datasheet Specifications Eugene Lim, (Intel of Canada) Donald Telian, (SiGuys Consulting) Image SPEAKERS Eugene K Lim Hardware Design Engineer, Intel Corporation eugene.k.lim@intel.com
More informationVirtex-5 FPGA RocketIO GTX Transceiver IBIS-AMI Signal Integrity Simulation Kit User Guide
Virtex-5 FPGA RocketIO GTX Transceiver IBIS-AMI Signal Integrity Simulation Kit User Guide for SiSoft Quantum Channel Designer Notice of Disclaimer The information disclosed to you hereunder (the Materials
More informationKeysight Technologies IBIS-AMI Modeling of Asynchronous High Speed Link Systems
Keysight Technologies IBIS-AMI Modeling of Asynchronous High Speed Link Systems by Hongtao Zhang, Xilinx Inc. Fangyi Rao, Keysight Technologies Daniel (Zhaoyin) Wu, Xilinx Inc. Geoff Zhang, Xilinx Inc.
More informationSV2C 28 Gbps, 8 Lane SerDes Tester
SV2C 28 Gbps, 8 Lane SerDes Tester Data Sheet SV2C Personalized SerDes Tester Data Sheet Revision: 1.0 2015-03-19 Revision Revision History Date 1.0 Document release. March 19, 2015 The information in
More informationStatistical Link Modeling
April 26, 2018 Wendem Beyene UIUC ECE 546 Statistical Link Modeling Review of Basic Techniques What is a High-Speed Link? 1011...001 TX Channel RX 1011...001 Clock Clock Three basic building blocks: Transmitter,
More informationTrue Differential IBIS model for SerDes Analog Buffer
True Differential IBIS model for SerDes Analog Buffer Shivani Sharma, Tushar Malik, Taranjit Kukal IBIS Asia Summit Shanghai, China Nov. 14, 2014 Agenda Overview of Differential IBIS Description of test-case
More informationAsian IBIS Summit, Tokyo, Japan
Asian IBIS Summit, Tokyo, Japan Satoshi Nakamizo / 中溝哲士 12 Nov. 2018 Keysight Technologies Japan K.K. T h e d a t a e y e i s c l o s i n g 1600 3200 6400 Memory channel BW limited Rj improving slowly
More informationNew SI Techniques for Large System Performance Tuning
DesignCon 2016 New SI Techniques for Large System Performance Tuning Donald Telian, SiGuys telian@siguys.com Michael Steinberger, SiSoft msteinb@sisoft.com Barry Katz, SiSoft bkatz@sisoft.com Abstract
More information2015 The MathWorks, Inc. 1
2015 The MathWorks, Inc. 1 What s Behind 5G Wireless Communications? 서기환과장 2015 The MathWorks, Inc. 2 Agenda 5G goals and requirements Modeling and simulating key 5G technologies Release 15: Enhanced Mobile
More informationEffect of Power Noise on Multi-Gigabit Serial Links
Effect of Power Noise on Multi-Gigabit Serial Links Ken Willis (kwillis@sigrity.com) Kumar Keshavan (ckumar@sigrity.com) Jack Lin (jackwclin@sigrity.com) Tariq Abou-Jeyab (tariqa@sigrity.com) Sigrity Inc.,
More informationDesignCon Comparison of Two Statistical Methods for High Speed Serial Link Simulation
DesignCon 2013 Comparison of Two Statistical Methods for High Speed Serial Link Simulation Masashi Shimanouchi, Altera Corporation mshimano@alatera.com Mike Peng Li, Altera Corporation mpli@altera.com
More informationHigh-Speed Transceiver Toolkit
High-Speed Transceiver Toolkit Stratix V FPGA Design Seminars 2011 3.0 Stratix V FPGA Design Seminars 2011 Our seminars feature hour-long modules on different Stratix V capabilities and applications to
More informationVirtex-5 FPGA RocketIO GTP Transceiver IBIS-AMI Signal Integrity Simulation Kit User Guide
Virtex-5 FPGA RocketIO GTP Transceiver IBIS-AMI Signal Integrity Simulation Kit User Guide for SiSoft Quantum Channel Designer Notice of Disclaimer The information disclosed to you hereunder (the Materials
More informationWhat s Behind 5G Wireless Communications?
What s Behind 5G Wireless Communications? Marc Barberis 2015 The MathWorks, Inc. 1 Agenda 5G goals and requirements Modeling and simulating key 5G technologies Release 15: Enhanced Mobile Broadband IoT
More informationTo learn fundamentals of high speed I/O link equalization techniques.
1 ECEN 720 High-Speed Links: Circuits and Systems Lab5 Equalization Circuits Objective To learn fundamentals of high speed I/O link equalization techniques. Introduction An ideal cable could propagate
More informationXilinx Answer Link Tuning For UltraScale and UltraScale+
Xilinx Answer 70918 Link Tuning For UltraScale and UltraScale+ Important Note: This downloadable PDF of an Answer Record is provided to enhance its usability and readability. It is important to note that
More information56+ Gb/s Serial Transmission using Duobinary Signaling
56+ Gb/s Serial Transmission using Duobinary Signaling Jan De Geest Senior Staff R&D Signal Integrity Engineer, FCI Timothy De Keulenaer Doctoral Researcher, Ghent University, INTEC-IMEC Introduction Motivation
More informationTITLE. Novel Methodology of IBIS-AMI Hardware Correlation using Trend and Distribution Analysis for high-speed SerDes System
TITLE Novel Methodology of IBIS-AMI Hardware Correlation using Trend and Distribution Analysis for high-speed SerDes System Hong Ahn, (Xilinx) Brian Baek, (Cisco) Ivan Madrigal (Xilinx) Image Hongtao Zhang
More informationCharacterizing and Modeling of a Linear CTE. Skipper Liang Asian IBIS Summit Shanghai, PRC November 13, 2017
Characterizing and Modeling of a Linear CTE Skipper Liang Asian IBIS Summit Shanghai, PRC November 13, 2017 To Divide a RX : For modeling a RX circuit, we usually need to separate the whole design into
More informationValidation & Analysis of Complex Serial Bus Link Models
Validation & Analysis of Complex Serial Bus Link Models Version 1.0 John Pickerd, Tektronix, Inc John.J.Pickerd@Tek.com 503-627-5122 Kan Tan, Tektronix, Inc Kan.Tan@Tektronix.com 503-627-2049 Abstract
More informationEnd-to-End System-Level Simulations with Repeaters for PCIe Gen4: A How-To Guide
DesignCon 2017 End-to-End System-Level Simulations with Repeaters for PCIe Gen4: A How-To Guide Yongyao Li, Huawei liyongyao@huawei.com Casey Morrison, Texas Instruments cmorrison@ti.com Fangyi Rao, Keysight
More informationReal-time Distributed MIMO Systems. Hariharan Rahul Ezzeldin Hamed, Mohammed A. Abdelghany, Dina Katabi
Real-time Distributed MIMO Systems Hariharan Rahul Ezzeldin Hamed, Mohammed A. Abdelghany, Dina Katabi Dense Wireless Networks Stadiums Concerts Airports Malls Interference Limits Wireless Throughput APs
More informationSERDES High-Speed I/O Implementation
SERDES High-Speed I/O Implementation FTF-NET-F0141 Jon Burnett Digital Networking Hardware A R P. 2 0 1 4 External Use Overview SerDes Background TX Equalization RX Equalization TX/RX Equalization optimization
More informationDesign for Reliability --
Design for Reliability -- From Self-Test to Self-Recovery Tim Cheng Electrical and Computer Engineering University of California, Santa Barbara Increasing Failure Sources and Failure Rates design errors
More informationBehavioral Modeling of Digital Pre-Distortion Amplifier Systems
Behavioral Modeling of Digital Pre-Distortion Amplifier Systems By Tim Reeves, and Mike Mulligan, The MathWorks, Inc. ABSTRACT - With time to market pressures in the wireless telecomm industry shortened
More informationUFS v2.0 PHY and Protocol Testing for Compliance. Copyright 2013 Chris Loberg, Tektronix
UFS v2.0 PHY and Protocol Testing for Compliance Copyright 2013 Chris Loberg, Tektronix Agenda Introduction to MIPI Architecture & Linkage to UFS Compliance Testing Ecosystem UFS Testing Challenges Preparing
More informationFrom Antenna to Bits:
From Antenna to Bits: Wireless System Design with MATLAB and Simulink Cynthia Cudicini Application Engineering Manager MathWorks cynthia.cudicini@mathworks.fr 1 Innovations in the World of Wireless Everything
More informationAnsoft Designer with Nexxim. Statistical Eye Capabilities
Ansoft Designer with Nexxim Statistical Eye Capabilities Problem Statement Load Generic 0.25um M odels Buffer PCIE Connector BYPASS Planar EM S S S TRL TRL TRL TRL TRL TRL Programmable W-Element SI Wave
More informationDelft University of Technology Faculty of Electrical Engineering, Mathematics and Computer Science
Delft University of Technology Faculty of Electrical Engineering, Mathematics and Computer Science Analysis and Design of Decision Feedback Equalizers for bitrates of 10Gbps and Beyond in Submicron CMOS
More informationQAM-Based Transceiver Solutions for Full-Duplex Gigabit Ethernet Over 4 Pairs of UTP-5 Cable. Motivation for Using QAM
QAM-Based Transceiver Solutions for Full-Duplex Gigabit Ethernet Over 4 Pairs of UTP-5 Cable Henry Samueli, Jeffrey Putnam, Mehdi Hatamian Broadcom Corporation 16251 Laguna Canyon Road Irvine, CA 92618
More informationAnalyze and Optimize 32- to 56- Gbps Serial Link Channels
Analyze and Optimize 32- to 56- Gbps Serial Link Channels January 26, 2017 Al Neves Chief Technologist Wild River Technology Jack Carrel SerDes Applications Engineer Xilinx Heidi Barnes SI/PI Applications
More informationTo learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed I/O link circuits
1 ECEN 720 High-Speed Links: Circuits and Systems Lab6 Link Modeling with ADS Objective To learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed
More informationDesignCon Panel discussion: What is New in DC-DC Converters? V. Joseph Thottuvelil GE Energy Chris Young Intersil Zilker Labs
DesignCon 2012 Panel discussion: What is New in DC-DC Converters? Panelists: V. Joseph Thottuvelil GE Energy Chris Young Intersil Zilker Labs Steve Weir IPBLOX Istvan Novak* Oracle * panel organizer and
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 0 Lecture 8: RX FIR, CTLE, & DFE Equalization Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam is
More informationHigh Speed I/O 2-PAM Receiver Design. EE215E Project. Signaling and Synchronization. Submitted By
High Speed I/O 2-PAM Receiver Design EE215E Project Signaling and Synchronization Submitted By Amrutha Iyer Kalpana Manickavasagam Pritika Dandriyal Joseph P Mathew Problem Statement To Design a high speed
More informationEE290C Spring Lecture 5: Equalization Techniques. Elad Alon Dept. of EECS 9" FR4 26" FR4. 9" FR4, via stub.
EE29C Spring 211 Lecture 5: Equalization Techniques Elad Alon Dept. of EECS Link Channels Attenuation [db] -1-2 -3-4 -5 9" FR4, via stub 9" FR4 26" FR4-6 26" FR4, via stub 2 4 6 8 1 frequency [GHz] EE29C
More informationWIRELESS TRANSCEIVER ARCHITECTURE
WIRELESS TRANSCEIVER ARCHITECTURE BRIDGING RF AND DIGITAL COMMUNICATIONS Pierre Baudin Wiley Contents Preface List of Abbreviations Nomenclature xiii xvii xxi Part I BETWEEN MAXWELL AND SHANNON 1 The Digital
More informationTDEC for PAM4 Potential TDP replacement for clause 123, and Tx quality metric for future 56G PAM4 shortwave systems
TDEC for PAM4 Potential TDP replacement for clause 123, and Tx quality metric for future 56G PAM4 shortwave systems 802.3bs ad hoc 19 th April 2016 Jonathan King 1 Introduction Link budgets close if: Tx
More informationReducing Development Risk in Communications Applications with High-Performance Oscillators
V.7/17 Reducing Development Risk in Communications Applications with High-Performance Oscillators Introducing Silicon Labs new Ultra Series TM Oscillators Powered by 4 th Generation DSPLL Technology, new
More informationTITLE. Image. Topic: Topic: Hee-Soo o LEE, Keysight Technologies Cindy Cui, Keysight Technologies
TITLE Topic: Accurate o Nam elementum Statistical-Based commodo mattis. Pellentesque DDR4 Margin Estimation using malesuada SSN blandit Induced euismod. Jitter Model Topic: Hee-Soo o LEE, Keysight Technologies
More informationECEN720: High-Speed Links Circuits and Systems Spring 2017
ECEN72: High-Speed Links Circuits and Systems Spring 217 Lecture 4: Channel Pulse Model & Modulation Schemes Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda Lab 1 Report
More informationc 2014 Drew J. Newell
c 2014 Drew J. Newell TRANSISTOR LEVEL X-PARAMETER SIMULATIONS OF EQUALIZATION CIRCUITS BY DREW J. NEWELL THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science
More information100 Gb/s: The High Speed Connectivity Race is On
100 Gb/s: The High Speed Connectivity Race is On Cathy Liu SerDes Architect, LSI Corporation Harold Gomard SerDes Product Manager, LSI Corporation October 6, 2010 Agenda 100 Gb/s Ethernet evolution SoC
More informationHow to anticipate Signal Integrity Issues: Improve my Channel Simulation by using Electromagnetic based model
How to anticipate Signal Integrity Issues: Improve my Channel Simulation by using Electromagnetic based model HSD Strategic Intent Provide the industry s premier HSD EDA software. Integration of premier
More informationDesigning Filters Using the NI LabVIEW Digital Filter Design Toolkit
Application Note 097 Designing Filters Using the NI LabVIEW Digital Filter Design Toolkit Introduction The importance of digital filters is well established. Digital filters, and more generally digital
More informationECEN 720 High-Speed Links: Circuits and Systems
1 ECEN 720 High-Speed Links: Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by
More information2002 IEEE International Solid-State Circuits Conference 2002 IEEE
Outline 802.11a Overview Medium Access Control Design Baseband Transmitter Design Baseband Receiver Design Chip Details What is 802.11a? IEEE standard approved in September, 1999 12 20MHz channels at 5.15-5.35
More informationECEN720: High-Speed Links Circuits and Systems Spring 2017
ECEN720: High-Speed Links Circuits and Systems Spring 207 Lecture 8: RX FIR, CTLE, DFE, & Adaptive Eq. Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 4 Report and Prelab
More informationSome Radio Implementation Challenges in 3G-LTE Context
1 (12) Dirty-RF Theme Some Radio Implementation Challenges in 3G-LTE Context Dr. Mikko Valkama Tampere University of Technology Institute of Communications Engineering mikko.e.valkama@tut.fi 2 (21) General
More informationCharacterize Phase-Locked Loop Systems Using Real Time Oscilloscopes
Characterize Phase-Locked Loop Systems Using Real Time Oscilloscopes Introduction Phase-locked loops (PLL) are frequently used in communication applications. For example, they recover the clock from digital
More informationPerformance Analysis of FIR Filter Design Using Reconfigurable Mac Unit
Volume 4 Issue 4 December 2016 ISSN: 2320-9984 (Online) International Journal of Modern Engineering & Management Research Website: www.ijmemr.org Performance Analysis of FIR Filter Design Using Reconfigurable
More informationUSE OF MATLAB IN SIGNAL PROCESSING LABORATORY EXPERIMENTS
USE OF MATLAB SIGNAL PROCESSG LABORATORY EXPERIMENTS R. Marsalek, A. Prokes, J. Prokopec Institute of Radio Electronics, Brno University of Technology Abstract: This paper describes the use of the MATLAB
More informationModeling & Simulating Antenna Arrays and RF Beamforming Algorithms Giorgia Zucchelli Product Marketing MathWorks
Modeling & Simulating Antenna Arrays and RF Beamforming Algorithms Giorgia Zucchelli Product Marketing MathWorks giorgia.zucchelli@mathworks.nl 2016 The MathWorks, Inc. 1 Agenda Introducing antenna design
More informationDesignCon A Tale of Long Tails. Dai Fen, Huawei Mike Harwood, HSZ Consulting, Ltd.
DesignCon 2010 A Tale of Long Tails Dai Fen, Huawei daifen@huawei.com Mike Harwood, HSZ Consulting, Ltd. mike@hszconsulting.com Huang Chunxing, Huawei huangchunxing@huawei.com Mike Steinberger, SiSoft
More informationA Complete 64Gb/s/lane Active Electrical Repeater. Yue Lu, Jaeduk Han, Nicholas Sutardja Prof. Elad Alon January 23, 2014
A Complete 64Gb/s/lane Active Electrical Repeater Yue Lu, Jaeduk Han, Nicholas Sutardja Prof. Elad Alon January 23, 2014 The Electrical Signaling Challenge Required I/O speed rising dramatically, but power
More informationA 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a, Wang Zhengchen b, Gui Xiaoyan c,
4th International Conference on Computer, Mechatronics, Control and Electronic Engineering (ICCMCEE 2015) A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a,
More informationKeysight Technologies Understanding the SystemVue To ADS Simulation Bridge. Application Note
Keysight Technologies Understanding the To Simulation Bridge Application Note Introduction The Keysight Technologies, Inc. is a new system-level design environment that enables a top-down, model-based
More informationREVOLUTIONIZING THE COMPUTING LANDSCAPE AND BEYOND.
December 3-6, 2018 Santa Clara Convention Center CA, USA REVOLUTIONIZING THE COMPUTING LANDSCAPE AND BEYOND. https://tmt.knect365.com/risc-v-summit @risc_v ACCELERATING INFERENCING ON THE EDGE WITH RISC-V
More informationAchieving SerDes Interoperability on Altera s 28 nm FPGAs Using Introspect ESP
Achieving SerDes Interoperability on Altera s 28 nm FPGAs Using Introspect ESP Introduction Introspect Technology has implemented its award-winning Introspect ESP embedded signal integrity analyzer on
More informationA 24Gb/s Software Programmable Multi-Channel Transmitter
A 24Gb/s Software Programmable Multi-Channel Transmitter A. Amirkhany 1, A. Abbasfar 2, J. Savoj 2, M. Jeeradit 2, B. Garlepp 2, V. Stojanovic 2,3, M. Horowitz 1,2 1 Stanford University 2 Rambus Inc 3
More informationLow power SERDES transceiver for supply-induced jitter sensitivity methodology analysis
Low power SERDES transceiver for supply-induced jitter sensitivity methodology analysis Micro Chang htc Michael_Chang@hTC.com Jan 9, 2019 X 1 Agenda Jitter-aware target impedance of power delivery network
More informationPower Amplifier Linearization using RF Pre-Distortion JUNE, 2012
Power Amplifier Linearization using RF Pre-Distortion JUNE, 2012 1 PA Linearization Overview General principles Overview/Block Diagram of DPD and RFPD RFPAL System architecture & Implementation Predistortion
More informationHigh-Throughput, High- Sensitivity Measurement of Power Supply-Induced Bounded, Uncorrelated Jitter in Time, Frequency, and Statistical Domains
DesignCon 2013 High-Throughput, High- Sensitivity Measurement of Power Supply-Induced Bounded, Uncorrelated Jitter in Time, Frequency, and Statistical Domains Daniel Chow, Ph.D., Altera Corporation dchow@altera.com
More informationRF and Microwave Test and Design Roadshow 5 Locations across Australia and New Zealand
RF and Microwave Test and Design Roadshow 5 Locations across Australia and New Zealand ni.com Design and test of RADAR systems Agenda Radar Overview Tools Overview VSS LabVIEW PXI Design and Simulation
More information10GBASE-T Transmitter SNDR Definition (System ID Approach) IEEE P802.3an Task Force Santa Clara, Feb 2005 Albert Vareljian, Hiroshi Takatori KeyEye
10GBASE-T Transmitter SNDR Definition (System ID Approach) IEEE P802.3an Task Force Santa Clara, Feb 2005 Albert Vareljian, Hiroshi Takatori KeyEye 1 OUTLINE Transmitter Performance Evaluation Block Diagram
More informationA fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications
LETTER IEICE Electronics Express, Vol.10, No.10, 1 7 A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications June-Hee Lee 1, 2, Sang-Hoon Kim
More informationKeysight Technologies Virtual Flight Testing of Radar System Performance Using SystemVue and STK
Keysight Technologies Virtual Flight Testing of Radar System Performance Using SystemVue and STK White Paper Abstract Keysight SystemVue (electronic system simulation) and AGI STK (inertial and environmental
More informationModel-Based Design for Sensor Systems
2009 The MathWorks, Inc. Model-Based Design for Sensor Systems Stephanie Kwan Applications Engineer Agenda Sensor Systems Overview System Level Design Challenges Components of Sensor Systems Sensor Characterization
More informationAnalysis and Decomposition of Duty Cycle Distortion from Multiple Sources
DesignCon 2013 Analysis and Decomposition of Duty Cycle Distortion from Multiple Sources Daniel Chow, Ph.D., Altera Corporation dchow@altera.com Shufang Tian, Altera Corporation stian@altera.com Yanjing
More informationDetection, Interpolation and Cancellation Algorithms for GSM burst Removal for Forensic Audio
>Bitzer and Rademacher (Paper Nr. 21)< 1 Detection, Interpolation and Cancellation Algorithms for GSM burst Removal for Forensic Audio Joerg Bitzer and Jan Rademacher Abstract One increasing problem for
More informationEE 403: Digital Signal Processing
OKAN UNIVERSITY FACULTY OF ENGINEERING AND ARCHITECTURE 1 EEE 403 DIGITAL SIGNAL PROCESSING (DSP) 01 INTRODUCTION FALL 2012 Yrd. Doç. Dr. Didem Kıvanç Türeli didem.kivanc@okan.edu.tr EE 403: Digital Signal
More informationIssues with C_comp and Differential Multi-stage IBIS Models. Michael Mirmak Intel Corporation. IBIS Summit DesignCon East 2004 April 5, 2004.
Issues with C_comp and Differential Multi-stage IBIS Models Michael Mirmak Intel Corporation IBIS Summit DesignCon East 2004 April 5, 2004 Page 1 Agenda Background Typical serial/diff. interface buffer
More informationYour Network. Optimized.
Over 20 years of research both at the National Institute of Standards and Technology (NIST) and in private industry have been dedicated to the research and development of Symmetricom s phase noise and
More informationMaximizing MIMO Effectiveness by Multiplying WLAN Radios x3
ATHEROS COMMUNICATIONS, INC. Maximizing MIMO Effectiveness by Multiplying WLAN Radios x3 By Winston Sun, Ph.D. Member of Technical Staff May 2006 Introduction The recent approval of the draft 802.11n specification
More informationDesign and Verification of High Efficiency Power Amplifier Systems
Design and Verification of High Efficiency Power Amplifier Systems Sean Lynch Platform Engineering Manager MATLAB EXPO 2013 1 What is Nujira? Nujira makes Envelope Tracking Modulators that make power amplifiers
More information