Multi-Gigabit Serial Link Simulation with Xilinx 7 Series FPGA GTX Transceiver IBIS-AMI Models

Transcription

1 White Paper: 7 Series FPGAs WP424 (v1.) September 28, 212 Multi-Gigabit Serial Link Simulation with Xilinx 7 Series FPGA GTX Transceiver IBIS-AMI Models By: Harry Fu, Romi Mayder, and Ian Zhuang The 7 series GTX transceiver is the first 28 nm transceiver in the FPGA industry. The transceiver supports line rates from 5 Mb/s to 12.5 Gb/s. To enable fast high-speed serial link simulation and accurate link margin estimation, Xilinx provides an IBIS-AMI model kit for the 7 series GTX transceiver. The features and the quality of this IBIS-AMI model kit are the subject of this white paper. Copyright Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. ARM is a registered trademark and Cortex is a trademark of ARM in the EU and other countries. All other trademarks are the property of their respective owners. WP424 (v1.) September 28,

2 Introduction to High-Speed Serial Link Simulation Introduction to High-Speed Serial Link Simulation The high-technology industries have been transitioning from parallel to serial interfaces, and the data rates required of high-speed serial interfaces have been steadily increasing. These higher data rates have produced higher bandwidths, along with associated challenges for system design. Data recovery from a received serial data stream is negatively impacted by channel loss, reflections, crosstalk, etc. Overall, the complicated channel conditions that exist at 1 Gb/s and higher raise the importance of serial link simulation to a newly critical position. Meanwhile, the cost of simulation, like simulation time, rises as the transceiver circuits incorporate more and more complicated equalization features. Classic time-domain transient simulations based on multi-gigabit transceiver transistor netlists have reached a stage where simulation time is intolerably long, even for the fastest workstations. Over the past few years, therefore, the IBIS Algorithmic Modeling Interface (IBIS-AMI) has become the industry standard for transceiver simulation, with ~1,X faster time-domain simulation speeds while maintaining a high-level of accuracy. IBIS-AMI Developed by the IBIS Advanced Technology Modeling (IBIS-ATM) working group, the IBIS-AMI is a modeling standard for transceivers to enable fast and accurate simulation of multi-gigabit serial links. Semiconductor vendors provide IBIS-AMI models as compiled binary executables without exposing their proprietary algorithms. The models are portable through different EDA platforms. Multi-million bits of simulation can be done in minutes, thus making it practical to run low Bit-Error-Rate (BER) channel analysis. An IBIS-AMI simulation starts with analyzing the analog network and generating the impulse response characteristics of the transmitter and receiver analog buffers, the packages, and the link channel between transmitter and receiver, as illustrated in Figure 1. X-Ref Target - Figure 1 TX IBIS-AMI Model IBIS-AMI Model TX EQ (dll) TX Analog (ibs) TX Pkg Link Channel (PCB, Connector, Backplane, Cable, etc.) Pkg Analog (ibs) EQ CDR (dll) TX AMI AMI Channel Characterization to Generate the Impulse Response h AC (t) WP424_1_72512 Figure 1: Building Blocks of an IBIS-AMI Simulation and Channel Characterization The EDA tool calls Tx_Init() and Rx_Init() with the characterized channel impulse response to generate a system impulse response. To run a bit-by-bit simulation, the EDA tool takes the stimulus through Tx_GetWave(), system response, and 2 WP424 (v1.) September 28, 212

3 Introduction to High-Speed Serial Link Simulation Rx_GetWave(), then outputs the behavior of the overall system. The Init() and GetWave() calls are all defined in the executables of the AMI models. See Figure 2. X-Ref Target - Figure 2 Impulse Response Processing Channel Response h AC (t) TX Init h TEI (t) h AC (t) X h TEI (t) h AC (t) X h TEI (t) X h REI (t) Init h REI (t) Stimulus TX GetWave GetWave Post- Equalization Waveform Bit-by-Bit Simulation Figure 2: IBIS-AMI Simulation Flow 7 Series Transceiver IBIS-AMI Modeling Overview WP424_2_72512 With 7 series FPGAs, Xilinx offers a portfolio of four transceivers (Figure 3) to meet different application requirements, running from 5 Mb/s to 28.5 Gb/s. As a member of the IBIS Advanced Technology Modeling Group, Xilinx provides an IBIS-AMI model for each transceiver, which enables customers to run serial link simulation and estimate system performance. X-Ref Target - Figure 3 7 Series Transceiver Max Line Rate Industry-leading 28G with SSI for 1G/4G Datapath, 1GE, SONET/OTU, FC, Aurora, and CPRI 19.6G Max Line RAte (Gb/s) Low Power 13.1G for Wired OTU and Advanced DFE for 1G Backplanes 13.1 Low-cost Nx1G, PCIe Gen1/2/3, CPRI 9.8G, 1G Backplanes, and 11G OTU/SONET 12.5 High Volume, Low Power, Bare Die, Flip-Chip, and Wire-Bond 6.6 GTZ GTH GTX GTP Figure 3: Transceiver Portfolio Xilinx 7 Series FPGA Transceiver Portfolio WP424_3_8812 The 7 series GTX transceiver is the first of four 7 series transceivers available to the market. It is designed for best-in-class signal integrity. Figure 4 describes the blocks dedicated to achieving excellent signal integrity in the Kintex -7/Virtex -7 GTX transceiver in DFE mode. All the shaded blocks PLL, TX pre-emphasis, Automatic Gain Control (AGC), Linear Equalization (EQ), Decision Feedback WP424 (v1.) September 28,

4 Equalization (DFE), Clock Data Recovery (CDR), and Adaptation block are modeled in the GTX transceiver IBIS-AMI model kit. The generic packages for both transmitter and receiver are also provided in the model kit. X-Ref Target - Figure 4 Serial Transceiver FPGA Logic Hard PCS Logic PISO SIPO PLL CDR DFE Linear EQ TX Driver Pre-emphasis AGC TX PKG PKG Serial Channel 2-D Eye Scan Adaptation WP424_4_9412 Figure 4: 7 Series GTX Transceiver Blocks for Signal Integrity IBIS-AMI Features in 7 Series Transceiver Models IBIS-AMI Model Transportability The IBIS-AMI provides a standard mechanism for modeling transceivers. The models developed based on this standard must be able to run on any IBIS-AMI compatible EDA platform. The 7 series GTX transceiver IBIS-AMI model is fully compatible with the IBIS 5. standard. As part of the model release process, the transceiver models have been verified with different EDA tools that support IBIS-AMI simulations. Table 1 lists, in alphabetic order, the EDA tools with which the GTX transceiver IBIS-AMI model has been verified. Table 1: 7 Series GTX Transceiver EDA Tool Compatibility EDA Tool Compatible Agilent Advanced Design System Yes Mentor Graphics HyperLynx Yes Sigrity SystemSI Yes SiSoft Quantum Channel Designer Yes Figure 5 is a sample simulation setup provided in the GTX transceiver IBIS-AMI model kit. Figure 6 through Figure 9 show the statistical simulation results from four different EDA tools running this setup at 8 Gb/s. The four tools used are Agilent ADS 211.1, Mentor Graphics HyperLynx 8.2, Sigrity SystemSI 12., and SiSoft QCD X-Ref Target - Figure 5 7-GTX TX TX Pkg Sample PCIE Channel Pkg 7-GTX Sim Output Figure 5: Sample GTX Transceiver Measurement Setup WP424_5_ WP424 (v1.) September 28, 212

5 X-Ref Target - Figure Density Time (psec) WP424_6_71416 Figure 6: GTX Transceiver Statistical Simulation Result (Agilent ADS 211.1) X-Ref Target - Figure 7 2m Voltage 15m 1m 5m -5m -1m -15m -2m m 1m 2m 3m 4m 5m 6m 7m 8m 9m 1^-1 1^-2 1^-3 1^-4 1^-5 1^-6 1^-7 1^-8 WP424_7_71412 Figure 7: GTX Transceiver Statistical Simulation Result (Mentor Graphics HyperLynx 8.2) WP424 (v1.) September 28,

6 Volt UI WP424_8_71612 X-Ref Target - Figure 8 Figure 8: GTX Transceiver Statistical Simulation Result (Sigrity SystemSI 12.) X-Ref Target - Figure E E-2 Volts (mv). 3.8E-3 Probability E E Time (ps) Figure 9: GTX Transceiver Statistical Simulation Result (SiSoft Quantum Channel Designer ) WP424_9_ WP424 (v1.) September 28, 212

7 7 Series GTX Transceiver IBIS-AMI Model Flexibility Two modes of simulation are supported by the IBIS-AMI standard: statistical analysis and time domain simulation. Statistical analysis makes the assumption that TX/ equalization is both linear and time invariant. It uses the impulse response and applies the respective equalization to derive the statistical eye for the serial link. Statistical analysis is faster than a time-domain simulation and well suited to exploring a large design space. Time-domain simulation uses a waveform instead of impulse response during the simulation. It allows nonlinear and/or time-varying effects in the TX or IP to be represented, and it supports detailed modeling of the clock data recovery (CDR). The clock information from the CDR is used to generate the eye diagram post equalization. Time-domain analysis is well suited to detailed analysis of specific stimulus patterns or conditions. 7 series transceiver models support both statistical analysis and time-domain simulation. Figure 1 to Figure 13 are the time-domain simulation results with the setup described in Figure 5, page 4. X-Ref Target - Figure Density Time (psec) Figure 1: Sample GTX Transceiver Time-Domain Simulation Result (Agilent ADS 211.1) WP424_1_71416 WP424 (v1.) September 28,

8 X-Ref Target - Figure 11 Volts UI Figure 11: Sample GTX Transceiver Time-Domain Simulation Result (Mentor Graphics HyperLynx 8.2) e-5 1e-6 1e-7 1e-8 1e-9 WP424_11_71612 X-Ref Target - Figure Volt UI WP424_12_71412 Figure 12: Sample GTX Transceiver Time-Domain Simulation Result (Sigrity SystemSI 12.) 8 WP424 (v1.) September 28, 212

9 X-Ref Target - Figure E-2 2. Volts (mv) E-2 3.1E-3 Probability E E Time (ps) WP424_13_71412 Figure 13: Sample GTX Transceiver Time-Domain Simulation Result (SiSoft Quantum Channel Designer ) 7 Series GTX Transceiver IBIS-AMI Model Usability The IBIS-AMI models allow users to customize the settings of the transmitter and receivers do meet different channel conditions, as well as process/voltage/temperature variations. 7 series GTX transceiver IBIS-AMI model covers different signal integrity blocks in the transceiver. The same algorithm used to architect the transceiver is also implemented in the IBIS-AMI model. The same control parameters (listed in UG476, 7 Series FPGAs GTX/GTH Transceivers User Guides) available on the 7 series transceiver silicon are also available in the IBIS-AMI model. The match between the simulation parameters and the silicon parameters ensures the easy transformation of simulation setup to silicon setup, or vice-versa. Table 2 shows transmitter parameters that are available in the IBIS-AMI model and described in UG476, 7 Series FPGAs GTX/GTH Transceivers User Guides. In Figure 14, parts (a) and (b) show the waveform differences created by adjusting the TXPOSTCURSOR parameters. There are parameters only available in the IBIS-AMI models. For example, the process parameter to select the process/voltage/temperature (PVT) corner is only available for simulations. Exploring different PVT corners can ensure the system is stable under different conditions. WP424 (v1.) September 28,

10 Table 2: Sample Control Parameters in GTX Transceiver Receiver IBIS-AMI Models Parameter Name Tunable Bits Description TXDIFFCTRL [3:] TXPRECURSOR [4:] TXPOSTCURSOR [4:] Adjust transmitter output amplitude swing. There are 16 settings represented by 16 codes. The swing level for each code could vary with the process corner selection. The minimum output swing (differential peak-to-peak) is ~23 mv (code ); the maximum swing is ~1,28 mv (code 1111). Default = 4 b1111 Adjust transmitter pre-cursor emphasis. Default = 5 b Adjust transmitter post-cursor emphasis. Default = 5 b X-Ref Target - Figure 14 Waveform Figure 14: 27.9 A Time (nsec) 28.3 Signal without Emphasis Sample GTX Transceiver TX Waveforms with Different Post-Tap Settings 7 Series GTX Transceiver IBIS-AMI Model Accuracy Waveform WP424_14_8212 The main reason to move from traditional SPICE simulation to IBIS-AMI is the simulation time. While the speed of SPICE simulation makes it impractical to run system analysis, accuracy close to that of the SPICE simulation is an important goal of IBIS-AMI model development. Correlation with the SPICE simulation is always a significant milestone one that the 7 series GTX transceiver IBIS-AMI model has achieved. The same algorithms used to architect the transceiver blocks are implemented in the IBIS-AMI models. This simplifies the tuning process to correlate the behavior of the IBIS-AMI model with the behavior of the circuits. In Figure 15, parts (a) and (b) show comparisons of GTX transceiver receiver simulation eye-diagrams, with part (a) from IBIS-AMI simulations and part (b) from HSPICE models. Figure 16 is the time-domain representation of the two simulations, which produce virtually identical waveforms. The simulations were running at 12.5 Gb/s with TT corner. As shown in both Figure 15 and Figure 16, the IBIS-AMI and HSPICE simulations correlate with a high degree of exactness ~6 db B Time (nsec) Signal with 6 db De-Emphasis WP424 (v1.) September 28, 212

11 X-Ref Target - Figure 15 Model CTLE Output Eye (AGC-31, CTLE-5_3_, TT/85C/1p95/1p135) HSPICE CTLE Output Eye (AGC-31, CTLE-5_3_, TT/85C/1p95/1p135) Amplitude Amplitude Time x Time x1-11 WP424_15_71512 Figure 15: Model CTLE Output Eye (AGC-31, CTLE-5_3_, TT/85C/p95/1p135) X-Ref Target - Figure 16 CTLE Output Correlation (AGC-31, CTLE-5_3_, TT/85C/p95/1p135).3.2 Model Data HSPICE Data WP424_16_71612 Figure 16: Time Domain CTLE Output Correlation Waveform (AGC-31, CTLE-5_3_, TT/85C/p95/1p135) The GTX transceiver IBIS-AMI models have been correlated against SPICE simulations in hundreds of cases to cover different data rates, different equalization settings, and different PVT corners. Figure 15 and Figure 16 show only one sample of these correlation case results.the eye width and eye height of the simulation results are used as the main metrics to quantify the correlation. Figure 17 and Figure 18 show histograms of the correlation data on eye height and eye width, respectively. With ~5 valid data points, eye width correlates to well within 7%, and eye height correlates to well within 1%, with one outlier at 11.71%. WP424 (v1.) September 28,

12 X-Ref Target - Figure 17 7 Eye Width Correlation Histogram Figure 17: -1% -9% -8% -12% -11% -7% -6% -5% -4% -3% -2% % 1% 2% 3% 4% 5% 6% 7% 8% 9% -1% Eye Width Histogram for GTX Transceiver IBIS-AMI and HSPICE Correlation 11% 12% 1% WP424_17_71612 X-Ref Target - Figure Eye Height Correlation Histogram Figure 18: -1% -9% -8% -12% -11% -7% -6% -5% -4% -3% -2% % 1% 2% 3% 4% 5% 6% 7% 8% 9% -1% Eye Height Histogram for GTX Transceiver IBIS-AMI and HSPICE Correlation 11% 12% 1% WP424_18_ WP424 (v1.) September 28, 212

13 Conclusion Conclusion The 7 series FPGAs include a portfolio of four transceivers that covers different application needs with unrivalled signal integrity features. To enable channel analysis of the serial links with the transceivers, Xilinx continues to supporting IBIS-AMI models for high-speed transceivers. The 7 series GTX IBIS-AMI model is fully compatible with IBIS 5.. It has been verified with four industry-leading EDA platforms. Both statistical analysis and time-domain simulation are supported. Customers can manually adjust the transceiver settings to meet different channel conditions, or rely on the auto-adaptation features in the receiver to tune the transceivers. The model is well correlated with SPICE models. It provides an portable, fast, and accurate solution for link margin estimation on multi-gig serial links. The currently released IBIS-AMI model and the correlation reports can be requested through Xilinx FAEs or I/O specialists. For additional information, visit the Transceiver section on xilinx.com: Revision History The following table shows the revision history for this document: Date Version Description of Revisions 9/28/12 1. Initial Xilinx release. Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available AS IS and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: WP424 (v1.) September 28,