Virtex-5 FPGA GTX Transceiver OC-48 Protocol Standard

Transcription

1 Virtex-5 FPGA GTX Transceiver OC-48 Protocol Standard Characterization Report

2 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Virtex-5 FPGA GTX Transceiver OC-48 Protocol

3 Revision History The following table shows the revision history for this document. Date Version Revision 02/23/ Initial Xilinx release. Virtex-5 FPGA GTX Transceiver OC-48 Protocol

4 Virtex-5 FPGA GTX Transceiver OC-48 Protocol

5 Table of Contents Revision History Introduction Test Conditions Transceiver Selection Summary of Results OC-48 Electrical Characterization Details Transmitter Near-End Output Eye Test Methodology Test Results Transmitter Output Jitter Test Methodology Test Results Receiver Jitter Tolerance Test Methodology Test Results References Virtex-5 FPGA GTX Transceiver OC-48 Protocol 5

6 6 Virtex-5 FPGA GTX Transceiver OC-48 Protocol

7 Virtex-5 FPGA GTX Transceiver OC-48 Protocol Standard Introduction This characterization report compares the electrical performance of the Virtex -5 FPGA RocketIO GTX transceiver against the GR-253-CORE standard [Ref 1]. Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) are a set of related standards for synchronous data transmission over fiber optic networks. SONET links are traditionally used in the telecommunication industry. The applicable test specifications are found in GR-253, International Telecommunication Union Telecommunication Standardization Sector (ITU-T) G.783 [Ref 2], and ITU-T G.957 [Ref 3]. The specifications are written for optical signals. Thus, a reference optical device is used in the test setup. The characterization is performed as per specifications at a data rate of Gb/s across voltage, temperature, and worst-case transceiver performance corners. The following tests are included in this report: Transmitter Output Jitter Receiver Jitter Tolerance Test Conditions Table 1 and Table 2 show the supply voltage and temperature conditions, respectively. Table 1: Supply Voltage Test Conditions Condition MGTAVCC (V) MGTAVCCPLL (V) MGTAVTTRX (V) MGTAVTTTX (V) V MIN V MAX Notes: 1. Other FPGA voltages remain at their nominal values. Table 2: Temperature Test Conditions Condition Temperature ( C) T Virtex-5 FPGA GTX Transceiver OC-48 Protocol 7

8 Transceiver Selection Table 2: Temperature Test Conditions (Cont d) Condition Temperature ( C) T 0 0 T Transceiver Selection As part of the transceiver selection process, volume generic transceiver characterization is first performed across process, voltage, and temperature (PVT). The generic data from this characterization can be found in Virtex-5 FPGA RocketIO GTX Transceiver Characterization Report [Ref 4]. Protocol-specific characterization is then performed using representative transceivers from generic characterization. The chosen transceivers represent a mixture of worst-case and typical performance transmitters and receivers. Transceivers with the absolute worst-case transmitter output jitter and receiver jitter tolerance are selected from the corner silicon used during generic volume characterization. The histograms in this characterization report are therefore skewed towards worst-case performance and do not contain a true statistical representation of the entire population. Summary of Results Table 3 shows a comparison of the GTX transceiver using two reference clock rates: MHz and MHz. The data reported in Table 3 represents the worst-case voltage, temperature, and performance corners tested. Table 3: OC-48 Characterization: Summary of Results Test Parameter Specification (P2P) (1) Test Results for MHz REFCLK (P2P) Test Results for MHz REFCLK (P2P) Units Compliant Transmitter HP1 + LP UI Yes Output Jitter (2) Receiver Jitter HP1 + LP UI Yes Tolerance (3) HP2 + LP UI Yes Notes: 1. P2P is peak to peak. 2. Tests were run for 60 seconds as per the ITU-T Recommendation G The jitter tolerance tester is limited at UI. Table 3 uses standard SONET terminology for filters: HP, HP1, HP2, and LP. These values are described in Figure 1 and Table Virtex-5 FPGA GTX Transceiver OC-48 Protocol

9 OC-48 Electrical Characterization Details X-Ref Target - Figure Jitter Generate Mask Jitter Tolerance Mask HP1 UI 1.00 HP HP LP Frequency (Hz) RPT116_01_ Figure 1: OC-48 Jitter Tolerance and Generation Filter Specifications Table 4: SONET Filter Description Parameter HP HP1 HP2 LP Specification 12 KHz 6 KHz 1 MHz 20 MHz OC-48 Electrical Characterization Details This section contains the detailed OC-48 test methodology and results of each test summarized in Table 3. The GTX transceiver is configured using version 1.5 of the RocketIO GTX Wizard, including attribute settings. GTX transceiver attribute settings that differ from the GTX Wizard default settings are identified in Table 6, Table 7, page 12, and Table 9, page 15 for each test. Table 5 shows the phase-locked loop (PLL) settings for OC-48 characterization for MHz and MHz REFCLKs. Table 5: Gb/s Line Rate PLL Settings Data Rate (Gb/s) PLL Frequency (GHz) REFCLK Frequency (MHz) PLL_DIVSEL_REF PLL_DIVSEL_FB and DIV PLL_TXDIVSEL_OUT and PLL_RXDIVSEL_OUT = = 16 2 Virtex-5 FPGA GTX Transceiver OC-48 Protocol 9

10 OC-48 Electrical Characterization Details Transmitter Near-End Output Eye This section details the test methodology and results of the transmitter near-end output eye. Test Methodology The FPGA is configured to transmit a received pattern on the TX data pins, and the resulting eye is captured using an Agilent DSA91304A infiniium high-performance oscilloscope for 1,000 samples at nominal voltage and room temperature. Table 6 details the test setup and conditions. Table 6: Transmitter Near-End Output Eye Test Setup and Conditions Parameter Value Load Board Measurement Instrument Pattern Temperature ML523 characterization platform, revision D (FF1136) Agilent DSA91304A infiniium high-performance oscilloscope: 13 GHz OTN bulk PRBS23 Room temperature TX Amplitude/Pre-Emphasis Maximum amplitude, TXDIFFCTRL = 111 TX Coupling Voltage AC coupled using DC blocks Nominal Test Results Figure 2 and Figure 3 show the transmitter near-end output eye at Gb/s with MHz and MHz REFCLKs, respectively. X-Ref Target - Figure 2 RPT116_02_ Figure 2: TX Near-End Output Eye (2.488 Gb/s with MHz REFCLK) 10 Virtex-5 FPGA GTX Transceiver OC-48 Protocol

11 OC-48 Electrical Characterization Details X-Ref Target - Figure 3 RPT116_03_ Figure 3: TX Near-End Output Eye (2.488 Gb/s with MHz REFCLK) Transmitter Output Jitter This section details the transmitter output jitter test methodology and test results. Test Methodology Transmitter output jitter data was collected using the test setup shown in Figure 4. A JDSU ONT-506 optical network tester was used to collect the output jitter data. To obtain the appropriate reference clock rate for the GTX transceiver under test, the bit rate clock supplied by the JDSU optical network tester was divided down by factors of eight ( MHz REFCLK) and sixteen ( MHz REFCLK) using the Agilent 81134A pulse pattern generator. Virtex-5 FPGA GTX Transceiver OC-48 Protocol 11

12 OC-48 Electrical Characterization Details X-Ref Target - Figure 4 JDSU ONT-506 Agilent E3631A 0 6V, 5A / 0 ±25V, 1A Electrical Connection Display Adjust TxClk TxData RxClk On/Off Function GPIB Addr = 6 Voltage/Current 6V + 25V COM - RxData MGTAVTT Power Supply Optical Connection TxData TxData RxData RxData Agilent E3631A 0 6V, 5A / 0 ±25V, 1A Display Adjust Function Voltage/Current On/Off 6V V - - COM - GPIB Addr = 5 MGTAVTT Power Supply 81134A 3.35 GHz Pulse/Pattern Generator Display Keyboard and Miscellaneous Buttons Clock Input Output Channel 2 Output GPIB Addr = 13 Start Input Trigger Out Channel 1 Output Output Xilinx SMA-SFP RXN RXP TXP TXN Channel 1 TXP TXN RXP RXN MGTAVCC 1.0V AVCCPLL 1.0V AVTTTX 1.2V SMA Matched Pair Cables for GT Receiver SMA Matched Pair Cables for GT Transmitter SMA Matched Pair Cables for GT Clocks SC to LC Fibre Cable, Single Mode Cable for 1.0V Power Supply Cable for 1.2V Power Supply Cable for Ground Power Supply DC Blocks 50Ω Termination CLKN CLKP Channel 1 Virtex-5 FPGA GND AVTTRX 1.2V ML523 Virtex-5 FPGA DUT Board RPT116_04_ Figure 4: OC-48 Transmitter Output Jitter Test Setup Table 7 details the test setup and conditions. Table 7: OC-48 Transmitter Output Jitter Test Setup and Conditions Parameter Value Load Board ML523 characterization platform, revision D (FF1136) Measurement Instrument JDSU ONT-506 optical network tester BN 3061/90.27 Optical to SFP Board Pattern FiberOn FTM-3128C-SL2G OTN bulk PRBS23 REFCLK MHz: JDSU bit rate clock divided by MHz: JDSU bit rate clock divided by 16 Temperature T -40, T 0, T Virtex-5 FPGA GTX Transceiver OC-48 Protocol

13 OC-48 Electrical Characterization Details Table 7: OC-48 Transmitter Output Jitter Test Setup and Conditions (Cont d) Parameter Value TX Amplitude/Pre-Emphasis TX Coupling Voltage GTX transceiver attributes: TXDIFFCTRL = 000 TXBUFDIFFCTRL = 101 TXPREEMPHASIS = 0000 AC coupled using DC blocks V MIN, V MAX Test Results Figure 5 and Figure 6 show the output jitter test results for MHz and MHz REFCLKs, respectively, using an OTN bulk PRBS23 pattern. Due to mechanical limitations, the measurement is taken with 4 to 6.8 inches of FR4 between the TXP/TXN FPGA pins and the SMA connectors on the ML523 characterization platform. The added FR4 channel contributes additional ISI (deterministic jitter) when tested with an OTN bulk PRBS23 pattern, artificially increasing the measured output jitter. X-Ref Target - Figure 5 Number of Datapoints TJ (UI) RPT116_05_ Figure 5: OC-48 Transmitter Output Jitter Test Results (OTN Bulk PRBS23) Using MHz REFCLK Virtex-5 FPGA GTX Transceiver OC-48 Protocol 13

14 OC-48 Electrical Characterization Details X-Ref Target - Figure 6 Number of Datapoints TJ (UI) RPT116_06_ Figure 6: OC-48 Transmitter Output Jitter Test Results (OTN Bulk PRBS23) Using MHz REFCLK Table 8 summarizes the results of the transmitter output jitter characterization. Table 8: Summary of OC-48 Transmitter Output Jitter Characterization (1) Parameter Specification (P2P) Test Results for MHz REFCLK (P2P) Test Results for MHz REFCLK (RMS) Test Results for MHz REFCLK (P2P) Test Results for MHz REFCLK (RMS) Units Compliant HP1 + LP UI Yes Notes: 1. Tests were run for 60 seconds as per the specification. Receiver Jitter Tolerance This section details the receiver jitter tolerance test methodology and test results. Test Methodology Receiver jitter tolerance was measured using the test setup shown in Figure 4, page 12. The JDSU optical network tester generates an SDH frame using a PRBS23 pattern. The GTX transceiver under test recovers the data and transmits the pattern back to the error detector input of the optical network tester where bit errors are measured. To obtain the appropriate reference clock rate for the GTX transceiver under test, the bit rate clock supplied by the JDSU optical network tester is divided down by factors of eight ( MHz REFCLK) and sixteen ( MHz REFCLK) using the Agilent 81134A pulse pattern generator. Eye diagrams are generated using the Agilent DSA91304A oscilloscope Virtex-5 FPGA GTX Transceiver OC-48 Protocol

15 OC-48 Electrical Characterization Details Figure 7 shows a screen capture of the jitter injected to the GTX transceiver under test for OC-48 testing. X-Ref Target - Figure 7 RPT116_08_ Figure 7: OC-48 Eye Diagram of OTN Bulk PRBS23 Pattern Table 9 details the test setup and conditions. Table 9: OC-48 Receiver Jitter Tolerance Test Setup and Conditions Parameter Value Load Board ML523 characterization platform, revision D (FF1136) Measurement Instrument JDSU ONT-506 optical network tester BN 3061/90.27 Optical Module Optical to SFP Board Pattern FiberOn FTM-3128C-SL2G Xilinx HW-AFX-SMA-SFP, Rev. A OTN Bulk PRBS23 REFCLK MHz: JDSU bit rate clock divided by MHz: JDSU bit rate clock divided by 16 RX Coupling AC coupled using DC blocks Temperature T -40, T 0, T 100 Voltage V MIN, V MAX Table 10 lists filter parameter specifications. Table 10: OC-48 Jitter Tolerance Filter Description Parameter Specification HP1 HP2 LP 6 KHz 1 MHz 20 MHz Virtex-5 FPGA GTX Transceiver OC-48 Protocol 15

16 References Test Results Table 11 and Figure 8 show the results of jitter tolerance for both MHz and MHz REFCLKs at the worst-case voltage, temperature, and performance corners. Table 11: Summary of OC-48 Receiver Jitter Tolerance Characterization Parameter Specification (P2P) Test Results for MHz REFCLK (P2P) Test Results for MHz REFCLK (P2P) Units Compliant HP1 + LP UI Yes HP2 + LP UI Yes Notes: 1. The tolerance of the GTX transceiver devices exceeded the UI limit of the jitter tolerance tester. X-Ref Target - Figure Jitter Tolerance Mask UI Frequency (Hz) RPT116_08_ Figure 8: JItter Tolerance Results for Both MHz and MHz REFCLKs References This characterization report uses the following references: 1. GR-253-CORE, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, Telcordia Technologies, Inc., 2. ITU-T G.783, Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks, International Telecommunication Union, 3. ITU-T G.957, Optical Interfaces for Equipments and Systems Relating to the Synchronous Digital Hierarchy, International Telecommunication Union, 4. RPT109, Virtex-5 FPGA RocketIO GTX Transceiver Characterization Report Virtex-5 FPGA GTX Transceiver OC-48 Protocol