SCG2000 Series Synchronous Clock Generators
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1 SCG2000 Series Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois Phone: Fax: Bulletin SG035 Page 1 of 20 Revision 00 Date 23 AUG 04 Issued By MBATTS Application The Connor-Winfield SCG2000 Series provides high precision phase lock loop frequency translation for the telecommunication applications. SCG2000 Series is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, phase locked, synchronization and low phase gain for TDM, PDH, SONET and SDH network equipment. The SCG2000 Series provides a jitter filtered, wander following output signal synchronized to a superior Stratum or peer input reference signal. Features 3.3V High Precision PLL Tri-State Capability Active Alarms Guaranteed Free Run ±20ppm 1 Sec. Acquisition Time
2 General Description The SCG2000 Series provides high precision phase lock loop frequency translation for the telecommunication applications. The SCG2000 products generate a CMOS output from an intrinsically low jitter, voltage controlled crystal oscillator. Most models provide a jitter attenuated, internal reference that is connected to a Reference Output pin. SCG2000 Series is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, phase locked, synchronization for TDM, PDH, SONET and SDH network equipment. The SCG2000 Series provides a low phase gain (<0.2dB), jitter filtered, wander following output signal synchronized to a superior Stratum or peer input reference signal. The SCG2000 Series include the following features: Free Run, Tri-state and alarm outputs for Loss-of-Reference, (LOR), Loss-of-Lock, (LOL). During the LOR alarm, the SCG2000 will Functional Block Diagram Figure 1 also enter a Free Run state which will guarantee a 20 ppm accurate output. Additionally the Free Run mode may be entered manually by asserting a high signal to the Free Run Enable pin. The outputs, except the oscillator output, may be put into the tri-state high impedance condition for external testing purposes by asserting a high signal to the Tri-State Enable pin. The SCG2000 Series are 3.3 Volt components that typically draw less than 100 ma. All models have an acquisition time of approximately 1.0 second and can be used in applications that require temperature rating of 0-70 C. All models have a 33Ω resistor in series with the oscillator output. The SCG2000 maximum package dimensions are.78 x.83 x.35 on a six layer FR4 board with surface mount pins. Parts are assembled using high temperature solder to withstand surface mount reflow process. Tri-State Enable (Pin 10) Free Run Enable (Pin 5) ALARM DETECTION LOL Alarm Output (Pin 7) LOR Alarm Output (Pin 6) Reference Input (Pin 8) DIVIDER DPFD ANALOG FILTER FREE RUN CONTROL VCXO Oscillator Output (Pin 9) DIVIDER Optional Oscillator Output (Pin 1) Input Freq. Select A (Pin 14) Input Freq. Select B (Pin 13) Reference Output (Pin 1) (Not available on models with optional oscillator output) Table 1 Model Comparison Table Max Model Input Duty Reference Output Oscillator Output Notes Ref Freq Cycle (Pin #1) (Pin #9) SCG khz 40/60 = Input Ref Freq MHz to MHz Basic Model SCG MHz 40/60 8 khz MHz SCG MHz 40/ MHz MHz SCG khz 45/55 = Input Ref Freq MHz to MHz Tight Duty Cycle SCG khz 40/ MHz MHz SCG MHz 40/ MHz, MHz MHz, MHz Ref Output = Osc Output *Features which differentiate a model from the base model (SCG2000) are highlighted in boldface color and in the notes column. Data Sheet #: SG035 Page 2 of 20 Rev: 00 Date: 08/23/04
3 Pin Description Table 2 All SCG2000 Models Pin # Connection Description 1 Reference Output Output frequency is dependent on SCG model 2 TCK JTAG pin that is used only by Connor-Winfield for programming. Do not connect 3 TMS JTAG pin that is used only by Connor-Winfield for programming. Do not connect 4 Ground Ground 5 Free Run Enable/TDI Free Run enable pin. 1 = Free Run at nominal frequency ±20ppm. Input is pulled to GND 6 Loss of Reference (LOR) Alarm indicator. 1 = The reference has been lost. 7 Loss of Lock (LOL) Alarm indicator. 1 = Phase lock has been lost 8 Reference Input Input reference frequency 9 Oscillator Output Output frequency is dependent on SCG model 10 Tri-State enable Tri State control for all outputs except Oscillator Output. 1 = Hi-Z, 0 = normal. Input is pulled to GND. 11 Vcc 3.3V Supply Voltage. 12 TDO JTAG pin that is used only by Connor-Winfield for programming. Do not connect 13 Input Freq. Select B Control pin B used to select input frequency. Input is pulled to GND. 14 Input Freq. Select A Control pin A used to select input frequency. Input is pulled to GND. Typical Application Figure 2 BITS System Signal Input Select Timing Card #1 Line Card 1 A S A B MUX Y CW's STM/MSTM module B MUX Y CW's SCG 2000/4000 Clock out S RCV Timing Card #N Line Card #N S A B Y MUX CW's STM/MSTM module A B MUX Y CW's SCG 2000/4000 Clock out S RCV System Select Data Sheet #: SG035 Page 3 of 20 Rev: 00 Date: 08/23/04
4 Absolute Maximum Rating Table 3 All SCG2000 Models Symbol Parameter Minimum Nominal Maximum Units Notes Vcc Power Supply Voltage Volts V1 Input Voltage Volts Ts Storage Temperature deg. C Specifications Table 4 All SCG2000 Models Parameter Specifications Notes Voltage 3.3V ±5% 1.0 Current 100 ma Typical Temperature Range 0 to 70 C Input Jitter Tolerance (Input Jitter Frequencies > 10 Hz) Jitter Bandwidth 31.25us Typical (SCG2000, SCG2030, SCG2050) >1 us Typical (SCG2010, SCG2015, SCG2020, SCG2070) <15 Hz Acquisition Time Approx 1.0 second 2.0 Capture/Pull-in Range ±25 ppm Minimum Output Duty Cycle 40/60 % 50% Level Output Rise and Fall Time 3 20% to 80% output level Output Load 30 pf Alarms LOR, LOL Status on seperate outputs Free Run Accuracy ±20 ppm Package Fr4 SM 0.78" x.83" x 0.35" (maximum) TDEV 60 ps Typical MTIE 750 ps Typical Reference Output/Oscillator Output Offset 8 ns Static Offset ± 26 ns Maximum 3.0, 5.0 Dynamic Offset ± 20 ns Maximum 4.0, 5.0 Input And Output Characteristics Table 5 All SCG2000 Models Symbol Parameter Minimum Nominal Maximum Units Notes V IH High Level Input Voltage V V IL Low Level Input Voltage V T IO I/O to Output Valid 10 ns C O Output Capacitance 10 pf V HO High Level Output Voltage l oh = -4mA 2.4 Vcc Min. V IO Low Level Output Voltage l ol = 8mA 0.4 Vcc Max. T IR Input Reference Signal Pulse Width 30 ns NOTES: ` 1.0: Requires external regulation 2.0: From a 20 ppm offset in reference frequency 3.0: Offset between Reference Input and Reference room temp. 4.0: Offset change between Reference Input and Reference Output over temperature range from room temperature. 5.0: The SCG2015 will maintain an offset/skew, between the reference input and the oscillator output, of X ± 1ns. X is TBD. Data Sheet #: SG035 Page 4 of 20 Rev: 00 Date: 08/23/04
5 Output Jitter Specifications Table 6 All SCG2000 Models Jitter BW 10 Hz - 20 MHz SONET Jitter BW 12 KHz - 20 MHz Frequency (MHz) ps (RMS) m UI ps (RMS) m UI Typ Typ. 4 Typ Typ Typ. 4 Typ Typ Typ. 1 Max., 0.5 Typ Max Typ Typ. 1 Max., 0.5 Typ Max Typ Typ. 1 Max., 0.5 Typ Max Typ Typ. 1 Max., 0.5 Typ Max Typ Typ. 1 Max., 0.5 Typ Max Typ Typ. 1 Max., 0.5 Typ Max Typ Typ. 1 Max., 0.5 Typ Max Typ Typ. 1 Max., 0.5 Typ Max Typ Typ. 1 Max., 0.5 Typ Max Typ Typ. 1 Max., 0.5 Typ Max. * Note: These jitter specs only apply to version 2 models Output Programming Table 7 All SCG2000 Models Tristate Free Run Output 0 0 Locked to reference selected (default) 1 X Hi-Z Tristate condition 0 1 Free run at nominal frequency Alarm Status Table 8 All SCG2000 Models LOL Output LOR Output Alarm Output 0 0 No alarm 1 0 Loss-of-Lock X 1 Loss-of-Reference Maximum Package Dimensions Figure 3 Recommended Footprint Dimensions Figure " [20.32mm] 0.640" [16.26mm] 0.050" [1.27mm] 0.080" [2.03mm] 0.050" [1.27mm] 0.650" [16.51mm] 0.100" [2.54mm] Data Sheet #: SG035 Page 5 of 20 Rev: 00 Date: 08/23/04
6 Tape and Reel Dimensions Figure 5 Data Sheet #: SG035 Page 6 of 20 Rev: 00 Date: 08/23/04
7 SCG2000 Typical TDEV Figure E-12 TDEV (seconds) 10.0E E E E-3 1.0E E+0 Integration Time (τ) (seconds) SCG2000 Typical MTIE Figure 7 1.0E-9 MTIE (seconds) 100.0E E E E-3 1.0E E E+0 Observation Window (S) (seconds) Data Sheet #: SG035 Page 7 of 20 Rev: 00 Date: 08/23/04
8 SCG2000 Switch from Free Run to a new Reference Figure E E E-6 Phase Deviation (sec) -30.0E E E E Time (sec) SCG2000 Switch from a Reference to Free Run Figure 9 2.0E-6 1.0E E+0-1.0E-6 Phase Deviation (sec) -2.0E-6-3.0E-6-4.0E-6-5.0E-6-6.0E-6-7.0E-6-8.0E Time (sec) Data Sheet #: SG035 Page 8 of 20 Rev: 00 Date: 08/23/04
9 SCG2000 Step Response due to a -20ppm Freq. Step Figure E E E E+0 Frequency (Hz) E E+0-1.0E+3-1.2E+3-1.4E+3-1.6E+3-1.8E Time (sec) SCG2000 1µs Phase Transient Response Figure E-6 1.0E E-9 Time (sec) 600.0E E E E E Time (sec) Data Sheet #: SG035 Page 9 of 20 Rev: 00 Date: 08/23/04
10 100.0E E-9 1.0E E E-9 1.0E-9 1.0E-6 TDEV GR1244- Fig5. 1 GR1244- Fig5-3 Samp le MT IE Da ta fo r ST M - S 3/ M ST M - S 3 1.0E E-3 1.0E E E E E+3 Obs ervati on Tim e (s) Copyri ght 1998 Connor-Winfield al lr ights reserved Sample Wander G e ne r at i on (T DEV) fo r STM /M ST M-S3 Typi cal response second test -Ji ter applied (2 Hz) ref date APR kdh Typicalresponse second test- Jit ter appl ied (2UI@ 10 H z) refdat eapr kdh 100.0E E E E E E+0 1.0E+3 In tegration Time (sec) Copyright 198 C MT IE M ask ( A) M ask ( B) M as k GR onor -W infi el d a l r ights reser ved SCG2000 Jitter Attenuation Figure 12 Jitter attenuation (db) Jitter Attenuation vs. Input Frequency INPUT Jitter frequency (Hz) Typical System Test Setup Figure 13 This device supplies system time information. It can be thought of as supplying "absolute time" reference information GPS or LORAN Timing Source Possible Choice : Stanford Research Model: FS MHz MT IE (s Target System Under Test External Reference I nput 10 MHz External Reference I nput Arbitrary Waveform Generator Arbitrary Waveform Generator [Noise Source] DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 khz clock RZ with noise modulation Clock or BITS l ogic l evel clock input (TTL, CMOS, etc.) Noise Modulation Input Timing Card Line Card Timing Card OC-3 Line Card OC-12 Line Card OC-48 Line Card DS-1 Line Card TD E V ( sec Standards Compliance Documents MTIE, TDEV, Wander Transfer, and Wander Generation Plots DS1 rate [1.544 MHz] BITS Bipolar 10 MHz Time-stamped ensemble based on absolute time reference (10MHz input) DS-1, OC-3, OC-12 electrical or optical signals Phase Error data output 10 MHz Tektronix SJ300E External Reference Input HP53310A Modulation Analyzer / Time Interval Analyzer Wander Analyzer data (IEEE-488) External Reference I nput IEEE-488 Contr oller Platform for software HP 53305A Phase Analyzer HP E1748A Sync Measurement Tektronix Wander Analyzer Data Sheet #: SG035 Page 10 of 20 Rev: 00 Date: 08/23/04
11 Alarm Timing Diagram Figure 14 LOR Start-up Region Output 4 LOL Output Phase Detector External Reference Internal Reference LOR Output LOL Output 5 Phase Detector External Reference Internal Reference MHz &77.76 MHz Reference Input Units 8 khz Reference Input Units 1 < 1 µsec < µsec 2 1 µsec µsec 3 > 1 µsec > µsec 4 LOR is active when LOL is active 125 µsec wide range 5 Minimum pulse width = 2 µsec Minimum pulse width = 62.5 µsec Start-up Region During Start-up, The LOL Alarm will pulse during the first second of operation Data Sheet #: SG035 Page 11 of 20 Rev: 00 Date: 08/23/04
12 Solder Profile Figure Temp (Deg C) Time (minutes) Recommended Reflow Profile Peak Temp: 217 Deg C Max Rise Slope: 1.5 Deg C/Sec Time Above 150 C: 100 Sec Ordering Information SCG{XXXX}-{FFF.FFF}{M} XXXX equals a specific model (2000, 2010, 2020, 2030, 2050, 2070) FFF.FFF equals the Oscillator Output frequency ( , , , , , , , , , , , 125.0) M equals MHZ and is added to all part numbers Example: To order an SCG2000 with an Oscillator Output of MHz, Order part number SCG M Please contact Connor-Winfield for other frequencies that may be available. Data Sheet #: SG035 Page 12 of 20 Rev: 00 Date: 08/23/04
13 SCG2000 SCG2000 Individual Features: Four selectable References: 8, 16, 32, and 64 khz. Oscillator Output Available: MHz to MHz. The SCG2000 is Connor-Winfield s base model for the SCG2000 Series product line. The SCG2000 can lock to one of four input reference frequencies from 8 to 64 khz which is selectable using two input control pins. Input Reference Selection Table 9 SCG2000 Input Sel A Input Sel B Reference Frequency (Pin #14) (Pin #13) (Pin #8) khz (default) khz khz (see note 4.0) khz (see note 4.0) Reference and Output Availability Table 10 SCG2000 Input Reference Oscillator Output Reference Output (Pin #8) (Pin #9) (Pin #1) 8 khz 8 khz MHz 16 khz 16 khz 8 khz 8 khz 16 khz MHz 16 khz 32 khz 32 khz 8 khz 8 khz 16 khz 1.544, 2.048, , , 16 khz 32 khz , , and MHz 32 khz 64 khz 64 khz 8 khz MHz 8 khz Notes: Note 4.0: Not available with MHz output. Data Sheet #: SG035 Page 13 of 20 Rev: 00 Date: 08/23/04
14 SCG2010 SCG2010 Individual Features: Input References (Pin #8) at MHz. Oscillator Output (Pin #9) at MHz. Reference Output (Pin #1) at 8 khz. The SCG2010 is designed as a clean-up PLL with the input reference frequency (Pin #8) equal to the oscillator output (Pin #9). The reference output frequency (Pin #1) is 8 khz. The LOL alarm is designed to tolerate 1µs p-p of jitter on the reference. Jitter greater than 1µs p-p will result in LOL alarm pulses. Input Reference Selection Table 11 SCG2010 Input Sel A Input Sel B Reference Frequency (Pin #14) (Pin #13) (Pin #8) X X MHz (Default) X= Don t Care Reference and Output Availability Table 12 SCG2010 Input Reference Oscillator Output Reference Output (Pin #8) (Pin #9) (Pin #1) MHz MHz 8 khz Data Sheet #: SG035 Page 14 of 20 Rev: 00 Date: 08/23/04
15 SCG2020 SCG2020 Individual Features: Input References (Pin #8) at MHz. Oscillator Output (Pin #9) at MHz. Reference Output (Pin #1) at MHz. The SCG2020 accepts a MHz Input Reference (Pin #8) and provides a MHz Output Reference (Pin #1) and a MHz signal output on Output #2. The LOL alarm is designed to tolerate 1µs p-p of jitter on the reference. Jitter greater than 1µs p-p will result in LOL alarm pulses. Input Reference Selection Table 15 SCG2020 Input Sel A Input Sel B Reference Frequency (Pin #14) (Pin #13) (Pin #8) X X MHz (Default) X= Don t Care Reference and Output Availability Table 16 SCG2020 Input Reference Oscillator Output Reference Output (Pin #8) (Pin #9) (Pin #1) MHz MHz MHz Data Sheet #: SG035 Page 15 of 20 Rev: 00 Date: 08/23/04
16 SCG2030 Individual Features: Four selectable References: 8, 16, 32, and 64 khz. Oscillator Output Available: MHz to MHz. Tight Duty cycle SCG2030 Input Reference Selection Table 17 SCG2030 Input Sel A Input Sel B Reference Frequency (Pin #14) (Pin #13) (Pin #8) khz (default) khz khz (see note 4.0) khz (see note 4.0) The SCG2030 is similar to the SCG2000 but with a tighter duty cycle of 45/55. Reference and Output Availability Table 18 SCG2030 Input Reference Oscillator Output Reference Output (Pin #8) (Pin #9) (Pin #1) 8 khz 8 khz MHz 16 khz 16 khz 8 khz 1.544, 2.048, 8.448, , MHz 8 khz 16 khz 1.544, 2.048, 8.448, 20.48, MHz 16 khz 32 khz 8.448, , , MHz 32 khz 64 khz 8.448, and MHz 64 khz 8 khz MHz 8 khz Notes: Note 4.0: Not available with MHz output. Data Sheet #: SG035 Page 16 of 20 Rev: 00 Date: 08/23/04
17 SCG2050 SCG2050 Individual Features: Four selectable References: 8, 16, 32, and 64 khz. Oscillator Output Available: MHz only The SCG2050 can use any 1 of 4 selectable Input Reference frequencies with an Oscillator output of MHz and a Reference Output of MHz Input Reference Selection Table 19 SCG2050 Input Sel A Input Sel B Reference Frequency (Pin #14) (Pin #13) (Pin #8) khz (default) khz khz khz Reference and Output Availability Table 20 SCG2050 Input Reference Oscillator Output Reference Output (Pin #8) (Pin #9) (Pin #1) 8 khz MHz MHz 16 khz MHz MHz 32 khz MHz MHz 64 khz MHz MHz Data Sheet #: SG035 Page 17 of 20 Rev: 00 Date: 08/23/04
18 SCG2070 SCG2070 Individual Features: Input References (Pin #8) at MHz. Oscillator Output (Pin #9) equals Reference Output (Pin #1) The SCG2070 is designed to provide two output frequencies that are equal. The Reference Output is actually a second Oscillator Output. SCG2070 is available with either MHz outputs or with MHz outputs. The LOL alarm is designed to tolerate 1µs p-p of jitter on the reference. Jitter greater than 1µs p-p will result in LOL alarm pulses. Input Reference Selection Table 21 SCG2070 Input Sel A Input Sel B Reference Frequency (Pin #14) (Pin #13) (Pin #8) X X MHz (Default) X= Don t Care Reference and Output Availability Table 22 SCG2070 Input Reference Oscillator Output Reference Output (Pin #8) (Pin #9) (Pin #1) MHz MHz MHz MHz MHz MHz Data Sheet #: SG035 Page 18 of 20 Rev: 00 Date: 08/23/04
19 Data Sheet #: SG035 Page 19 of 20 Rev: 00 Date: 08/23/04
20 2111 Comprehensive Drive Aurora, Illinois Phone: Fax: Revision Revision Date Note 00 8/23/04 Final Release
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