Figure 1. Typical System Block Diagram

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1 Si5335 SOLVES TIMING CHALLENGES IN PCI EXPRESS, C OMPUTING, COMMUNICATIONS AND FPGA-BASED SYSTEMS 1. Introduction The Si5335 is ideally suited for PCI Express (PCIe) and FPGA-based embedded computing and communications systems. The Si5335 generates up to eight output clocks at up to four unique frequencies up to 350 MHz with subpico second jitter. The device's architecture is based on Silicon Lab's proven MultiSynth technology, which integrates the frequency synthesis capability of four low-jitter PLLs in a single device. To maximize design flexibility, each of the four differential, or up to eight CMOS clocks is independently configurable to support any signal format and I/O voltage. This combination of frequency and format flexibility simplifies clock trees by replacing fixed frequency clock generators, buffers, level translators and crystal oscillators with a single device, minimizing cost, PCB area and power consumption. 2. Multi-Rate, Multi-Format, Multi-Voltage Support Figure 1. Typical System Block Diagram Figure 1 illustrates a typical system design using a variety of devices that require specific clocks at specific frequencies and signal formats. Each device's clock requirement is satisfied by a separate oscillator or clock generator that supplies a clock at the required specific frequency using the appropriate signal format. This approach to clock sourcing requires several different parts, perhaps customized to meet the application, with corresponding impact to PCB real estate, BOM/AVL complexity, power consumption and cost. This is a typical design approach used to accommodate the varied clock needs of many systems, but a better solution is now available. Rev /11 Copyright 2011 by Silicon Laboratories AN624

2 Figure 2. Improved System Block Diagram In Figure 2, all of the individual clock sources have been replaced with a single Si5335 clock generator. The Si5335 can easily meet mixed format clocking requirements. It can provide 4 independent differential clocks or 8 singleended clocks, all synthesized from a single crystal reference or externally supplied clock. The Si5335 uses Silicon Labs' patented MultiSynth technology that allows each clock output to be a unique non-integer related frequency synthesized with 0 ppm frequency error up to 350 MHz. Stand alone jitter performance is <1 ps RMS over the common OC-48 specified phase noise bandwidth of 12 khz to 20 MHz. In addition, independent choice of supply voltages for core and/or output drivers, as well as output driver format support for CMOS, LVDS, LVPECL, HCSL, and CML allow for maximum design flexibility. The Si5335 also supports PCI Express (PCIe) compliant spread spectrum modulation for PCIe Gen 3.0/2.1/1.1 Refclk applications. 2 Rev. 1.0

3 3. System Noise Induced Clock Jitter In many systems, clock signal integrity can be adversely affected by a variety of sources having the effect of increasing system clock jitter. Excessive clock jitter can potentially render a clock unsuitable for its intended application, negatively impact system jitter margins, or degrade the system's BER (bit error rate) performance. Typical sources of increased clock jitter are as follows: Switched mode power supply noise (typically harmonics of switching regulation rate) Noise from FPGA/SoC/Peripheral dynamic switching currents conducted via power rails Noisy or distorted reference clocks due to crosstalk at connector The Si5335 is designed with all of these jitter sources in mind. The Si5335 incorporates an on-chip voltage regulator that provides industry-leading power supply rejection ratio (PSRR) performance that all but eliminates additive jitter due to noise on the power supply rails. In cases where the application requires output clocks to be locked to an input reference clock (e.g., PCIe applications), jitter on the input clock can be transferred directly to the synchronized output clock. Most general clock generators incorporate some type of low pass loop filter after the phase detector in the PLL. These filters usually have relatively high 3 db cutoffs of anywhere from 1.5 to 3 MHz or higher and will attenuate jitter above those frequencies. This doesn't help if the input clock has switching power supply noise induced jitter or other jitter components below those frequencies. Reducing the 3 db point of the PLL's loop filter sounds like a viable solution to attenuate jitter but there is a cost. Jitter attenuation is available with loop bandwidths ranging from sub-hz (specialized telecom), Hz to khz (e.g., Silicon Labs' Precision Clocks), and khz to MHz (e.g., Silicon Labs' Clock Generators). Because loop bandwidth is generally inversely proportional to device cost, it is helpful to choose the correct range of filtering actually required by a system. What is needed in many applications is jitter attenuation that addresses power supply switching band noise and connector crosstalk noise. This is where the Si5335 Clock Generator works best. The Si5335 has selectable loop filter settings of 475 khz or 1.6 MHz. The 475 khz setting is designed to attenuate jitter caused by, for example, switch-mode power supply (SMPS) noise and/or board interconnect (connector) induced crosstalk, to aid in meeting the clock jitter requirements for applications such as PCIe data links and xdsl line cards. Note the Si5335's loop filter is completely contained within the device, as shown in the block diagram below, without the need for external components. Unlike some clock generator devices with external loop filters that serve as noise coupling nodes which degrade output clock's jitter performance, the Si5335's loop filter is integrated on the chip. V DD XA/CLKIN XB/CLKINB P1 P2 P3 P5 P6 LOS CLKIN Osc Programmable Pin Function Options: OEB0/1/2/3 OEB_all SSENB FS[1:0] RESET Control PLL Bypass Low noise V regulator PLL w/ Adj. Loop Filter 475 khz/1.6 MHz Si5335 MultiSynth0 PLL Bypass MultiSynth1 PLL Bypass MultiSynth2 PLL Bypass MultiSynth3 OEB0 OEB1 OEB2 OEB3 VDDO0 CLK0A CLK0B VDDO1 CLK1A CLK1B VDDO2 CLK2A CLK2B VDDO3 CLK3A CLK3B Figure 3. Si5335 Block Diagram Rev

4 In general, the Si5335's 1.6 MHz loop bandwidth setting is used with the on-chip crystal oscillator or with a known clean input reference clock. When used to lock to an external input clock (via CLKIN) with excessive phase noise or spurs, the 475 khz loop bandwidth setting can be used to help improve output jitter due to phase noise on the clock input. See Table 1 for help with the loop filter bandwidth decision. Table 1. Si5335 Loop Bandwidth Selection Guidelines Loop BW = 1.6 MHz Loop BW = 475 khz Random noise floor X Spur attenuation X XTAL reference X Clean input clock X Excessive random noise at input X The real benefit of the adjustable loop filter can be seen in Table 2. In this application example, a 100 MHz clock from a system clock source (Ext Clock) with phase noise jitter, mainly due to switching power supply noise and/or board interconnect (connector) crosstalk, was supplied to a typical PCIe clock generator and to the Si5335. The generated output clocks were both 100 MHz HCSL formatted (PCIe RefClk), and locked to the 100 MHz external input clock (Ext Clock). All captured clock waveform data was processed using the Intel PCIe Clock Jitter Tool Ver Table 2. Si5335 PCIe RefClk Jitter Performance Jitter Tool Test Name Si5335 PCIe RefClk Generation Jitter Test Comparison (When locked to external clock source) HF/L Pass/ Pass/ F Fail Fail Test limit (ps) Ext Clock Jitter (ps) Typical PCIe Clock Generator (ps) Si5335 w/475 khz BW (ps) Notice the significant benefit using the Si5335's 475 khz loop filter setting in a synchronized PCIe RefClk application with jitter on the external clock input. The phase noise jitter on the input clock was effectively filtered out by the Si5335, and the Si5335 provided a clean 100 MHz PCIe RefClk with substantial jitter margin. In contrast, a typical PCIe clock generator device with a wide loop bandwidth provided only marginal jitter attenuation, resulting in only two of the eleven PCIe jitter specifications being met. Pass/ Fail Si5335 Margin PCIE_1_1 (J pk-pk) HF F F P 74% PCIE_2_0_5MHZ_1_5M_H3_FIRST HF F 7.35 F 1.05 P 66% PCIE_2_0_5MHZ_1_5M_H3_FIRST LF F 4.85 F 0.94 P 69% PCIE_2_0_5MHZ_1_5M_H3_STEP HF F 8.11 F 1.07 P 65% PCIE_2_0_5MHZ_1_5M_H3_STEP LF F 3.44 F 0.92 P 69% PCIE_2_0_8MHZ_1_5M_H3_FIRST HF F 5.86 F 0.78 P 75% PCIE_2_0_8MHZ_1_5M_H3_FIRST LF F 2.77 P 0.44 P 85% PCIE_2_0_8MHZ_1_5M_H3_STEP HF F 6.35 F 0.82 P 74% PCIE_2_0_8MHZ_1_5M_H3_STEP LF P 1.30 P 0.36 P 88% PCIE_3_0_2MHZ_4M_H3_FIRST HF F 1.87 F 0.31 P 69% PCIE_3_0_2MHZ_5M_H3_FIRST HF F 1.43 F 0.24 P 76% 4 Rev. 1.0

5 4. DVT Testing/Frequency Margining/Design Re-Use The Si5335 has another feature unique to cost effective clock generators: it can support up to three unique frequency plans (frequency profiles). One of three clock frequency profiles can be selected via the FS[1:0] pins providing flexibility to repurpose a single part for use in multiple circuit areas, provide for multiple product performance ranges, or on a different design (design reuse). Alternatively, this feature can be used during system DVT testing for frequency margining purposes by using two of the frequency profiles as a "high" and "low" frequency verification test limit. This feature can simplify test equipment requirements for production test, leading to lower overall costs. 5. Conclusion Mixed clocking applications require an understanding of the unique challenges they present and the need for carefully thought out designs. The Si5335 provides a solution to many of these challenges. The Si5335's frequency flexibility, multiple frequency profiles, and unprecedented output format flexibility coupled with selectable loop filter bandwidth and superior PSRR can help the designer avoid some of the common clock design pitfalls and produce more cost effective and robust products. Rev

6 DOCUMENT CHANGE LIST Revision 0.1 to Revision 1.0 Corrected errors in Figure 3, Si5335 Block Diagram, on page 3. 6 Rev. 1.0

7 NOTES: Rev

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