Achieving SerDes Interoperability on Altera s 28 nm FPGAs Using Introspect ESP

Transcription

1 Achieving SerDes Interoperability on Altera s 28 nm FPGAs Using Introspect ESP Introduction Introspect Technology has implemented its award-winning Introspect ESP embedded signal integrity analyzer on Altera s high-end 28 nm transceiver FPGAs. The result was a gamechanging ability to achieve link optimization and interoperability on complex system boards containing a multitude of SerDes links. This white paper describes the various Introspect and Altera technologies involved and illustrates, with real-life examples, the ability to self-measure, self-optimize, and self-repair SerDes links and systems. Voted by users as Test and Measurement World s Best in Test, Introspect ESP is a leading-edge on-die signal-integrity analyzer and embedded instrument for SerDes enabled devices. It transforms any system board into an in situ tester with the capability to measure, debug, and characterize in-line high-speed data links. When deployed on an Altera FPGA (Figure 1), Introspect ESP allows the FPGA to explore its own signal-integrity environment, thus helping users optimize performance and achieve the utmost quality for their high-speed PCB product. Figure 1 Instantiation of Introspect ESP on Altera 28 nm FPGA March Page 1

2 Unprecedented Signal Visibility Altera s 28 nm transceiver technology is an ideal match for Introspect ESP for various reasons. First, the transceivers offer best-in-class performance with respect to jitter performance, transmitter pre-emphasis, and receiver equalization. Additionally, the transceivers feature highly flexible on-die instrumentation (ODI) and clock recovery features that are exploited by Introspect ESP to enable unprecedented visibility into SerDes link performance on any system board. The rest of this white paper is organized as follows. First, the visibility capability of Introspect ESP on Altera s ODI is described. We then illustrate real-life examples of PCB issues that are identified by Introspect ESP and ODI. We then address the allimportant topic of parallel link optimization for achieving interoperability, and we even describe innovative self-repair opportunities with this technology. The application of Introspect ESP on Altera FPGA is illustrated in Figure 2. Importantly, the topic of this paper is the in-line self measurement of the links that are attached to the FPGA without requiring external equipment. It is the combination of Altera s ODI and Introspect ESP that enables unmatched capability in this regard, as measurement is performed across all connected lanes simultaneously. On the largest 28 nm Stratix V FPGAs, one can perform self measurement on more than 50 lanes simultaneously. Figure 2 Instantiation of Introspect ESP on an Altera FPGA within a system board March Page 2

3 With a connection scenario such as the one shown in Figure 2, Introspect ESP can be used to perform a multitude of measurementss as summarized in Figure 3. In short: digital capture & bit-error rate (BER) tests, bathtub plots, analog waveforms, time- and frequency-domain measurements, partial-response decision feedback equalization (DFE) eye diagrams, and jitter decomposition are all possible. Most importantly, no FPGA tool expertise is required. Figure 3 Gallery of features enabled by the setup shown in Figure 2 March /introspect.ca Page 3

4 Identifying PCB Issues The above measurements are all obtained by writing simple scripts within the Introspect user environment. The primary goal of these scripts is to identify potential issues in the PCB as well as optimize performance. Both of thesee topics are addressed next with real-life examples. Figure 4 illustrates a simplified 2-lane, 10 Gbps link that was recently verified using Introspect ESP. The link was part of a multi-lane 1000 Gbps Ethernet (100GbE) application, and development had been hampered by poor, intermittent performance. In the figure, we show that one of the two lanes in question had excessively large intra-pair mismatch, and this was identified readily and rapidly with Introspect ESP running on Altera ODI. Specifically, an eye diagram acquisition on the two Stratix V FPGA receivers revealed the two measurements shown in Figure 5. As can be seen, the properly routed trace has a wide eye opening with up to 0.85 UI receiver eye opening. On the other hand, the eye diagram for the improperly routed transmissionn line shows extremee distortion due to the mismatch between the positive and negative arms of the signal coming into the FPGA receiver. In this case, Introspect ESP and Altera ODI were able to identify the issue almost instantaneously. It was not an ASIC transmitter issue, an FPGA receiver issue, or even a software stack issue. Instead, it was a signal routing issue. At 10 Gbps, even the slightest of mismatch can cause dramatic effects as shown in the figure. Finally, it is imperative to note that the distortion in Figure 5 may have revealed a deceptively wide horizontal eye opening, but it is the entire eye shape that fails, which explains the poor BER performance. With heavy pseudorandom traffic, this link fails to pass a simple BER test using Introspect ESP. Figure 4 Simplified connection diagram of a real system board containing excessive intra-pair routing mismatch March /introspect.ca Page 4

5 (a) (b) Figure 5 Self-measured eye diagrams for (a) the properly matched and (b) the improperly matched signal traces Rapid, Parallel Link Optimization We now move on to the all-important topic of SerDes parameter optimization. The Altera 28 nm transceivers offer a multitude of controls that help optimize performance. For example, there are 64 different differential drive levels, 32 different post-cursor preemphasis levels, and so on. In all, a SerDes link between, say, an ASIC and an Altera FPGA can have a potential parameter space that is in the hundreds of millions per lane. While this offers tremendous flexibility for a wide variety of system applications, it can represent an overwhelming challenge to systems engineers who need to select optimal parameters for their own links. Introspect ESP includes built-in features that borrow from the field of multi-dimensional mathematical optimization in order to assist users in the deployment of massively parallel SerDes links. To illustrate this, Figure 6 shows a screen capture of the Introspect ESP user environment with a function call for receiver optimization. This function has been created for specific compatibility with Altera s 28 nm transceiver FPGAs, and it explores all possible receiver parameters for best performance. The user does not need to be an expert in FPGA programming in order to select receiver parameters. Once the optimal results are obtained by Introspect ESP, they can be exported for further use by other developers. March Page 5

6 Figure 6 A screenshot of a single receiver optimization command call in Introspect ESP For insight into the optimization process, Introspect ESP offers the ability to view all intermediate results in a Shmoo viewer, and this is illustrated in Figure 7. As can be seen, every setting is shown on a color map thatt displays the parameterr value being measured. In this optimization example, note thatt the green region (the region closest to optimal performance) is different (or slightly shifted) from lane to lane. This is expected since each lane is subjected to its own PCB trace and power supply environment. With Altera and Introspect, each lane gets its own optimal parameter value. Figure 7 Shmoo view of two lanes that have been optimized simultaneously. Note the difference in optimal settings between lanes March /introspect.ca Page 6

7 Finally, Figure 8 shows the outcome of the optimization process for one of the lanes. As can be seen from the very open eye diagram on the right hand side, optimization has yielded a much more optimal, much more guard-banded setting for the receiver than the default value before optimization. This helps maximize BER performance throughout the life of the product. (a) (b) Figure 8 Eye diagrams of a single link (a) before optimization, and (b) after optimization. Both images have the same x and y scales Innovative Self Repair We now describe repair possibilities enabled by self measurement. The main goal of any self measurement is to guarantee performance for one s own system. This offers the flexibility and freedom to make optimization and operation decisions based on the specific environment being measured, without being overburdened by any external parameters such as compliance eye masks. In fact, the very notion of compliance has been invented in the traditional sense to predict how a link will behave in its system environment. However, with Altera s ODI and Introspect ESP, the measurement is itself already within the system March Page 7

8 environment. There is no reason to be constrained by artificial compliance prediction tools. Instead, the goal is to achieve error free operation in one s own system. As an example of the self-repair innovation possibility, Figure 9 shows a real 8-lane bus in which one link (pink trace) has poor signal integrity performance. The corresponding eye diagram is shown in Figure 10. It is possible, when faced by a situation like this, to make programming or operational decisions that keep the system up without sacrificing yield. For example, system software can favor the high-margin lanes, or additional pre-emphasis and equalization can be applied to the weak link. Figure 9 integrity An 8-lane measurement in which one lane has poor signal (a) (b) Figure 10 Eye diagram of (a) a signal before repair compared to (b) a good signal March Page 8

9 Conclusion Introspect ESP has been deployed on Altera s 28 nm transceiver FPGAs, and this paper describes how the combination of worldclass transceiver technology and innovative self measurement are enabling tremendous productivity enhancement and pioneering solutions to the market place. We presented the Introspect/Altera combination at a high level and illustrated real-life examples of PCB issue identification, massively parallel link optimization, and even self repair. The solutions described in this white paper illustrate Altera s leadership in transceiver innovations such as ondie instrumentation (ODI) and in signal integrity performance. The transceiver features have been exploited fully by the Best in Test Introspect ESP in order to offer unprecedented visibility into the performance of links inside live systems. In addition to the topics presented in this paper, Introspect ESP offers tools for PLL and CDR measurement, frequency-domain measurement, and jitter injection. This makes it and Altera an ideal combination for creating modular instrument solutions [1]. A truly complete and instrument-grade capability is available in soft form, thus creating an entirely new test and optimization paradigm for the most advanced applications. References [1] Next Generation Digital Tester Design Using Introspect ESP, White Paper Further Information Introspect ESP Embedded Instruments: Introspect ESP Software: Acknowledgements Mohamed Hafed, CEO, Introspect Technology Mike Peng Li, Altera Fellow, Altera Vivek Sardana, Customer Marketing, Altera March Page 9