A Complete 64Gb/s/lane Active Electrical Repeater. Yue Lu, Jaeduk Han, Nicholas Sutardja Prof. Elad Alon January 23, 2014

Transcription

1 A Complete 64Gb/s/lane Active Electrical Repeater Yue Lu, Jaeduk Han, Nicholas Sutardja Prof. Elad Alon January 23, 2014

2 The Electrical Signaling Challenge Required I/O speed rising dramatically, but power budget is not increasing Must build very fast links Datarate ~80Gb/s Gb/s [ITRS 2010] Year At very low power consumption Normalized E/bit Energy efficiency ~5x improvement Year 2

3 Proposed Signaling Platform Tx Core 16-Gb/s x 4 lane Active Connector Tx 64-Gb/s Cable Primary focus 16-Gb/s x 4 lane Active Connector Rx Rx Core Dispersion AND Reflections Active Connector Active connector design isolates dispersion from reflections We believe this enables 64Gb/s soon! Evidence? 3

4 Cable Characteristic 1m long 32-AWG Twinax Cable from Samtech * Courtesy of Intel 0 Overall Channel Output UI-Spaced Pulse Overall Channel Output When sending 1V 64Gb/s pulse Mag (db) Amplitude (mv) Looks amenable to equalization! Freq (GHz) t [Normalized to Tsym] 4

5 Previous Receiver Equalizer 3-Tap DDR DFE Half Circuit 66Gb/s, 46mW Have realized these speeds relatively efficiently even in 65nm * Y. Lu and E. Alon, ISSCC

6 So What s Next? Implementing a complete active connector prototype while: Reducing power consumption Supporting RX feed-forward equalization Integrating energy-efficient timing recovery 4X16Gb/s Parallel RX Serializer 64Gb/s TX 64Gb/s RX Des 4X16Gb/s TX PI Logic PD Digital CDR Sync Divider Chain LPF 16GHz 32GHz DCO LF CDR Logic Dividers 6

7 Reducing Power: Previous Design 3-Tap DDR DFE Half Circuit Power Breakdown A large portion of power comes from the linear continuous-time summer for later taps 7

8 Current Integration Summer 1 1 V/V sw V/V sw 0 0 τ 0 t/t bit 1 T int 0 t/t bit 1 Continuous Summer I I Key: higher effective gain (impedance) for the same g m ~N τ (>3) power saving INT CS Tb τ Integrating Summer * T.O. Dickson et al, JSSC,

9 Integrating DFE Sim. Results 32mW for same functionality as ISSCC design DIP DIM VGA, CTLE, FFE 2nd, 3rd taps Integrator Dynamic summer Dynamic latch Delay 1st tap / QE /QE QO /QO / Delay / Design Optimization 2nd, 3rd taps 6.9 mw 22.5 mw 16.6 mw mw mw 22.7 mw Current Integration + Optimization Continuous time summer Dynamic summer Latches ISSCC Design Integrator Dynamic summer Latches New Design 9

10 Enabling RX FFE FFE DFE X Vout G -1 G 0 G +1 Vin Z -1 Z -1 Z -1 Reuse DFE dynamic latch design for delay stages So, key challenge is how to enable variable (analog) gain 10

11 Variable Gain Implementation VDD VDD VP MP VP MP CL VOM VOP CL CL VOM VOP CL VIP MIN VIM VIP MIN DAC VBN MN VBN MN Variable tail current doesn t maintain sufficient linearity vs. gain Unit cell design leads to large parasitics (power) for high resolution 11

12 Solution: Variable Bias Cascode VRST VP MP Decreasing VBNCAS CL DAC VIP VOM VOP VBNCAS MIN CL VIM Small Signal Gain VBN1 MN Input Signal (V) Adjusting cascode DC bias enables wide gain tuning range without degrading signal linearity (and minimal power overhead) 12

13 Clock Recovery Challenge I Q 2x oversampled CDR Any extra loading/clock phases very expensive at these rates Baud-rate CDR eliminates a phase and an extra deser. path But has some well-known issues Baud-rate CDR 13

14 Baud-rate CDR Challenge Baud-rate CDR looks for zero slope on the waveform Phase wandering for well-equalized inputs Ambiguous Locking Point False locking using MMSE algorithm Locked with DFE Optimum Pulse response with pre-cursor Locked to pre-cursor 14

15 Avoiding Phase Wandering Ambiguous Locking Point 1UI Integrator Unique Locking Point Integrator front-end avoids phase wondering 15

16 Avoiding False Locking +e dlev -e +e dlev -e - - Increases Look for the peak of the pulse response I.e., maximize the data level (dlev) Occurs when dlev/ φ = 0 Found by intentionally dithering by With sign-sign: [n+1] = [n] + k sgn( e) 16

17 Complete Clocking Path Using a single-loop architecture for the CDR Have a clean LC VCO on the RX, so no need for decoupled PLL & recovery bandwidth 17

18 Conclusions 64Gb/s links are on the way! Developing new techniques to continue improving power at these speeds: RX equalizers with I&D summer to reduce analog power Eye-max based baud-rate CDR reduces clocking and deserialization power A 65nm test-chip will be taped-out in mid. Feb. Stay tuned! 18

19 BWRC Sponsors Acknowledgements NSF Infrastructure Grant Berkeley Design Automation Integrand EMX Lorentz PeakView B. Casper, T. Karnik, F. Spagna of Intel, R. Bai, P. Y. Chiang of OSU, P. K. Hanumolu of UIUC, M.- S. Chen, C.-K. K. Yang of UCLA, V. Stojanovic of UC Berkeley, H. Hoss, K. Chang of Xilinx 19

20 Thanks! 20

21 Backup Slides 21

22 Integrator Output Timing 2nd, 3rd taps DFE Integrator Dynamic Latch + Summer from FFE CLK Voltage CLK high Optimal latching point Integration Reset Integration Reset High initial common integrator output drives dynamic latch input pair into triode Output level is not fully generated when clock is high Time

23 Solution: Delayed Clock 2nd, 3rd taps from FFE DFE Integrator CLK1 Passive delay Dynamic Latch + Summer CLK2 Integrator output Latch output (differential) With delayed clock W/o delayed clock CLK1 C H R H R D C D CLK2 Latch clock Latch tail node Turning on too early discharges the tail node of latches VCM Delay dynamic latch turn-on until integrator CM/DM has reached a reasonable value Requires small delay, so a passive RC delay element work very well

24 Complete FFE + DFE D +3 F -1 D +2 Gm L L L F 0 F +1 L Gm Gm L L L Gm L L L F +1 F 0 L Gm Gm D +1 D +1 L L L F -1 D +2 Put an I&D front-end at the very beginning Make sure the slope information required by CDR is generated RC-source degeneration is used as a CTLE Also helps FFE s linearity D +3 24

25 Phase Code CDR Time-Domain Simulation Pre-Cursor = 0.3 Post-Cursor = Phase Code vs. Updates DFE Coef Value Tap 1 Tap 2 Tap 3 DFE Taps vs. Updates dlev Value dlev Value vs. Updates Phase Code # of Updates x 10 4 Pre-Cursor = 0.6 Post-Cursor = Phase Code vs. Updates # of Updates x 10 4 DFE Coef Value # of Updates x DFE Taps vs. Updates 40 Tap 1 20 Tap 2 Tap # of Updates x 10 4 dlev Value # of Updates x 10 4 dlev Value vs. Updates # of Updates x

26 Loop Dynamics K PD p K i Ф Freq out est DCO (K DCO ) Ф est Z -1 Z -1 Update equations are the same as traditional 2nd order loop CDR Phase detector is different Interacts with dlev loop Need to evaluate its performance 26

27 PD Characterization Setup dlev loop faster than phase update In order not to loose dither correlation First assume we filter for data pattern (-1, 1, -1) such that we have explicit peak shape Later we will see how filtering for other data pattern may affect the CDR performance Noise source: AWGN for both voltage and jitter noises dlev error

28 Small-signal Behavior Average PD output vs. phase Choice on dither amplitude trades off gain/deadzone/slewing rate Dither amplitude ~1 jitter sigma is a good balance J.S. =0.04UI 28

29 Parallel to Serial Interface 2x 2x 2x 2x RX 2:4 4:8 8:16 RX /2 /2 /2 2:4 4:8 8:16 /2 /2 /2 D1[0:15], E1[0:15] D2[0:15], E2[0:15] FF D gen PRBS Gen. / Pattrn Mem MUX 64:4 4:1 DRV 64Gb/s Simplified CDR Model {D3}@16Gb/s {D4}@16Gb/s RX RX 2:4 2:4 4:8 8:16 /2 /2 /2 4:8 8:16 /2 /2 /2 {±I, ±Q}@8GHz D3[0:15], E3[0:15] D4[0:15], E4[0:15] D rx sel 1GHz Div. /2 {±I, in clk K pd K i /s K p /s K DCO /s out 16GHz DCO CDR Prop. Accum. CDR Logic Intg. Accum. BER Checker Separate jitter tracking path input data only sets frequency 1:64 deserialized first to improve timing margin ease high-speed resynchronization 29