行動裝置高速數位介面及儲存技術. 克服 MIPI PHY UniPro UniPort-M UFS 與 (LP)DDR4 測試挑戰 Master the latest MIPI PHY UniPro UniPort-M UFS and (LP)DDR4 Test Challenges

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1 行動裝置高速數位介面及儲存技術 克服 MIPI PHY UniPro UniPort-M UFS 與 (LP)DDR4 測試挑戰 Master the latest MIPI PHY UniPro UniPort-M UFS and (LP)DDR4 Test Challenges Dec Jacky Yu 1

2 Agenda 2 MIPI 實體層測試 C-PHY D-PHY M-PHY (LP)DDR4 測試及 DDR5 說明 DDR4 Testing DDR5 update

3 C-PHY Three Data Lane PHY Configuration C-PHY Master Data Lane Module C-PHY Master Data Lane Module C-PHY Master Data Lane Module C-PHY Slave Data Lane Module C-PHY Slave Data Lane Module C-PHY Slave Data Lane Module Data-rate completely agile, no discrete operating frequencies, continous range Embeddeded / encoded clocking RX testing is basically stressed eye testing (eye closure mainly due to ISI and DCD caused by A,B, C skew and Tr, Tf differences ) 3

4 C-PHY Spec 1.2 CTS 1.0 TX Eye diagram test, RX jitter test. Concern 1 C-PHY TX eye diagram test/ RX jitter test required to imply reference channel that needs 6 port S-parameter to test but none of scope can support 6 port s-parameter directly. Original measurement Adding reference channel TX eye diagram test Keysight has proposed to using 2 port S-Parameter as test reference channel for C-PHY. 4

5 C-PHY Spec 1.2 CTS 1.0 TX Eye diagram test, RX jitter test. Concern 2 Current CTS can not promise, TX eye diagram test result and RX jitter calibration method is same so that both test will be correlated between. Because oscilloscope can t make one eye diagram for 3 VAB, VBC, VCA waveforms, which will be required for RX jitter calibration. Which eye diagram to use RX jitter calibration? 5

6 C-PHY Spec 1.2 CTS 1.0 TX Eye diagram test, RX jitter test. Keysight will use/propose combined one eye diagram for eye mask test. 3 single VA,VB, VC Makes differential VAB, VBC, VCA Based on differential Signals generate clock Stich VAB, VBC, VCA As one long signal Also stich generated clock signal 6

7 Combined 3 waveforms to 1 eye diagram Test results Result show that eye shape is not same 7

8 Agenda 8 MIPI 實體層測試 C-PHY D-PHY M-PHY (LP)DDR4 測試及 DDR5 說明 DDR4 Testing DDR5 update

9 D-PHY specification 2.0 CTS1.0 Concern 1. Higher speed - TX RTB issue, current Reference termination Board is not fit to test over 1.5Gbps, due to LP to HS switching speed. 4.5Gbps signal measure from RTB, added STD channel 4.5Gbps original signal, added STD channel Unless UNH-IOL or other vendor provide new RTB, test result will be impacted by this limitation Start in consideration on direct connection or Active termination adopter, RTB will used for Global parameter test only 9

10 D-PHY CTS 2.0 consideration Concern 2. Eye diagram test - TX Eye diagram test will be performed after passing reference channel while applying TX EQ(de-emphasis), Keysight will provide reference channel as S-parameter model so do not need to change probing due to reference channel. 10

11 D-PHY CTS 2.0 consideration Concern 2. Eye diagram test - TX Do we need to consider moving eye diagram? D-PHY specification 1.2 support SKEW calibration, but Oscilloscope does not support this feature. So if there has inter skew between clock and data, eye mask can be violated due to inter skew which can be compensated by skew calibration in real environmental. CLK Inter skew Data Keysight will add to finding optimal Eye position within +/-0.2UI range 11

12 Agenda 12 MIPI 實體層測試 C-PHY D-PHY M-PHY (LP)DDR4 測試及 DDR5 說明 DDR4 Testing DDR5 update

13 M-PHY Physical Layer High Speed and Low Speed Modes High Speed NRZ (HS) and Lower Speed (LS) modes Common LS mode: Pulse Width Modulation (PWM) Always differential and 8b/10b coded High and low voltage swing operations Terminated (100 ohm) or not terminated operation 13

14 M-PHY 4.1 CTS consideration Concern 1, wrong spec M-PHY CTLE USB 3.1 Gen2 CTLE CTLE shape is looks like USB3.1 Gen2 CTLE but equation is totally different How we can get similar shape? 14

15 M-PHY 4.1 CTS consideration Concern 1, wrong spec M-PHY CTLE USB 3.1 Gen2 CTLE?? Okay, MIPI also has Vac. But where in equation? Equation has Vdc, Wpz, Wp1 and Wp2 as variable. Where is fp1? USB 3.1 Gen2 use Aac value to limiting boost effect(peaking) 15

16 MIPI Technology Industry Roadmap Q Q H H M-PHY M-PHY 4.0 M-PHY v 4.0 compliance D-PHY D-PHY 2.0 D-PHY 2.0 Pre compliance D-PHY v2.0 compliance D-PHY 1.2 CTS D-PHY 2.0 (M8085A) C-PHY C-PHY v1.0 compliance C-PHY 1.2 C-PHY v1.2 compliance C-PHY 1.2 (M8085A) Others I3C v0.8 I3C protocol Phase 1 I3C protocol Phase 2 SPMI 2.0 protocol C-PHY protocol *Roadmap based on fiscal quarters Industry spec drop Keysight scope solution (Tx) Keysight receiver solution (Rx) Keysight protocol solution (P) 16

17 Keysight MIPI Physical Testing solution MIPI All TX 9K/90K/90KX series scope S, V, Z series scope S, V, Z series scope M-PHY RX J-BERT N4903B J-BERT M8020A J-BERT M8020A C-PHY RX AWG M8190A AWG M8195A D-PHY RX ParBERT AWG M8190A AWG M8195A ~2013/ ~ 17

18 Agenda 18 MIPI 實體層測試 C-PHY D-PHY M-PHY (LP)DDR4 測試及 DDR5 說明 DDR4 Testing DDR5 update

19 Measuring The DDR4 Eye (tdivw and vdivw) DDR4 Measured Eye Diagram Use the smallest observed timing or voltage margin Test supported with N6462A DDR4 compliance app Clock Tests Electrical Timing Eye diagram DDR4 Speed grades: 1600, 1866, 2133, 2400, 2666, 3200 MT/s (as per JESD79-4) 19

20 Mask Voltage Position - Vcent LPDDR4 Vref is an internal signal not visible during system operation Vref can driven out DQ pins only when DRAM is in special test mode Vcent = estimate of the internal Vref derived from DQ eyes Vcent How to determine Vcent: 1. Find the widest part of the eye for each DQ 2. Select the highest and lowest eyes 3. Vcent = Midpoint (all DQ eyes) = Average(highest, lowest) Vcent necessary to enable in-system measurements 20

21 DDR4 / LPDDR4 Insight with a Logic Analyzer Connect Acquire View & Analyze DIMM SODIMM Interposers New Mid-Bus & specialty Probing Capture highest data rates! Address and command for DDR4 or LPDDR4 up to 5000 Mb/s Data up to 4000 Mb/s Capture smallest eyes! 100mV x 100ps at probe point. Sequential Triggers up to 2.5GHz or 4000 Mb/s! 12.5GHz Timing Zoom 256k deep Up to 400M deep traces Memory Analysis SW Listing with Decoders Traffic Overview Protocol Compliance across Speed changes Performance Analysis Waveforms New Bus Level Signal Integrity Insight U4164A Logic Analyzer Module B4661A Memory Analysis SW 21

22 Key User Requirements Addressed by new features of U4164A Maximum visibility of simultaneous R/W traffic capture for DDR4 and LPDDR4 U4164A has new comparator that enables single point probing, relaxing routing constraints and decreasing probe loading. Higher speed timing mode U4164A has new ¼ channel 10GHz timing mode with SW deskew. (2 x U4154B) Deeper captures U4164A has twice the memory depth option of U4154B, with 400M option 400M option in State modes and full channel Timing, 800M in half channel timing mode and 1.6G in ¼ channel timing mode. Continuous state mode capture through resets and clock off periods. U4164A has new clock hysteresis to improve state capture through clock tri-state events. 22

23 Agenda 23 MIPI 實體層測試 C-PHY D-PHY M-PHY (LP)DDR4 測試及 DDR5 說明 DDR4 Testing DDR5 update

24 What s new in DDR5 proposed spec? Source: Intel DDR5 Technical Review 1. Speed bin: up to 6.4GT/s 2. New Tx jitter specs (defined separately for DQ and DQS) 3. DFE for Data Buffer Testing requirements may add: 1. Jitter characterization on DRAM, Host and Buffer 2. Equalization for unmatched DQ/DQS at Receiver 3. More accurate simulation models to optimize system margin EZJIT Complete Jitter Decomposition Software 24

25 Questions? 25 Thank you!