DDR Verification Approaches. designinsight seminar
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1 DDR Verification Approaches designinsight seminar
2 DDR Test Challenges Signal Access & Probing Easy-to-use / reliable connections Bandwidth & Signal Integrity Affordable Isolation of Read/Write bursts Triggering or Post-Processing (ASM) Complexity of JEDEC Conformance Tests Vref / Vih / Vil Derating Results Validity / Statistics Effective Reporting / Archiving Advanced Analysis Characterization Debug 2 designinsight seminar
3 Challenge 1: Probing DDR Memory Computer Systems use standardized DIMM s for which several probing solutions are available Memory in Embedded Designs is usually directly mounted on the PCB All DDR2 & DDR3 Components use BGA Packages Probing a BGA package is Difficult Unable to probe at the Balls of the Device Signal Access Solutions Component Interposers Direct Probing Analog Probing DQ, DQS, Clock Digital Probing Address Command Power, Reset, and Reference Component Interposer Analog and Digital Probing 3 designinsight seminar *Courtesy Micron Technologies Direct Probing
4 Analog Solder-In Probing Solutions for DDR P7500 Series Tri-Mode Probes Socket Cable xx TriMode Micro-Coax Tip 4GHz P75TRLST Solder Tip up to 20GHz 4 designinsight seminar
5 Nexus DDR3 BGA Chip Interposers For Oscilloscopes Retention Socket BGA Chip Interposer 5 designinsight seminar
6 BGA Chip Access For DDR2, DDR3 Unique, reusable socket design allows for multiple chip exchanges Able to use both analog and digital probes Nexus DDR Interposers sold by Tektronix DDR2 and DDR3 versions X4/x8, x16 pins Socket and solder models (See MSR for details) 6 designinsight seminar
7 BGA Chip Interposer Signal Fidelity Filters are available to de-embed analog effects Library of filters is provided with the interposer Filters were developed based on the actual S-parameters of the interposer + probe tip Available for DPO/DSA/MSO70000 and DPO7000 scopes Eye - unfiltered Eye with filter 7 designinsight seminar
8 Challenge 2: Burst Identification Locate the right kind of bursts (read vs write) Locate the precise edges of each burst Refine burst identity based on other criteria (rank, secondary bus state, etc) DDR3 Read Burst DDR3 Write Burst 8 designinsight seminar
9 HW Triggering on DDR Reads / Writes Window Trigger - useful for real-time DDR read /write isolation DQS goes high for writes, low for reads (DDR3) 9 designinsight seminar
10 Advanced Search & Mark (ASM) and Long Records Easily identify & measure all Read / Write bursts in the acquisition Based on the Advanced Search & Mark feature Scroll through marked reads / writes across the entire waveform record 10 designinsight seminar
11 Burst Identification on an MSO Using bus state, specific transactions can be isolated For example, locate only Reads from a specific memory rank Advanced Search & Mark is used for fine burst positioning 11 designinsight seminar
12 Challenge 3: Measurement Setup JEDEC Standards specify measurements & methods 12 designinsight seminar
13 Ease of Use - DDRA Wizard Step #1 Select DDR Generation Select DDR Rate Step #2 13 designinsight seminar Choose measurements (Read / Write / CLK / Addr & Command)
14 Comprehensive Measurement Support Option DDRA supports a broad range of JEDEC-specified measurements for DDR, DDR2, DDR3, LP-DDR Example measurements list for DDR2 : tipw tis (base) tck(avg) tds - diff (base) tih (base) tck(abs) tds - SE (base) tis - DERATED tch(avg) tds -diff - DERATED tih - DERATED tch(abs) tds -SE - DERATED Vid - diff (AC) tcl(avg) tdh - diff (base) Vix (AC) - DQS tcl(abs) tdh - SE (base) Vix (AC) - CLK thp tdh -diff - DERATED Vox (AC) - DQS tjit(duty) tdh -SE - DERATED Vox (AC) - CLK tjit(per) tdipw Input Slew-Rise (DQS), tjit(cc) tac - diff terr(02) tdqsck -diff Input Slew-Fall (DQS), terr(03) tdqsck - SE Input Slew-Rise (CLK), terr(04) tdqsq - diff Input Slew-Fall (CLK), terr(05) tdqsq - SE AC - Overshoot Amplitude - diff terr( 6-10 per) tqh AC -Undershoot Amplitude - diff terr(11-50 per) tdqss AC - Overshoot Amplitude - SE tdqsh tdss AC - Undershoot Amplitude - SE tdsh Data Eye Width 14 designinsight seminar
15 Measurement De-rating JEDEC stipulates de-rating of DDR2 and DDR3 pass / fail limits for Setup & Hold measurements based on signal slew rate* Option DDRA automatically calculates slew rates and applies the appropriate de-rating values to the measurement limits. tds - diff (base) tds -diff - DERATED tds - SE (base) tds -SE - DERATED tdh - diff (base) tdh -diff - DERATED tdh - SE (base) tdh -SE - DERATED tis (base) tis - DERATED tih (base) tih - DERATED 15 designinsight seminar * JESD79-2E, JESD79-3C specifications
16 Challenge 4: Results and Statistical Validity To have confidence in your test results, you need 100 s, 1000 s or even more observations of each measurement As a practical matter, measurement throughput is essential 16 designinsight seminar
17 Challenge 5: Reporting and Archiving HTML Reports Source Waveforms 17 designinsight seminar
18 Challenge 6: Advanced Analysis and Debug DDRA has access to all plotting & debug tools in DPOJET 18 designinsight seminar
19 DDR Analog Validation & Debug Tektronix Solutions Signal Access - Probing P7500 TriMode Probing Single probe for diff, CM and single-ended measurements Up to 20 GHz bandwidth to the probe tip P6780 Logic Probe 16 channel Active Differential probe with 2.5 GHz bandwidth Socketed BGA interposers for multiple exchanges Signal Acquisition Automatically trigger and capture DDR signals Identify and trigger directly on DQ, DQS in real-time to isolate Reads/Writes Command Bus triggering with user-defined decode files Capture long time duration at high resolution Direct connection to DPOJET for signal analysis Time trend view for analysis of low frequency effects Signal Analysis DDRA Automated setup, read/write burst detection, JEDEC pass/fail meas. DPOJET The most powerful Jitter, Eye and Timing analysis tool Time, Amplitude, Histogram, measurements Advanced Jitter, Eye diagram measurements and Pass/Fail testing Many display and plotting options Report generator 19 designinsight seminar
20 Resources Tektronix Knowledge Center: DDR Application Note: 20 designinsight seminar
Jerry Chu 2010/08/23 Vincent Chang 2010/08/23
Product Model Name: AD1U400A1G3 Product Specification: DDR-400(CL3) 184-Pin U-DIMM 1GB (128M x 64-bits) Issuing Date: 2010/08/23 Version: 0 Item: 1. General Description 2. Features 3. Pin Assignment 4.
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REV /2003 NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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