HY5DV Banks x 1M x 16Bit DOUBLE DATA RATE SDRAM
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1 4 Banks x M x 6Bit DOUBLE DATA RATE SDRAM PRELIMINARY DESCRIPTION The Hyundai is a 67,08,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point to point applications which require high bandwidth. is organized as 4 banks of,048,576x6. offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data strobes(ldqs/udqs) and Write data masks(ldm/udm) inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. Mode Register Set options include the length of pipeline (CAS latency of 2.0 / 2.5 / 3.0), the number of consecutive read or write cycles initiated by a single control command (Burst length of 2 / 4 / 8), and the burst count sequence(sequential or interleave). Because data rate is doubled through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous DRAM. FEATURES 3.3V for VDD and 2.5V for power supplies All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock operations(clk & CLK) All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ), Data strobes(ldqs/udqs) and Write masks(ldm/udm) latched on both rising and falling edges of the clock Data outputs on LDQS/UDQS edges when read (edged DQ) Data inputs on LDQS/UDQS centers when write (centered DQ) Data strobes synchronized with output data for read and input data for write Delay Locked Loop(DLL) installed with DLL reset mode Write mask byte controls by LDM and UDM Programmable CAS Latency 2.0 / 2.5 / 3.0 Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 4096 refresh cycles / 64ms ORDERING INFORMATION Part No. Power Supply Clock Frequency Organization Interface Package TC-G6 66MHz TC-G7 TC-7 TC-75 VDD=3.3V =2.5V 43MHz 33MHz(*PC266A) 25MHz(*PC266B) 4Banks x Mbit x6 SSTL_2 400mil 66pin TSOP II TC-8 00MHz(*PC200) * JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.8/ Oct.99
2 PIN CONFIGURATION VDD DQ0 DQ DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS VDD LDM /WE /CAS /RAS /CS BA0 BA A0/AP A0 A A2 A3 VDD TOP VIEW 400mil X 875mil 66 Pin TSOP-II 0.65mm Pin Pitch VSS DQ5 DQ4 DQ3 DQ2 DQ DQ0 DQ9 DQ8 UDQS VREF VSS UDM /CLK CLK CKE A A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTION PIN PIN NAME DESCRIPTION CLK, CLK CKE CS BA0, BA A0 ~ A RAS, CAS, WE Differential Clock Input Clock Enable Chip Select Bank Select Address Address Row Address Strobe, Column Address Strobe, Write Enable The system clock input. All of the inputs are latched on the rising edges of the clock except DQi, LDQS/UDQS and LDM/UDM that are sampled on the both. Controls internal clock signal and when deactivated, the DDR SDRAM will be one of the states among power down, suspend or self refresh. Enables or disables all inputs except CLK/CLK, CKE, LDQS/UDQS and LDM/UDM. Selects bank to be activated during either RAS or CAS activity. Selects bank to be read/written during either RAS or CAS activity. Row Address : A0 ~ A, Column Address : A0 ~ A7 Auto-precharge flag : A0 RAS, CAS and WE define the operations. Refer function truth table for details. LDM, UDM Write Mask Masks input data in write mode. LDQS, UDQS Data Input/Output Strobe Active on the both edges for Data Input and Output. DQ0 ~ DQ5 Data Input/Output Multiplexed data input / output pin. VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers. / Data Output Power/Ground Power supply for output buffers for Noise immunity. VREF Reference Voltage Reference voltage for inputs for SSTL interface. No Connection No connection. Rev. 0.8/ Oct.99 2
3 FUTIONAL BLOCK DIAGRAM 4banks x Mbit x 6 I/O Double data rate Synchronous DRAM CLK /CLK CKE /CS /RAS /CAS /WE DM Command Decoder Mode Register Bank Control Row Decoder Write Data Register 2-bit Prefetch Unit 32 Mx6/Bank0 Mx6/Bank Mx6/Bank2 Mx6/Bank3 Sense AMP 6 2-bit Prefetch Unit 32 6 Input Buffer Output Buffer DS DQ[0:5] Column Decoder DQS ADD Address Buffer Column Address Counter CLK_DLL Data Strobe Transmitter DS Data Strobe Receiver CLK DLL Block Mode Register Rev. 0.8/ Oct.99 3
4 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 C Storage Temperature TSTG -55 ~ 25 C Voltage on Any Pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD relative to VSS VDD -.0 ~ 4.6 V Voltage on relative to VSS -0.5 ~ 3.6 V Output Short Circuit Current IOS 50 ma Power Dissipation PD W Soldering Temperature Time TSOLDER C Sec Operation at above absolute maximum rating can adversely affect device reliability. DC OPERATING CONDITIONS (TA=0 to 70 C, Voltage referenced to VSS = 0V) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage VDD V Power Supply Voltage V Input High Voltage VIH VREF V Input Low Voltage VIL VREF V 2 Termination Voltage VTT VREF VREF VREF V Reference Voltage VREF V 3. must not exceed the level of VDD. 2. VIL (min) is acceptable -.5V AC pulse width with 5ns of duration. 3. The value of VREF is approximately equal to 0.5. AC OPERATING TEST CONDITIONS (TA=0 to 70 C, Voltage referenced to VSS = 0V) Parameter Value Unit Reference Voltage x 0.5 V Termination Voltage x 0.5 V AC Input High Level Voltage (VIH, min) VREF V AC Input Low Level Voltage (VIL, max) VREF V Input Timing Measurement Reference Level Voltage VREF V Output Timing Measurement Reference Level Voltage VTT V Rev. 0.8/ Oct.99 4
5 AC OPERATING TEST CONDITIONS (TA=0 to 70 C, Voltage referenced to VSS = 0V) - continued - Parameter Value Unit Input Signal maximum peak swing.5 V Input minimum Signal Slew Rate V/ns Termination Resistor (RT) 50 Ω Series Resistor (RS) 25 Ω Output Load Capacitance for Access Time Measurement (CL) 30/5 *Note pf * -G6/-G7 for 5pF, and -7/-75/-8 for 30pF Test Load CAPACITAE (TA=25 C, f=mhz) Parameter Pin Symbol Min Max Unit Input Capacitance A0 ~ A, BA0 ~ BA, CKE, CS, RAS, CAS, WE CIN pf Clock Capacitance CLK, CLK CCLK pf Data Input / Output Capacitance DQ0 ~ DQ5, LDQS, UDQS, LDM, UDM CIO pf OUTPUT LOAD CIRCUIT VTT VTT RT=50Ω RT=50Ω Output RS=25Ω Zo=50Ω VREF CL=5 / 30pF * -6/-7 for 5pF, and -75/-8/-0 for 30pF Test Load Rev. 0.8/ Oct.99 5
6 DC CHARACTERISTICS I (TA=0 to 70 C, Voltage referenced to VSS = 0V) Parameter Symbol Min. Max Unit Note Input Leakage Current ILI -5 5 µa Output Leakage Current ILO -5 5 µa 2 Output High Voltage VOH VTT V IOH = -5.2mA Output Low Voltage VOL - VTT V IOL = +5.2mA.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 2.7V DC CHARACTERISTICS II (TA=0 to 70 C, Voltage referenced to VSS = 0V) Parameter Symbol Test Condition Speed -G6 -G Unit Note Operating Current IDD Burst length=2, One bank active trc trc(min), IOL=0mA ma Precharge Standby Current in Power Down Mode IDD2P CKE VIL(max), tck = min 20 ma Precharge Standby Current in Non Power Down Mode IDD2N CKE VIH(min), CS VIH(min), tck = min Input signals are changed one time during 2clks 40 ma Active Standby Current in Power Down Mode IDD3P CKE VIL(max), tck = min 25 ma Active Standby Current in Non Power Down Mode IDD3N CKE VIH(min), CS VIH(min), tck = min Input signals are changed one time during 2clks 50 ma CL= Burst Mode Operating Current IDD4 tck tck(min), IOL=0mA All banks active CL= ma CL= Auto Refresh Current IDD5 trc trfc(min), All banks active 200 ma 2 Self Refresh Current IDD6 CKE 0.2V 2 ma. IDD and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of trfc (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS. Rev. 0.8/ Oct.99 6
7 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol -G6 -G7-7(PC266A) -75(PC266B) -8(PC200) Min Max Min Max Min Max Min Max Min Max Unit Note Row Cycle Time trc ns Auto Refresh Row Cycle Time trfc ns Row Active Time tras 42 20K 42 20K 45 20K 48 20K 50 20K ns Row Address to Column Address Delay trcd ns Row Prechage Time trp ns Row Active to Row Active Delay trrd ns Column Address to Column Address Delay tccd CLK Write Recovery Time twr ns Last Data-In to Read Command delay tdrl CLK Auto Precharge Write Recovery + Precharge Time tdal ns CAS Latency = ns System Clock Cycle Time CAS Latency = 2.5 tck ns CAS Latency = ns Clock High Level Width tch CLK Clock Low Level Width tcl CLK DQS-Out edge to Clock edge skew tdqsck ns Data-Out edge to Clock edge skew tac ns DQS-Out edge to Data-Out edge skew tdqsq ns Data/DQS-Out Valid Window tdv CLK DQS-Out Preamble Time trpre CLK DQS-Out Postamble Time trpst CLK CLK to first rising edge of DQS-In tdqss CLK DQS-In Preamble Setup Time twpres CLK DQS-In Preamble Hold Time twpreh CLK DQS-In Last falling edge to Hi-Z Delay twpst CLK DQS-In High Level Width tdsh CLK DQS-In Low Level Width tdsl CLK Input Setup Time to CLK (ADDR & Control) tis ns Input Hold Time to CLK (ADDR & Control) tih ns Data-In Setup Time to DQS-In (DQ & DM) tds ns 2 Data-In Hold Time to DQS-In (DQ & DM) tdh ns 2 DQS-In Pulse Width tdipw ns Mode register Set Cycle Time tmrd CLK Power Down Exit Time tpdex ns Exit Self Refresh to Non-Read Command txsnr ns Exit Self Refresh to Read command txsrd CLK Average Periodic Refresh Interval trefi us. Data sampled at the rising edges of the clock : A0~A, BA0~BA, CKE, CS, RAS, CAS, WE. 2. Data letched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM. 3. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Rev. 0.8/ Oct.99 7
8 SIMPLIFIED COMMAND TRUTH TABLE Command CKEn- CKEn CS RAS CAS WE ADDR A0/ AP BA Note Extended Mode Register Set H X L L L L OP code,2 Mode Register Set H X L L L L OP code,2 Device Deselect H X X X H X No Operation L H H H X Bank Active H X L L H H RA V Read L H X L H L H CA V Read with Autoprecharge H,3 Write L H X L H L L CA V Write with Autoprecharge H,4 Precharge All Banks H X,5 H X L L H L X Precharge selected Bank L V Read Burst Stop H X L H H L X Auto Refresh H H L L L H X Entry H L L L L H Self Refresh Exit L H H X X X L H H H X Precharge Power Down Mode Entry H L Exit L H H X X X L H H H X H X X X L H H H Active Power Down Mode (Clock Suspend) Entry H L H X X X L V V V X Exit L H X ( H=Logic High Level, L=Logic Low Level, X=Don t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ). LDM/UDM states are Don t Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A and BA0~BA used for Mode Registering duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after trp period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CLK(n), then there will be no command presented to activated bank until CLK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory compoment in CLK(n), then there will be no command presented to activated bank until CLK(n+BL/2++tDPL+tRP). Last Data-In to Prechage delay(tdpl) which is also called Write Recovery Time (twr) is needed to guarantee that the last data has been completely written. 5. If A0/AP is High when Row Precharge command being issued, BA 0/BA are ignored and all banks are selected to be precharged. Rev. 0.8/ Oct.99 8
9 WRITE MASK TRUTH TABLE Function CKEn- CKEn CS, RAS, CAS, WE LDM UDM ADDR A0/ AP BA Note Data Write H X X L L X,2 Data-In Mask H X X H H X,2 Lower Byte Write / Upper Byte-In Mask Upper Byte Write / Lower Byte-In Mask H X X L H X,2 H X X H L X,2 ( H=Logic High Level, L=Logic Low Level, X=Don t Care ). Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. 2. In case of x6 data I/O, LDM and UDM control lower byte(dq0~7) and Upper byte(dq8~5) respectively. PACKAGE INFORMATION 400mil 66pin Thin Small Outline Package Unit : mm(inch) BASE PLANE.94 (0.470).79 (0.462) 0.26 (0.404) 0.05 (0.396) (0.879) 22.2 (0.87) 0 ~ 5 Deg (0.0256) BSC 0.35 (0.038) 0.25 (0.0098) SEATING PLANE.94 (0.0470) 0.99 (0.0390) 0.5 (0.0059) 0.05 (0.0020) (0.0235) (0.060) 0.20 (0.0083) 0.20 (0.0047) Rev. 0.8/ Oct.99 9
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