Product Specifications

Transcription

1 Product Specificatio M383L2923E-CC L383L2923E-CC RE: General Information 1GB 128MX72 DDR SDRAM REGISTERED 18 PIN DIMM ECC Description: The M/L383L2923E is a 128M X 72 Double Data Rate SDRAM high deity registered DIMM. This memory module coists of 18 CMOS Mx8 bit with banks DDR Synchronous DRAMs in TSOP-II 00 mil packages, 2-1 bit Registered buffers in TSSOP package, a zero delay PLL clock in TSSOP package, and a 2K EEPROM in 8-pin TSSOP package. This module is a 18-pin Dual-In line-memory Module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR SDRAM. Features:. DD: +/- 1, : +/- 1. DDSPD = 3 to 3.. I/O (STTL_2 compatible). Supports ECC error detection and correction. Two data trafers per clock cycle. Birdirectional data strobe (DQS). Differential clock inputs ( and #). DLL alig DQ and DOS traition with traition. Programmable Read latency: DDR00(3 clock). Programmable Burst ; length (2,, 8). Progammable Burst (sequential & Interleave). Auto & Self refresh, 7.8us refresh interval (8K/ms refresh). Serial presence detect with EEPROM. PCB: Height 1125 (mil),double sided component. Gold edge contacts. Leaded & Lead-Free/RoHS compliant A0-A12 BA0,BA1 DQ0-DQ3 Function Address inputs Bank Selct Address Data /Outpu t C B0 ~ CB7 Check bit (Data-in/data-out ) DQS0-DQS8 0,0# E0,E1 CS0#, CS1# RAS# CAS# WE# DM0-DM8 Data Strobe /Outpu t Clock Inpu t Clock Enable Inpu t Chip Select Inpu t Row Address Strobe Column Addres Inpu t Write Enable Data Mask DD Power Supply () DDQ Power supply for DQS () REF Gound Power Supply for Referenc e Order Information: M383L2923E-CC X X DRAM DIE (Option) DRAM MANUFACTURER S - SAMSUNG M - MICRON MODULE SPEED CC: CL3 DDSPD SPD Power Supply (3-3. ) SDA SCL SA0-SA2 RESET# Serial Data /Outpu t SPD Clock Inpu t SPD Address Reset enable No Connectio n M : Leaded L : Lead-free/RoHS irtium Technology, Inc Tomas, Rancho Santa Margarita, CA 9288 PAGE 1 OF 8

2 Product Specificatio M383L2923E-CC L383L2923E-CC RE: Configuration 18-PIN DDR DIMM FRONT 18-PIN DDR DIMM BA 1 REF 2 DQ17 7 DQS8 70 DD DQ7 2 DQ0 25 DQS2 8 A DQ 117 DQ21 10 DM CB2 72 DQ8 95 DQ5 118 A11 11 A10 1 DQ1 27 A DQ DM2 12 CB DQ52 5 DQS0 28 DQ18 51 CB DM0 120 DD 13 1 DQ53 DQ2 29 A7 52 BA1 75 2# * 98 DQ 121 DQ22 1 CB7 17 A13* 7 DD DQ32 7 2* 99 DQ7 122 A8 18 DD 8 DQ3 31 DQ DQ23 1 DQ3 19 DM 9 32 A5 55 DQ33 78 DQS DQ DQ5 10 RESET# 33 DQ2 5 DQS 79 DQ A 18 DD 171 DQ vss 57 DQ3 80 DQ DQ28 19 DM DQ8 35 DQ DQ29 0 DQ DQ9 3 DQS3 59 BA DQ DQ39 17 DQ0 1 DQS1 37 A 0 DQ35 83 DQ5 10 DQ DM DQ1 38 DD 1 DQ0 8 DQ DM1 130 A3 3 DQ * 39 DQ DD 108 DD 131 DQ30 RAS# 177 DM7 17 1# * 0 DQ27 3 WE# 8 DQS7 109 DQ DQ5 178 DQ A2 DQ1 87 DQ DQ 133 DQ DQ3 19 DQ CAS# 88 DQ E1 13 CB 7 CS0# DQ11 3 A CB5 8 CS1# 181 SA0 21 E0 CB0 7 DQS DM5 182 SA CB1 8 DQ2 91 SDA 11 DQ SA2 23 DQ1 DD 9 DQ3 92 SCL 1 A # 11 DQ 18 DD- SPD Note: *: These pi are not used on this module. irtium Technology, Inc Tomas, Rancho Santa Margarita, CA 9288 PAGE 2 OF 8

3 Functional Block Diagram Product Specificatio M383L2923E-CC L383L2923E-CC RE: D0 D9 D D13 D1 D10 D5 D1 D2 D11 D D D3 D12 D7 D1 D8 D17 irtium Technology, Inc Tomas, Rancho Santa Margarita, CA 9288 PAGE 3 OF 8

4 Product Specificatio M383L2923E-CC L383L2923E-CC RE: Absolute Maximum Ratings alue oltage oltage on any pin relative to on DD & D DQ SS supply relative to SS IN, OUT 5 ~ 3. DD, 1 ~ Storage temperature T TG S 55 ~ +0-0 C Operating temperature TA 0 ~ 70 0 C Power Dissipation PD 18 W Short circuit output current IOS 50 Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposing to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Conditio 0 TA = 0 C to 70 0 C Min Max Note Supply voltage DDR00 ( nominal DD = ) DD 5 7 I/O Supply voltage DDR00 ( nominal DD = ) 5 7 I/O Reference voltage REF 9 * 51 * 1 I/O Termination voltage logic high voltage logic low voltage voltage level, and # differential voltage, and # crossing point voltage, and # Addr, CAS#,RAS#,WE# TT REF-0 REF+ 0 2 H I ( DC) REF L I ( DC) - 3 REF- N I ( DC) D I ( DC) X I ( DC) ua leakage current CS#, E -5 5 ua II, # ua DM - ua Output leakage current Output high current(normal strength) OUT = v + 8 Output high current(normal strength) OUT = TT - 8 Output high current(half strength) OUT = TT + 5 Output high current(half strength) OUT = TT - 5 IOZ ua IOH IOL IOH -9 - IOL 9 - Notes: 1. REF is expected to be equal to 5* of the tramitting device, Peak to peak noise on REF may not excedd +/- 2% of the DC value. T T is not applied directly to the device. TT is a system supply for signal REF, and must track variatio in the DC level ofr EF. 3. D I is the magnitude of the difference between the input level on and the input level of #. and to track variatio in the DC level of the same. termination resistors, is expected to be set equal to irtium Technology, Inc Tomas, Rancho Santa Margarita, CA 9288 PAGE OF 8

5 Product Specificatio M383L2923E-CC L383L2923E-CC RE: AC Operating Conditio Min Max p ut High (Logic1) oltage IH(AC ) REF+31 In p ut Low (Logic0) oltage IL(AC ) REF-31 In I nput Differential oltage, and # inputs ID(AC ) 7 + I nput Crossing Point oltage, and # input IX(AC ) 5*- 2 5*+ 2 /Output Capacitance 0 TA=25 C, f=100mhz Min Max capacitance (A0~A12, BA0~BA1,RAS#,CAS#,WE#) CIN capacitance (E0,E1) CIN capacitance (CS0#,CS1#) CIN capacitance (0,0#) CIN capacitance (DM0 ~ DM8), (DQS0 ~ DQS8) CIN capacitance (DQ0 ~ DQ3), (CB0 ~ CB7) COUT irtium Technology, Inc Tomas, Rancho Santa Margarita, CA 9288 PAGE 5 OF 8

6 Product Specificatio M383L2923E-CC L383L2923E-CC RE: IDD Specification Condition -CC OPERATING CURRENT: One device bank active; Active-Precharge; t t = t ; DQ,DM and DQS inputs change once per clock cycle; Address and control inputs change once every two clock cycles = t ; RC R C(MIN ) OPERATING CURRENT: One device bank; Active-Read-Precharge; BL=; t RC = t ; t = t ; I =0; Address and control inputs change once per RC(MIN ) (MIN ) OUT cycle clock IDD0* 105 IDD1* 1875 PRECHARGE POWER-DOWN STANDBY CURRENT: Power-down mode; t t E=LOW = (MIN) ; All device banks are idle; IDLE STANDBY CURRENT: CS#=HIGH; All device banks are idle; t = t (MIN) ; E=HIGH; Address and other control inputs changing once per clock cycle. for DQ,DQS and DM IN = REF ACITE POWER-DOWN STANDBY CURRENT: down mode; t = t ; E=LOW One device bank active; Power- ACTIE STANDBY CURRENT: CS#=HIGH; E=HIGH; One device bank active; t RC = t ; t = t ; DQ,DM and DQS inputs change twice per clock cycle; RAS(MAX) Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continnuous burst; One device bank active; Address and other control inputs changing once per clock cycle; t t I =0 OUT = ; OPERATING CURRENT: Burst = 2; Writes; Continnuous burst; One device bank active; Address and other control inputs changing once per clock cycle; t t DQ,DM and DQS inputs change twice per clock cycle = ; IDD2P** 570 IDD2F** 1020 IDD3P** 1290 IDD3N** 0 IDDR* 1920 IDDW* 2100 AUTO REFRESH CURRENT: T = T DD5* * RC R FC(MIN ) I 0 S ELF-REFRESH CURRENT: E< 0.2 IDD* * 90 OPERATING CURRENT: Four device bank interleaving Reads Burst= with auto precharge; t = t ; t = t ; Address and control inputs change only during RC RC(MIN ) (MIN ) Active READ, or WRITE commands IDD7* 3990 Note: IDD specification is based on Samsung components. Other DRAM Manufacturers specification may be different. *: alue calculated as one module rank in this operation condition, and other module rank in IDD2P (E LOW) mode. **: alue calculated as all module ranks in this operation condition. irtium Technology, Inc Tomas, Rancho Santa Margarita, CA 9288 PAGE OF 8

7 Product Specificatio M383L2923E-CC L383L2923E-CC RE: AC Timming s & Specificatio Min -CC Max Row Cycle Time Refresh row cycle time Row active RAS# to CAS# delay Row precharge time Row active to row active delay Write recovery time Last data in to READ command trc 55 trfc 70 ps tras 0 70K ps trcd trp trrd 10 twr twtr 2 CL=2 - - Clock cycle time CL=5 - - CL= Clock high level width Clock low level width DQS-out access time from /# Output data access time from /# Data strobe edge to output data edge Read preamble Read postamble to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to rising-setup time DQS falling edge to rising-hold time DQS-in high level width DQS-in low level width Address and control input setup time (fast) Address and control input hold time (fast) Address and control input setup (slow) Address and control input hold time (slow) Data-out high impedance time from /# Data-out low impedance time from /# Mode regigster set cycle DQ & DM setup time to DQS DQ & DM hold time to DQS Control & address input pulse width DQ & DM input pulse width Exit self refresh to non-read command Exit self refresh to Read command Refresh interval time tch 5 55 tcl 5 55 tdqs tac tdqsq - trpre trpst tdqss twpres 0 twpre 25 tdss 2 tdsh 2 tdqsh 35 TDQSL 35 tisf tihf tiss 7 tihs 7 thz + 5 tlz -5 tmrd 2 tds tdh tip W 2 tdip W 1.75 txsnr 75 txsrd 200 trefi 7. 8 us Output DQS valid window Clock half period tqh thp thp -tqhs - tclmin or tchmin - Data hold skew factor DQS write postamble Active Read with auto precharge command tqhs 5 twpst trap Auto precharge Write recovery + Precharge time tdal twr/ + trp/ irtium Technology, Inc Tomas, Rancho Santa Margarita, CA 9288 PAGE 7 OF 8

8 Product Specificatio M383L2923E-CC L383L2923E-CC RE: Package Dimeio 0.11(.10) (X) (3.90) FRONT IEW 5.25 (133.50) 5.2 (133.20) (128.95) TYP (50) D (2X) 700 (17.80) (28.73) (28.2) 091 (30) 091 (30) PIN (1.27) 039 (0) 250 (.35) PIN (1.37) 0 (1.17).750 (125) BA IEW 071 (1.80) PIN 18 PIN 93 TYP 0 (3.80) 1.95 (9.53) 55 (.77) 39 (100) NOTE: All dimeio in inches (millimeters); MAX MIN or typical where noted. irtium Technology, Inc Tomas, Rancho Santa Margarita, CA 9288 PAGE 8 OF 8