Product Specifications

Transcription

1 Product Specificatio.5 General Information 5MB 6Mx6 SDRAM PC/PC UNBUFFERED 68 PIN DIMM Description: The L66S655 is a 6M x 6 Synchronous Dynamic RAM high deity memory module. This memory module coists of 6 CMOS Mx8 bits with banks Synchronous DRAMs in TSOP-II mil packages and a K EEPROM in 8-pin TSSOP package. This module is a 68-pin Dual In-line Memory Module and is intended for mounting into connector sockets. Decoupling capacitors are mounted on the printed circuit board for each SDRAM. Features: Unbuffered 8 byte SDRAM 68pin DIMM High Speed - MHz, MHz, CL, CL Burst Mode Operation Auto & Self refresh Capability (89 Cycles/6ms) LTTL compatible inputs and outputs Single. ±. power supply // Addressing (Row/Column/Bank) MRS cycle with address key programs EPROM Serial Presence Detect Gold (Au) contacts Lead-free/RoHS compliant PCB height: 5 (mil), single sided component Pin A-A BA, BA Name DQ-DQ6 CLK, CLK, CLK, CLK CKE, CKE CS#~CS# RAS# CAS# WE# -7 Function Address inputs Bank Select Address Data /Outpu t Clock Inpu t Clock Enable Inpu t Chip Select Inpu t Row Address Strobe Column Address Inpu t Write Enable Data input/output mask DD Power Supply (.) SS Ground * REF Power Supply for Referenc e Order Information: SDA SCL SA~SA Serial Data /Outpu t SPD Clock Inpu t Address in EEPROM L66S655-GA S X DRAM DIE (Option) DRAM MANUFACTURER S -SAMSUNG NC No Connect * These pi are not used in this module. MODULE SPEED GA: CL GH: CL GL: CL L: Lead-free/RoHS PAGE OF 8

2 Product Specificatio.5 Pin Configuration Pin Front Number Side SS DQ DQ DQ 5 DQ 6 DD 7 DQ 8 DQ5 9 DQ6 DQ7 DQ8 SS DQ9 DQ 5 DQ 6 DQ 7 DQ 8 DD 9 DQ DQ5 NC NC SS NC 5 NC 6 DD 7 WE# 8 9 CS# NC SS A A 5 A 6 A6 7 A8 8 A/AP 9 BA DD DD CLK Pin Front Number Side SS NC 5 CS# NC 9 DD 5 NC 5 NC 5 NC 5 NC 5 SS 55 DQ6 56 DQ7 57 DQ8 58 DQ9 59 DD 6 DQ 6 NC 6 NC 6 CKE 6 SS 65 DQ 66 DQ 67 DQ 68 SS 69 DQ 7 DQ5 7 DQ6 7 DQ7 7 DD 7 DQ8 75 DQ9 76 DQ 77 DQ 78 SS 79 CLK 8 NC 8 WP 8 SDA 8 SCL 8 DD Pin Back Number Side 85 SS 86 DQ 87 DQ 88 DQ 89 DQ5 9 DD 9 DQ6 9 DQ7 9 DQ8 9 DQ9 95 DQ 96 SS 97 DQ 98 DQ 99 DQ DQ DQ5 DD DQ6 DQ7 5 NC 6 NC 7 SS 8 NC 9 NC DD CAS# 5 CS# 5 RAS# 6 SS 7 A 8 A 9 A5 A7 A9 BA A DD 5 CLK 6 A Pin Back Number Side 7 SS 8 CKE 9 CS# 6 7 NC DD NC 5 NC 6 NC 7 NC 8 SS 9 DQ8 DQ9 DQ5 DQ5 DD DQ5 5 NC 6 NC 7 NC 8 SS 9 DQ5 5 DQ5 5 DQ55 5 SS 5 DQ56 5 DQ57 55 DQ58 56 DQ59 57 DD 58 DQ6 59 DQ6 6 DQ6 6 DQ6 6 SS 6 CLK 6 NC 65 SA 66 SA 67 SA 68 DD PAGE OF 8

3 Product Specificatio.5 Functional Block Diagram CS# CS# DQ DQ DQ DQ DQ DQ5 DQ6 DQ7 DQ8 DQ9 DQ DQ DQ DQ DQ DQ5 U U U8 U9 DQ DQ DQ DQ5 DQ6 DQ7 DQ8 DQ9 5 DQ DQ DQ DQ DQ DQ5 DQ6 DQ7 U U5 U U CS# CS# 6 DQ6 DQ7 DQ8 DQ9 DQ DQ DQ DQ DQ DQ5 DQ6 DQ7 DQ8 DQ9 DQ DQ U U U U DQ8 DQ9 DQ5 DQ5 DQ5 DQ5 DQ5 DQ55 7 DQ56 DQ57 DQ58 DQ59 DQ6 DQ6 DQ6 DQ6 U6 U7 U U5 A ~ A, BA & RAS# SDRAM U ~ U5 SDRAM U ~ U5 DD SCL Serial PD A A A SDA WP CAS# WE# SDRAM U ~ U5 SDRAM U ~ U5 K SA SA SA 7K DD ss CKE DQn ohm SDRAM U ~ U7 Two.uF Capacitors per each SDRAM CKE Every DQpin of SDRAM To all SDRAMs SDRAM U8 ~ U5 CLK CLK ohm. ohm U U U8 U U U5 U9 CLK CLK ohm. ohm U U6 U U U U7 U. U. U5 PAGE OF 8

4 Product Specificatio.5 Absolute imum Ratings alue oltage on any pin relative to ss oltage on DD s upply relative to ss N I, OUT -. ~. 6 DD, DDQ -. ~. 6 Storage temperature TSTG -55 ~ +5 C Power dissipation PD 6 W Short circuit current IOS 5 Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Recommended DC Operating Conditio ( TA = C to +7 C) Typ Note Supply voltage DD, DDQ... 6 high voltage low voltage high voltage low voltage leakage current (s) leakage current (I/O pi) H I.. DDQ+. L I OH. - - IOH = - OL - -. IOL = IL I - - ua IL I - - ua, Notes:. I H (max) = 5.6 AC. The overshoot voltage duration is <=.. I L (min) =. AC. The undershoot voltage duration is <=.. Any input <= IN < = DDQ..DOUT is desabled, <= OUT < = DDQ. Capacitance ( TA = 5 C, f = MHz, D D =.) capacitance (A ~ A, BA ~ BA) CIN 8 capacitance (RAS#, CAS#, WE#) CIN 8 capacitance (CKE, CKE) CIN 5 6 capacitance (CLK ~ CLK) CIN 5 capacitance (CS# ~ CS#) CIN5 5 5 capacitance ( ~ 7) CIN6 5 Data input/output capacitance (DQ ~ DQ6) COUT 5 PAGE OF 8

5 Product Specificatio.5 DC Characteristics ( Recommended operation condition unless otherwise noted, TA = C to +7 C) Test Condion ersion -GA -GH -GL Note Operating current (One bank active) C Burst length = trc > = tr C(min) IOL = Precharge standby current power-down mode in CP CKE <= IL( max), tcc = CPS CKE & CLK <= I L( max), tcc = Precharge standby current non power-down mode in CN CNS CKE >= IH ( min), >= IH ( min), tcc = signals are changed one time during CKE >= IH( min), CLK <= I L( max), tcc = oo signals are stable 6 Active standby current in power- down mode CP CKE <= IL( max), tcc = 96 CPS CKE & CLK <= I L( max), tcc = 96 Active standby current power-down mode (One bank active) in non CN CNS CKE >= IH( min), >= IH(min), tcc = signals are changed one time during CKE >= IH( min), CLK <= I L ( max), tcc = signals are stable 8 Operating current (Burst mode) C IOL = Page burst Banks actived tccd = CLKs Refresh current C5 Self refresh current C6 trc > = tr C( min) CKE <=. 8 Note:. Measured with outputs open..refresh period is 6ms. PAGE 5 OF 8

6 Product Specificatio.5 AC Operating Test Conditio ( DD =., TA = C to +7 C) alue AC input levels (IH/ I L)./. timing measurement reference level. rise and fall time tr/tf = / timing measurement reference level. load condition See Fig.. tt!=!. 5 OH (DC)!=!.,!IOH!=!- OL!(DC)!=!.,!IOL!=! Z!=! (Fig.!)!DC!output!load!circuit! (Fig.!)!AC!output!load!circuit! Operating AC ersion -GA -GH -GL Note Row active to row active delay tr RD( min) 5 RAS# to CAS# delay tr CD( min) Row precharge time Row active time Row cycle time tr P( min) tr AS( min) tr AS( max) us tr C( min) Last data in to row precharge tr DL( min) CLK Last data in to Active delay td AL( min) CLK + trp - Last data in to new col. addrees delay tc DL( min) CLK Last data in to burst stop tb DL( min) CLK Col. address to col. address delay tc CD( min) CLK Number of valid output data CAS Latency = CLK CAS Latency = ea Notes:. The minimum number of clock cycles is determined and then rounding off to the next higher integer.. imum delay is required to complete write.. All parts allow every cycle column address change.. In case of row precharge interrupt, auto precharge and by dividing the minimum time required with clock cycle time read burst stop. PAGE 6 OF 8

7 Product Specificatio.5 Operating AC -GA -GH -GL Note CLK cycle time CAS latency = tcc CAS latency = - - CLK to valid output delay CAS latency = tsac CAS latency = - 6 -, data hold time CAS latency = toh - CAS latency = - - CLK high pulse width CLK low pulse width setup time hold time tch. 5 tcl. 5 tss. 5 tsh. 8 CLK to output in Low-Z tslz CLK to output in Hi-z CAS latency = tshz CAS latency = Notes:. s depend on programmed CAS latency.. If clock rising time is longer than, (tr/-.5) should. Assumed input rise and fall time (tr & tf) =. if tr & tf is longer than, traient timecompeation should i.e.,[(tr + tf)/-] should be added to the parameter. be added to the parameter. be coidered, PAGE 7 OF 8

8 Product Specificatio.5 Package Dimeio s : Inches (Millimeters) X.5 (6.5) X. (.6) X.8 (.) X.8 (.).5 (9.).5 (.68) X 5.5 (.5) 5. (7.5) X.89 (.6) X R.5+. (R.7+.) X FULL RADIUS X.57 ±. (. ±.) X.7 (7.78) X.8DIA ±. (.DIA ±.).5 (8.89).5 (6.5).5 (6.8).5 (6.5).5 (5.6).5 (.8).57 (. ) A B C.5 (.).55 (5.57). (.5 ).57 (6.675) FULL RADIUS FULL RADIUS.5 ±.9 (.7 ±.).6 (.75).5 (6.5). ±.5 (.5 ±.5).5 (.75).5 (6.5). ±.5 (.5 ±.5). (.5 ).9 ±. (. ±.5).8 ±.6 (. ±.5) Detail A.79 ±. (. ±.) Tolerances : ±.5(.) unless otherwise specified Revision History: Detail B.79 ±. (. ±.) Detail C.5 (.7) D ate Rev. Page Changes 9 //. 5 All Update datasheet PAGE 8 OF 8